fs: use kmem_cache_zalloc instead
[pv_ops_mirror.git] / include / asm-blackfin / cplb.h
blob06828d77a58ff4c4583da3f71376d942e3fd381c
1 /*
2 * File: include/asm-blackfin/cplb.h
3 * Based on: include/asm-blackfin/mach-bf537/bf537.h
4 * Author: Robin Getz <rgetz@blackfin.uclinux.org>
6 * Created: 2000
7 * Description: Common CPLB definitions for CPLB init
9 * Modified:
10 * Copyright 2004-2007 Analog Devices Inc.
12 * Bugs: Enter bugs at http://blackfin.uclinux.org/
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License as published by
16 * the Free Software Foundation; either version 2 of the License, or
17 * (at your option) any later version.
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
24 * You should have received a copy of the GNU General Public License
25 * along with this program; if not, see the file COPYING, or write
26 * to the Free Software Foundation, Inc.,
27 * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
30 #ifndef _CPLB_H
31 #define _CPLB_H
33 #include <asm/blackfin.h>
34 #include <asm/mach/anomaly.h>
36 #define SDRAM_IGENERIC (CPLB_L1_CHBL | CPLB_USER_RD | CPLB_VALID | CPLB_PORTPRIO)
37 #define SDRAM_IKERNEL (SDRAM_IGENERIC | CPLB_LOCK)
38 #define L1_IMEMORY ( CPLB_USER_RD | CPLB_VALID | CPLB_LOCK)
39 #define SDRAM_INON_CHBL ( CPLB_USER_RD | CPLB_VALID)
41 /*Use the menuconfig cache policy here - CONFIG_BFIN_WT/CONFIG_BFIN_WB*/
43 #if ANOMALY_05000158
44 #define ANOMALY_05000158_WORKAROUND 0x200
45 #else
46 #define ANOMALY_05000158_WORKAROUND 0x0
47 #endif
49 #define CPLB_COMMON (CPLB_DIRTY | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158_WORKAROUND)
51 #ifdef CONFIG_BFIN_WB /*Write Back Policy */
52 #define SDRAM_DGENERIC (CPLB_L1_CHBL | CPLB_COMMON)
53 #else /*Write Through */
54 #define SDRAM_DGENERIC (CPLB_L1_CHBL | CPLB_WT | CPLB_L1_AOW | CPLB_COMMON)
55 #endif
57 #define L1_DMEMORY (CPLB_LOCK | CPLB_COMMON)
58 #define L2_MEMORY (CPLB_COMMON)
59 #define SDRAM_DNON_CHBL (CPLB_COMMON)
60 #define SDRAM_EBIU (CPLB_COMMON)
61 #define SDRAM_OOPS (CPLB_VALID | ANOMALY_05000158_WORKAROUND | CPLB_LOCK | CPLB_DIRTY)
63 #define SIZE_1K 0x00000400 /* 1K */
64 #define SIZE_4K 0x00001000 /* 4K */
65 #define SIZE_1M 0x00100000 /* 1M */
66 #define SIZE_4M 0x00400000 /* 4M */
68 #define MAX_CPLBS (16 * 2)
70 #define ASYNC_MEMORY_CPLB_COVERAGE ((ASYNC_BANK0_SIZE + ASYNC_BANK1_SIZE + \
71 ASYNC_BANK2_SIZE + ASYNC_BANK3_SIZE) / SIZE_4M)
74 * Number of required data CPLB switchtable entries
75 * MEMSIZE / 4 (we mostly install 4M page size CPLBs
76 * approx 16 for smaller 1MB page size CPLBs for allignment purposes
77 * 1 for L1 Data Memory
78 * possibly 1 for L2 Data Memory
79 * 1 for CONFIG_DEBUG_HUNT_FOR_ZERO
80 * 1 for ASYNC Memory
84 #define MAX_SWITCH_D_CPLBS (((CONFIG_MEM_SIZE / 4) + 16 + 1 + 1 + 1 \
85 + ASYNC_MEMORY_CPLB_COVERAGE) * 2)
88 * Number of required instruction CPLB switchtable entries
89 * MEMSIZE / 4 (we mostly install 4M page size CPLBs
90 * approx 12 for smaller 1MB page size CPLBs for allignment purposes
91 * 1 for L1 Instruction Memory
92 * possibly 1 for L2 Instruction Memory
93 * 1 for CONFIG_DEBUG_HUNT_FOR_ZERO
96 #define MAX_SWITCH_I_CPLBS (((CONFIG_MEM_SIZE / 4) + 12 + 1 + 1 + 1) * 2)
99 #define CPLB_ENABLE_ICACHE_P 0
100 #define CPLB_ENABLE_DCACHE_P 1
101 #define CPLB_ENABLE_DCACHE2_P 2
102 #define CPLB_ENABLE_CPLBS_P 3 /* Deprecated! */
103 #define CPLB_ENABLE_ICPLBS_P 4
104 #define CPLB_ENABLE_DCPLBS_P 5
106 #define CPLB_ENABLE_ICACHE (1<<CPLB_ENABLE_ICACHE_P)
107 #define CPLB_ENABLE_DCACHE (1<<CPLB_ENABLE_DCACHE_P)
108 #define CPLB_ENABLE_DCACHE2 (1<<CPLB_ENABLE_DCACHE2_P)
109 #define CPLB_ENABLE_CPLBS (1<<CPLB_ENABLE_CPLBS_P)
110 #define CPLB_ENABLE_ICPLBS (1<<CPLB_ENABLE_ICPLBS_P)
111 #define CPLB_ENABLE_DCPLBS (1<<CPLB_ENABLE_DCPLBS_P)
112 #define CPLB_ENABLE_ANY_CPLBS CPLB_ENABLE_CPLBS | \
113 CPLB_ENABLE_ICPLBS | \
114 CPLB_ENABLE_DCPLBS
116 #define CPLB_RELOADED 0x0000
117 #define CPLB_NO_UNLOCKED 0x0001
118 #define CPLB_NO_ADDR_MATCH 0x0002
119 #define CPLB_PROT_VIOL 0x0003
120 #define CPLB_UNKNOWN_ERR 0x0004
122 #define CPLB_DEF_CACHE CPLB_L1_CHBL | CPLB_WT
123 #define CPLB_CACHE_ENABLED CPLB_L1_CHBL | CPLB_DIRTY
125 #define CPLB_I_PAGE_MGMT CPLB_LOCK | CPLB_VALID
126 #define CPLB_D_PAGE_MGMT CPLB_LOCK | CPLB_ALL_ACCESS | CPLB_VALID
127 #define CPLB_DNOCACHE CPLB_ALL_ACCESS | CPLB_VALID
128 #define CPLB_DDOCACHE CPLB_DNOCACHE | CPLB_DEF_CACHE
129 #define CPLB_INOCACHE CPLB_USER_RD | CPLB_VALID
130 #define CPLB_IDOCACHE CPLB_INOCACHE | CPLB_L1_CHBL
132 #endif /* _CPLB_H */