fs: use kmem_cache_zalloc instead
[pv_ops_mirror.git] / include / asm-blackfin / cplbinit.h
blobbec6ecdf1bdbc5cd23a5421c28f194132fbaa9f6
1 /*
2 * File: include/asm-blackfin/cplbinit.h
3 * Based on:
4 * Author:
6 * Created:
7 * Description:
9 * Modified:
10 * Copyright 2004-2006 Analog Devices Inc.
12 * Bugs: Enter bugs at http://blackfin.uclinux.org/
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License as published by
16 * the Free Software Foundation; either version 2 of the License, or
17 * (at your option) any later version.
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
24 * You should have received a copy of the GNU General Public License
25 * along with this program; if not, see the file COPYING, or write
26 * to the Free Software Foundation, Inc.,
27 * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
30 #include <asm/blackfin.h>
31 #include <asm/cplb.h>
33 #define INITIAL_T 0x1
34 #define SWITCH_T 0x2
35 #define I_CPLB 0x4
36 #define D_CPLB 0x8
38 #define IN_KERNEL 1
40 enum
41 {ZERO_P, L1I_MEM, L1D_MEM, SDRAM_KERN , SDRAM_RAM_MTD, SDRAM_DMAZ, RES_MEM, ASYNC_MEM, L2_MEM};
43 struct cplb_desc {
44 u32 start; /* start address */
45 u32 end; /* end address */
46 u32 psize; /* prefered size if any otherwise 1MB or 4MB*/
47 u16 attr;/* attributes */
48 u16 i_conf;/* I-CPLB DATA */
49 u16 d_conf;/* D-CPLB DATA */
50 u16 valid;/* valid */
51 const s8 name[30];/* name */
54 struct cplb_tab {
55 u_long *tab;
56 u16 pos;
57 u16 size;
60 extern u_long icplb_table[MAX_CPLBS+1];
61 extern u_long dcplb_table[MAX_CPLBS+1];
63 /* Till here we are discussing about the static memory management model.
64 * However, the operating envoronments commonly define more CPLB
65 * descriptors to cover the entire addressable memory than will fit into
66 * the available on-chip 16 CPLB MMRs. When this happens, the below table
67 * will be used which will hold all the potentially required CPLB descriptors
69 * This is how Page descriptor Table is implemented in uClinux/Blackfin.
72 #ifdef CONFIG_CPLB_SWITCH_TAB_L1
73 extern u_long ipdt_table[MAX_SWITCH_I_CPLBS+1]__attribute__((l1_data));
74 extern u_long dpdt_table[MAX_SWITCH_D_CPLBS+1]__attribute__((l1_data));
76 #ifdef CONFIG_CPLB_INFO
77 extern u_long ipdt_swapcount_table[MAX_SWITCH_I_CPLBS]__attribute__((l1_data));
78 extern u_long dpdt_swapcount_table[MAX_SWITCH_D_CPLBS]__attribute__((l1_data));
79 #endif /* CONFIG_CPLB_INFO */
81 #else
83 extern u_long ipdt_table[MAX_SWITCH_I_CPLBS+1];
84 extern u_long dpdt_table[MAX_SWITCH_D_CPLBS+1];
86 #ifdef CONFIG_CPLB_INFO
87 extern u_long ipdt_swapcount_table[MAX_SWITCH_I_CPLBS];
88 extern u_long dpdt_swapcount_table[MAX_SWITCH_D_CPLBS];
89 #endif /* CONFIG_CPLB_INFO */
91 #endif /*CONFIG_CPLB_SWITCH_TAB_L1*/
93 extern unsigned long reserved_mem_dcache_on;
94 extern unsigned long reserved_mem_icache_on;
96 extern void generate_cpl_tables(void);