fs: use kmem_cache_zalloc instead
[pv_ops_mirror.git] / include / asm-blackfin / traps.h
blobfe365b1b7ca8085cc54acf8197618aca85aa192c
1 /*
2 * linux/include/asm/traps.h
4 * Copyright (C) 1993 Hamish Macdonald
6 * Lineo, Inc Jul 2001 Tony Kou
8 * This file is subject to the terms and conditions of the GNU General Public
9 * License. See the file COPYING in the main directory of this archive
10 * for more details.
13 #ifndef _BFIN_TRAPS_H
14 #define _BFIN_TRAPS_H
16 #define VEC_SYS (0)
17 #define VEC_EXCPT01 (1)
18 #define VEC_EXCPT02 (2)
19 #define VEC_EXCPT03 (3)
20 #define VEC_EXCPT04 (4)
21 #define VEC_EXCPT05 (5)
22 #define VEC_EXCPT06 (6)
23 #define VEC_EXCPT07 (7)
24 #define VEC_EXCPT08 (8)
25 #define VEC_EXCPT09 (9)
26 #define VEC_EXCPT10 (10)
27 #define VEC_EXCPT11 (11)
28 #define VEC_EXCPT12 (12)
29 #define VEC_EXCPT13 (13)
30 #define VEC_EXCPT14 (14)
31 #define VEC_EXCPT15 (15)
32 #define VEC_STEP (16)
33 #define VEC_OVFLOW (17)
34 #define VEC_UNDEF_I (33)
35 #define VEC_ILGAL_I (34)
36 #define VEC_CPLB_VL (35)
37 #define VEC_MISALI_D (36)
38 #define VEC_UNCOV (37)
39 #define VEC_CPLB_M (38)
40 #define VEC_CPLB_MHIT (39)
41 #define VEC_WATCH (40)
42 #define VEC_ISTRU_VL (41) /*ADSP-BF535 only (MH) */
43 #define VEC_MISALI_I (42)
44 #define VEC_CPLB_I_VL (43)
45 #define VEC_CPLB_I_M (44)
46 #define VEC_CPLB_I_MHIT (45)
47 #define VEC_ILL_RES (46) /* including unvalid supervisor mode insn */
49 #ifndef __ASSEMBLY__
51 #define HWC_x2 "System MMR Error\nAn error occurred due to an invalid access to an System MMR location\nPossible reason: a 32-bit register is accessed with a 16-bit instruction,\nor a 16-bit register is accessed with a 32-bit instruction.\n"
52 #define HWC_x3 "External Memory Addressing Error\n"
53 #define HWC_x12 "Performance Monitor Overflow\n"
54 #define HWC_x18 "RAISE 5 instruction\n Software issued a RAISE 5 instruction to invoke the Hardware\n"
55 #define HWC_default "Reserved\n"
57 #define EXC_0x03 "Application stack overflow\n - Please increase the stack size of the application using elf2flt -s option,\n and/or reduce the stack use of the application.\n"
58 #define EXC_0x10 "Single step\n - When the processor is in single step mode, every instruction\n generates an exception. Primarily used for debugging.\n"
59 #define EXC_0x11 "Exception caused by a trace buffer full condition\n - The processor takes this exception when the trace\n buffer overflows (only when enabled by the Trace Unit Control register).\n"
60 #define EXC_0x21 "Undefined instruction\n - May be used to emulate instructions that are not defined for\n a particular processor implementation.\n"
61 #define EXC_0x22 "Illegal instruction combination\n - See section for multi-issue rules in the ADSP-BF53x Blackfin\n Processor Instruction Set Reference.\n"
62 #define EXC_0x23 "Data access CPLB protection violation\n - Attempted read or write to Supervisor resource,\n or illegal data memory access. \n"
63 #define EXC_0x24 "Data access misaligned address violation\n - Attempted misaligned data memory or data cache access.\n"
64 #define EXC_0x25 "Unrecoverable event\n - For example, an exception generated while processing a previous exception.\n"
65 #define EXC_0x26 "Data access CPLB miss\n - Used by the MMU to signal a CPLB miss on a data access.\n"
66 #define EXC_0x27 "Data access multiple CPLB hits\n - More than one CPLB entry matches data fetch address.\n"
67 #define EXC_0x28 "Program Sequencer Exception caused by an emulation watchpoint match\n - There is a watchpoint match, and one of the EMUSW\n bits in the Watchpoint Instruction Address Control register (WPIACTL) is set.\n"
68 #define EXC_0x2A "Instruction fetch misaligned address violation\n - Attempted misaligned instruction cache fetch. On a misaligned instruction fetch exception,\n the return address provided in RETX is the destination address which is misaligned, rather than the address of the offending instruction.\n"
69 #define EXC_0x2B "CPLB protection violation\n - Illegal instruction fetch access (memory protection violation).\n"
70 #define EXC_0x2C "Instruction fetch CPLB miss\n - CPLB miss on an instruction fetch.\n"
71 #define EXC_0x2D "Instruction fetch multiple CPLB hits\n - More than one CPLB entry matches instruction fetch address.\n"
72 #define EXC_0x2E "Illegal use of supervisor resource\n - Attempted to use a Supervisor register or instruction from User mode.\n Supervisor resources are registers and instructions that are reserved\n for Supervisor use: Supervisor only registers, all MMRs, and Supervisor\n only instructions.\n"
74 #endif /* __ASSEMBLY__ */
75 #endif /* _BFIN_TRAPS_H */