fs: use kmem_cache_zalloc instead
[pv_ops_mirror.git] / include / asm-m32r / ptrace.h
bloba0755b9820287901020b07757e9cc8acf521622f
1 #ifndef _ASM_M32R_PTRACE_H
2 #define _ASM_M32R_PTRACE_H
4 /*
5 * linux/include/asm-m32r/ptrace.h
7 * This file is subject to the terms and conditions of the GNU General Public
8 * License. See the file "COPYING" in the main directory of this archive
9 * for more details.
11 * M32R version:
12 * Copyright (C) 2001-2002, 2004 Hirokazu Takata <takata at linux-m32r.org>
15 /* 0 - 13 are integer registers (general purpose registers). */
16 #define PT_R4 0
17 #define PT_R5 1
18 #define PT_R6 2
19 #define PT_REGS 3
20 #define PT_R0 4
21 #define PT_R1 5
22 #define PT_R2 6
23 #define PT_R3 7
24 #define PT_R7 8
25 #define PT_R8 9
26 #define PT_R9 10
27 #define PT_R10 11
28 #define PT_R11 12
29 #define PT_R12 13
30 #define PT_SYSCNR 14
31 #define PT_R13 PT_FP
32 #define PT_R14 PT_LR
33 #define PT_R15 PT_SP
35 /* processor status and miscellaneous context registers. */
36 #define PT_ACC0H 15
37 #define PT_ACC0L 16
38 #define PT_ACC1H 17 /* ISA_DSP_LEVEL2 only */
39 #define PT_ACC1L 18 /* ISA_DSP_LEVEL2 only */
40 #define PT_PSW 19
41 #define PT_BPC 20
42 #define PT_BBPSW 21
43 #define PT_BBPC 22
44 #define PT_SPU 23
45 #define PT_FP 24
46 #define PT_LR 25
47 #define PT_SPI 26
48 #define PT_ORIGR0 27
50 /* virtual pt_reg entry for gdb */
51 #define PT_PC 30
52 #define PT_CBR 31
53 #define PT_EVB 32
56 /* Control registers. */
57 #define SPR_CR0 PT_PSW
58 #define SPR_CR1 PT_CBR /* read only */
59 #define SPR_CR2 PT_SPI
60 #define SPR_CR3 PT_SPU
61 #define SPR_CR4
62 #define SPR_CR5 PT_EVB /* part of M32R/E, M32R/I core only */
63 #define SPR_CR6 PT_BPC
64 #define SPR_CR7
65 #define SPR_CR8 PT_BBPSW
66 #define SPR_CR9
67 #define SPR_CR10
68 #define SPR_CR11
69 #define SPR_CR12
70 #define SPR_CR13 PT_WR
71 #define SPR_CR14 PT_BBPC
72 #define SPR_CR15
74 /* this struct defines the way the registers are stored on the
75 stack during a system call. */
76 struct pt_regs {
77 /* Saved main processor registers. */
78 unsigned long r4;
79 unsigned long r5;
80 unsigned long r6;
81 struct pt_regs *pt_regs;
82 unsigned long r0;
83 unsigned long r1;
84 unsigned long r2;
85 unsigned long r3;
86 unsigned long r7;
87 unsigned long r8;
88 unsigned long r9;
89 unsigned long r10;
90 unsigned long r11;
91 unsigned long r12;
92 long syscall_nr;
94 /* Saved main processor status and miscellaneous context registers. */
95 unsigned long acc0h;
96 unsigned long acc0l;
97 unsigned long acc1h; /* ISA_DSP_LEVEL2 only */
98 unsigned long acc1l; /* ISA_DSP_LEVEL2 only */
99 unsigned long psw;
100 unsigned long bpc; /* saved PC for TRAP syscalls */
101 unsigned long bbpsw;
102 unsigned long bbpc;
103 unsigned long spu; /* saved user stack */
104 unsigned long fp;
105 unsigned long lr; /* saved PC for JL syscalls */
106 unsigned long spi; /* saved kernel stack */
107 unsigned long orig_r0;
110 /* Arbitrarily choose the same ptrace numbers as used by the Sparc code. */
111 #define PTRACE_GETREGS 12
112 #define PTRACE_SETREGS 13
114 #define PTRACE_OLDSETOPTIONS 21
116 /* options set using PTRACE_SETOPTIONS */
117 #define PTRACE_O_TRACESYSGOOD 0x00000001
119 #ifdef __KERNEL__
121 #include <asm/m32r.h> /* M32R_PSW_BSM, M32R_PSW_BPM */
123 struct task_struct;
124 extern void init_debug_traps(struct task_struct *);
125 #define arch_ptrace_attach(child) \
126 init_debug_traps(child)
128 #if defined(CONFIG_ISA_M32R2) || defined(CONFIG_CHIP_VDEC2)
129 #define user_mode(regs) ((M32R_PSW_BPM & (regs)->psw) != 0)
130 #elif defined(CONFIG_ISA_M32R)
131 #define user_mode(regs) ((M32R_PSW_BSM & (regs)->psw) != 0)
132 #else
133 #error unknown isa configuration
134 #endif
136 #define instruction_pointer(regs) ((regs)->bpc)
137 #define profile_pc(regs) instruction_pointer(regs)
139 extern void show_regs(struct pt_regs *);
141 extern void withdraw_debug_trap(struct pt_regs *regs);
143 #define task_pt_regs(task) \
144 ((struct pt_regs *)(task_stack_page(task) + THREAD_SIZE) - 1)
146 #endif /* __KERNEL */
148 #endif /* _ASM_M32R_PTRACE_H */