fs: use kmem_cache_zalloc instead
[pv_ops_mirror.git] / include / asm-m68knommu / system.h
blob1bd1142685e18f5dd916c0dcf838fe1e3c2435df
1 #ifndef _M68KNOMMU_SYSTEM_H
2 #define _M68KNOMMU_SYSTEM_H
4 #include <linux/linkage.h>
5 #include <asm/segment.h>
6 #include <asm/entry.h>
8 /*
9 * switch_to(n) should switch tasks to task ptr, first checking that
10 * ptr isn't the current task, in which case it does nothing. This
11 * also clears the TS-flag if the task we switched to has used the
12 * math co-processor latest.
15 * switch_to() saves the extra registers, that are not saved
16 * automatically by SAVE_SWITCH_STACK in resume(), ie. d0-d5 and
17 * a0-a1. Some of these are used by schedule() and its predecessors
18 * and so we might get see unexpected behaviors when a task returns
19 * with unexpected register values.
21 * syscall stores these registers itself and none of them are used
22 * by syscall after the function in the syscall has been called.
24 * Beware that resume now expects *next to be in d1 and the offset of
25 * tss to be in a1. This saves a few instructions as we no longer have
26 * to push them onto the stack and read them back right after.
28 * 02/17/96 - Jes Sorensen (jds@kom.auc.dk)
30 * Changed 96/09/19 by Andreas Schwab
31 * pass prev in a0, next in a1, offset of tss in d1, and whether
32 * the mm structures are shared in d2 (to avoid atc flushing).
34 asmlinkage void resume(void);
35 #define switch_to(prev,next,last) \
36 { \
37 void *_last; \
38 __asm__ __volatile__( \
39 "movel %1, %%a0\n\t" \
40 "movel %2, %%a1\n\t" \
41 "jbsr resume\n\t" \
42 "movel %%d1, %0\n\t" \
43 : "=d" (_last) \
44 : "d" (prev), "d" (next) \
45 : "cc", "d0", "d1", "d2", "d3", "d4", "d5", "a0", "a1"); \
46 (last) = _last; \
49 #ifdef CONFIG_COLDFIRE
50 #define local_irq_enable() __asm__ __volatile__ ( \
51 "move %/sr,%%d0\n\t" \
52 "andi.l #0xf8ff,%%d0\n\t" \
53 "move %%d0,%/sr\n" \
54 : /* no outputs */ \
55 : \
56 : "cc", "%d0", "memory")
57 #define local_irq_disable() __asm__ __volatile__ ( \
58 "move %/sr,%%d0\n\t" \
59 "ori.l #0x0700,%%d0\n\t" \
60 "move %%d0,%/sr\n" \
61 : /* no outputs */ \
62 : \
63 : "cc", "%d0", "memory")
64 /* For spinlocks etc */
65 #define local_irq_save(x) __asm__ __volatile__ ( \
66 "movew %%sr,%0\n\t" \
67 "movew #0x0700,%%d0\n\t" \
68 "or.l %0,%%d0\n\t" \
69 "movew %%d0,%/sr" \
70 : "=d" (x) \
71 : \
72 : "cc", "%d0", "memory")
73 #else
75 /* portable version */ /* FIXME - see entry.h*/
76 #define ALLOWINT 0xf8ff
78 #define local_irq_enable() asm volatile ("andiw %0,%%sr": : "i" (ALLOWINT) : "memory")
79 #define local_irq_disable() asm volatile ("oriw #0x0700,%%sr": : : "memory")
80 #endif
82 #define local_save_flags(x) asm volatile ("movew %%sr,%0":"=d" (x) : : "memory")
83 #define local_irq_restore(x) asm volatile ("movew %0,%%sr": :"d" (x) : "memory")
85 /* For spinlocks etc */
86 #ifndef local_irq_save
87 #define local_irq_save(x) do { local_save_flags(x); local_irq_disable(); } while (0)
88 #endif
90 #define irqs_disabled() \
91 ({ \
92 unsigned long flags; \
93 local_save_flags(flags); \
94 ((flags & 0x0700) == 0x0700); \
97 #define iret() __asm__ __volatile__ ("rte": : :"memory", "sp", "cc")
100 * Force strict CPU ordering.
101 * Not really required on m68k...
103 #define nop() asm volatile ("nop"::)
104 #define mb() asm volatile ("" : : :"memory")
105 #define rmb() asm volatile ("" : : :"memory")
106 #define wmb() asm volatile ("" : : :"memory")
107 #define set_rmb(var, value) do { xchg(&var, value); } while (0)
108 #define set_mb(var, value) set_rmb(var, value)
110 #ifdef CONFIG_SMP
111 #define smp_mb() mb()
112 #define smp_rmb() rmb()
113 #define smp_wmb() wmb()
114 #define smp_read_barrier_depends() read_barrier_depends()
115 #else
116 #define smp_mb() barrier()
117 #define smp_rmb() barrier()
118 #define smp_wmb() barrier()
119 #define smp_read_barrier_depends() do { } while(0)
120 #endif
122 #define xchg(ptr,x) ((__typeof__(*(ptr)))__xchg((unsigned long)(x),(ptr),sizeof(*(ptr))))
124 struct __xchg_dummy { unsigned long a[100]; };
125 #define __xg(x) ((volatile struct __xchg_dummy *)(x))
127 #ifndef CONFIG_RMW_INSNS
128 static inline unsigned long __xchg(unsigned long x, volatile void * ptr, int size)
130 unsigned long tmp, flags;
132 local_irq_save(flags);
134 switch (size) {
135 case 1:
136 __asm__ __volatile__
137 ("moveb %2,%0\n\t"
138 "moveb %1,%2"
139 : "=&d" (tmp) : "d" (x), "m" (*__xg(ptr)) : "memory");
140 break;
141 case 2:
142 __asm__ __volatile__
143 ("movew %2,%0\n\t"
144 "movew %1,%2"
145 : "=&d" (tmp) : "d" (x), "m" (*__xg(ptr)) : "memory");
146 break;
147 case 4:
148 __asm__ __volatile__
149 ("movel %2,%0\n\t"
150 "movel %1,%2"
151 : "=&d" (tmp) : "d" (x), "m" (*__xg(ptr)) : "memory");
152 break;
154 local_irq_restore(flags);
155 return tmp;
157 #else
158 static inline unsigned long __xchg(unsigned long x, volatile void * ptr, int size)
160 switch (size) {
161 case 1:
162 __asm__ __volatile__
163 ("moveb %2,%0\n\t"
164 "1:\n\t"
165 "casb %0,%1,%2\n\t"
166 "jne 1b"
167 : "=&d" (x) : "d" (x), "m" (*__xg(ptr)) : "memory");
168 break;
169 case 2:
170 __asm__ __volatile__
171 ("movew %2,%0\n\t"
172 "1:\n\t"
173 "casw %0,%1,%2\n\t"
174 "jne 1b"
175 : "=&d" (x) : "d" (x), "m" (*__xg(ptr)) : "memory");
176 break;
177 case 4:
178 __asm__ __volatile__
179 ("movel %2,%0\n\t"
180 "1:\n\t"
181 "casl %0,%1,%2\n\t"
182 "jne 1b"
183 : "=&d" (x) : "d" (x), "m" (*__xg(ptr)) : "memory");
184 break;
186 return x;
188 #endif
191 * Atomic compare and exchange. Compare OLD with MEM, if identical,
192 * store NEW in MEM. Return the initial value in MEM. Success is
193 * indicated by comparing RETURN with OLD.
195 #define __HAVE_ARCH_CMPXCHG 1
197 static __inline__ unsigned long
198 cmpxchg(volatile int *p, int old, int new)
200 unsigned long flags;
201 int prev;
203 local_irq_save(flags);
204 if ((prev = *p) == old)
205 *p = new;
206 local_irq_restore(flags);
207 return(prev);
211 #ifdef CONFIG_M68332
212 #define HARD_RESET_NOW() ({ \
213 local_irq_disable(); \
214 asm(" \
215 movew #0x0000, 0xfffa6a; \
216 reset; \
217 /*movew #0x1557, 0xfffa44;*/ \
218 /*movew #0x0155, 0xfffa46;*/ \
219 moveal #0, %a0; \
220 movec %a0, %vbr; \
221 moveal 0, %sp; \
222 moveal 4, %a0; \
223 jmp (%a0); \
224 "); \
226 #endif
228 #if defined( CONFIG_M68328 ) || defined( CONFIG_M68EZ328 ) || \
229 defined (CONFIG_M68360) || defined( CONFIG_M68VZ328 )
230 #define HARD_RESET_NOW() ({ \
231 local_irq_disable(); \
232 asm(" \
233 moveal #0x10c00000, %a0; \
234 moveb #0, 0xFFFFF300; \
235 moveal 0(%a0), %sp; \
236 moveal 4(%a0), %a0; \
237 jmp (%a0); \
238 "); \
240 #endif
242 #ifdef CONFIG_COLDFIRE
243 #if defined(CONFIG_M5272) && defined(CONFIG_NETtel)
245 * Need to account for broken early mask of 5272 silicon. So don't
246 * jump through the original start address. Jump strait into the
247 * known start of the FLASH code.
249 #define HARD_RESET_NOW() ({ \
250 asm(" \
251 movew #0x2700, %sr; \
252 jmp 0xf0000400; \
253 "); \
255 #elif defined(CONFIG_NETtel) || defined(CONFIG_eLIA) || \
256 defined(CONFIG_SECUREEDGEMP3) || defined(CONFIG_CLEOPATRA)
257 #define HARD_RESET_NOW() ({ \
258 asm(" \
259 movew #0x2700, %sr; \
260 moveal #0x10000044, %a0; \
261 movel #0xffffffff, (%a0); \
262 moveal #0x10000001, %a0; \
263 moveb #0x00, (%a0); \
264 moveal #0xf0000004, %a0; \
265 moveal (%a0), %a0; \
266 jmp (%a0); \
267 "); \
269 #elif defined(CONFIG_M5272)
271 * Retrieve the boot address in flash using CSBR0 and CSOR0
272 * find the reset vector at flash_address + 4 (e.g. 0x400)
273 * remap it in the flash's current location (e.g. 0xf0000400)
274 * and jump there.
276 #define HARD_RESET_NOW() ({ \
277 asm(" \
278 movew #0x2700, %%sr; \
279 move.l %0+0x40,%%d0; \
280 and.l %0+0x44,%%d0; \
281 andi.l #0xfffff000,%%d0; \
282 mov.l %%d0,%%a0; \
283 or.l 4(%%a0),%%d0; \
284 mov.l %%d0,%%a0; \
285 jmp (%%a0);" \
286 : /* No output */ \
287 : "o" (*(char *)MCF_MBAR) ); \
289 #elif defined(CONFIG_M528x)
291 * The MCF528x has a bit (SOFTRST) in memory (Reset Control Register RCR),
292 * that when set, resets the MCF528x.
294 #define HARD_RESET_NOW() \
295 ({ \
296 unsigned char volatile *reset; \
297 asm("move.w #0x2700, %sr"); \
298 reset = ((volatile unsigned char *)(MCF_IPSBAR + 0x110000)); \
299 while(1) \
300 *reset |= (0x01 << 7);\
302 #elif defined(CONFIG_M523x)
303 #define HARD_RESET_NOW() ({ \
304 asm(" \
305 movew #0x2700, %sr; \
306 movel #0x01000000, %sp; \
307 moveal #0x40110000, %a0; \
308 moveb #0x80, (%a0); \
309 "); \
311 #elif defined(CONFIG_M520x)
313 * The MCF5208 has a bit (SOFTRST) in memory (Reset Control Register
314 * RCR), that when set, resets the MCF5208.
316 #define HARD_RESET_NOW() \
317 ({ \
318 unsigned char volatile *reset; \
319 asm("move.w #0x2700, %sr"); \
320 reset = ((volatile unsigned char *)(MCF_IPSBAR + 0xA0000)); \
321 while(1) \
322 *reset |= 0x80; \
324 #else
325 #define HARD_RESET_NOW() ({ \
326 asm(" \
327 movew #0x2700, %sr; \
328 moveal #0x4, %a0; \
329 moveal (%a0), %a0; \
330 jmp (%a0); \
331 "); \
333 #endif
334 #endif
335 #define arch_align_stack(x) (x)
337 #endif /* _M68KNOMMU_SYSTEM_H */