fs: use kmem_cache_zalloc instead
[pv_ops_mirror.git] / include / asm-sh / se7343.h
blobe7914a54aa96f285b30d1882b9e93f128ac85f96
1 #ifndef __ASM_SH_HITACHI_SE7343_H
2 #define __ASM_SH_HITACHI_SE7343_H
4 /*
5 * include/asm-sh/se/se7343.h
7 * Copyright (C) 2003 Takashi Kusuda <kusuda-takashi@hitachi-ul.co.jp>
9 * SH-Mobile SolutionEngine 7343 support
12 /* Box specific addresses. */
14 /* Area 0 */
15 #define PA_ROM 0x00000000 /* EPROM */
16 #define PA_ROM_SIZE 0x00400000 /* EPROM size 4M byte(Actually 2MB) */
17 #define PA_FROM 0x00400000 /* Flash ROM */
18 #define PA_FROM_SIZE 0x00400000 /* Flash size 4M byte */
19 #define PA_SRAM 0x00800000 /* SRAM */
20 #define PA_FROM_SIZE 0x00400000 /* SRAM size 4M byte */
21 /* Area 1 */
22 #define PA_EXT1 0x04000000
23 #define PA_EXT1_SIZE 0x04000000
24 /* Area 2 */
25 #define PA_EXT2 0x08000000
26 #define PA_EXT2_SIZE 0x04000000
27 /* Area 3 */
28 #define PA_SDRAM 0x0c000000
29 #define PA_SDRAM_SIZE 0x04000000
30 /* Area 4 */
31 #define PA_PCIC 0x10000000 /* MR-SHPC-01 PCMCIA */
32 #define PA_MRSHPC 0xb03fffe0 /* MR-SHPC-01 PCMCIA controller */
33 #define PA_MRSHPC_MW1 0xb0400000 /* MR-SHPC-01 memory window base */
34 #define PA_MRSHPC_MW2 0xb0500000 /* MR-SHPC-01 attribute window base */
35 #define PA_MRSHPC_IO 0xb0600000 /* MR-SHPC-01 I/O window base */
36 #define MRSHPC_OPTION (PA_MRSHPC + 6)
37 #define MRSHPC_CSR (PA_MRSHPC + 8)
38 #define MRSHPC_ISR (PA_MRSHPC + 10)
39 #define MRSHPC_ICR (PA_MRSHPC + 12)
40 #define MRSHPC_CPWCR (PA_MRSHPC + 14)
41 #define MRSHPC_MW0CR1 (PA_MRSHPC + 16)
42 #define MRSHPC_MW1CR1 (PA_MRSHPC + 18)
43 #define MRSHPC_IOWCR1 (PA_MRSHPC + 20)
44 #define MRSHPC_MW0CR2 (PA_MRSHPC + 22)
45 #define MRSHPC_MW1CR2 (PA_MRSHPC + 24)
46 #define MRSHPC_IOWCR2 (PA_MRSHPC + 26)
47 #define MRSHPC_CDCR (PA_MRSHPC + 28)
48 #define MRSHPC_PCIC_INFO (PA_MRSHPC + 30)
49 #define PA_LED 0xb0C00000 /* LED */
50 #define LED_SHIFT 0
51 #define PA_DIPSW 0xb0900000 /* Dip switch 31 */
52 #define PA_CPLD_MODESET 0xb1400004 /* CPLD Mode set register */
53 #define PA_CPLD_ST 0xb1400008 /* CPLD Interrupt status register */
54 #define PA_CPLD_IMSK 0xb140000a /* CPLD Interrupt mask register */
55 /* Area 5 */
56 #define PA_EXT5 0x14000000
57 #define PA_EXT5_SIZE 0x04000000
58 /* Area 6 */
59 #define PA_LCD1 0xb8000000
60 #define PA_LCD2 0xb8800000
62 #define __IO_PREFIX sh7343se
63 #include <asm/io_generic.h>
65 /* External Multiplexed interrupts */
66 #define PC_IRQ0 OFFCHIP_IRQ_BASE
67 #define PC_IRQ1 (PC_IRQ0 + 1)
68 #define PC_IRQ2 (PC_IRQ1 + 1)
69 #define PC_IRQ3 (PC_IRQ2 + 1)
71 #define EXT_IRQ0 (PC_IRQ3 + 1)
72 #define EXT_IRQ1 (EXT_IRQ0 + 1)
73 #define EXT_IRQ2 (EXT_IRQ1 + 1)
74 #define EXT_IRQ3 (EXT_IRQ2 + 1)
76 #define USB_IRQ0 (EXT_IRQ3 + 1)
77 #define USB_IRQ1 (USB_IRQ0 + 1)
79 #define UART_IRQ0 (USB_IRQ1 + 1)
80 #define UART_IRQ1 (UART_IRQ0 + 1)
82 #endif /* __ASM_SH_HITACHI_SE7343_H */