1 /* $Id: system.h,v 1.86 2001/10/30 04:57:10 davem Exp $ */
3 #ifndef __SPARC_SYSTEM_H
4 #define __SPARC_SYSTEM_H
6 #include <linux/kernel.h>
7 #include <linux/threads.h> /* NR_CPUS */
8 #include <linux/thread_info.h>
12 #include <asm/ptrace.h>
13 #include <asm/btfixup.h>
18 #include <linux/irqflags.h>
21 * Sparc (general) CPU types
29 sun4u
= 0x05, /* V8 ploos ploos */
31 ap1000
= 0x07, /* almost a sun4m */
34 /* Really, userland should not be looking at any of this... */
37 extern enum sparc_cpu sparc_cpu_model
;
40 #define ARCH_SUN4C_SUN4 (sparc_cpu_model==sun4c)
43 #define ARCH_SUN4C_SUN4 1
47 #define SUN4M_NCPUS 4 /* Architectural limit of sun4m. */
49 extern struct thread_info
*current_set
[NR_CPUS
];
51 extern unsigned long empty_bad_page
;
52 extern unsigned long empty_bad_page_table
;
53 extern unsigned long empty_zero_page
;
55 extern void sun_do_break(void);
56 extern int serial_console
;
57 extern int stop_a_enabled
;
59 static __inline__
int con_is_present(void)
61 return serial_console
? 0 : 1;
64 /* When a context switch happens we must flush all user windows so that
65 * the windows of the current process are flushed onto its stack. This
66 * way the windows are all clean for the next process and the stack
67 * frames are up to date.
69 extern void flush_user_windows(void);
70 extern void kill_user_windows(void);
71 extern void synchronize_user_stack(void);
72 extern void fpsave(unsigned long *fpregs
, unsigned long *fsr
,
73 void *fpqueue
, unsigned long *fpqdepth
);
76 #define SWITCH_ENTER(prv) \
78 if (test_tsk_thread_flag(prv, TIF_USEDFPU)) { \
79 put_psr(get_psr() | PSR_EF); \
80 fpsave(&(prv)->thread.float_regs[0], &(prv)->thread.fsr, \
81 &(prv)->thread.fpqueue[0], &(prv)->thread.fpqdepth); \
82 clear_tsk_thread_flag(prv, TIF_USEDFPU); \
83 (prv)->thread.kregs->psr &= ~PSR_EF; \
87 #define SWITCH_DO_LAZY_FPU(next) /* */
89 #define SWITCH_ENTER(prv) /* */
90 #define SWITCH_DO_LAZY_FPU(nxt) \
92 if (last_task_used_math != (nxt)) \
93 (nxt)->thread.kregs->psr&=~PSR_EF; \
98 * Flush windows so that the VM switch which follows
99 * would not pull the stack from under us.
101 * SWITCH_ENTER and SWITH_DO_LAZY_FPU do not work yet (e.g. SMP does not work)
102 * XXX WTF is the above comment? Found in late teen 2.4.x.
104 #define prepare_arch_switch(next) do { \
105 __asm__ __volatile__( \
106 ".globl\tflush_patch_switch\nflush_patch_switch:\n\t" \
107 "save %sp, -0x40, %sp; save %sp, -0x40, %sp; save %sp, -0x40, %sp\n\t" \
108 "save %sp, -0x40, %sp; save %sp, -0x40, %sp; save %sp, -0x40, %sp\n\t" \
109 "save %sp, -0x40, %sp\n\t" \
110 "restore; restore; restore; restore; restore; restore; restore"); \
113 /* Much care has gone into this code, do not touch it.
115 * We need to loadup regs l0/l1 for the newly forked child
116 * case because the trap return path relies on those registers
117 * holding certain values, gcc is told that they are clobbered.
118 * Gcc needs registers for 3 values in and 1 value out, so we
119 * clobber every non-fixed-usage register besides l2/l3/o4/o5. -DaveM
121 * Hey Dave, that do not touch sign is too much of an incentive
124 #define switch_to(prev, next, last) do { \
125 SWITCH_ENTER(prev); \
126 SWITCH_DO_LAZY_FPU(next); \
127 cpu_set(smp_processor_id(), next->active_mm->cpu_vm_mask); \
128 __asm__ __volatile__( \
129 "sethi %%hi(here - 0x8), %%o7\n\t" \
130 "mov %%g6, %%g3\n\t" \
131 "or %%o7, %%lo(here - 0x8), %%o7\n\t" \
132 "rd %%psr, %%g4\n\t" \
133 "std %%sp, [%%g6 + %4]\n\t" \
134 "rd %%wim, %%g5\n\t" \
135 "wr %%g4, 0x20, %%psr\n\t" \
137 "std %%g4, [%%g6 + %3]\n\t" \
138 "ldd [%2 + %3], %%g4\n\t" \
140 ".globl patchme_store_new_current\n" \
141 "patchme_store_new_current:\n\t" \
143 "wr %%g4, 0x20, %%psr\n\t" \
146 "nop\n\t" /* LEON needs all 3 nops: load to %sp depends on CWP. */ \
147 "ldd [%%g6 + %4], %%sp\n\t" \
148 "wr %%g5, 0x0, %%wim\n\t" \
149 "ldd [%%sp + 0x00], %%l0\n\t" \
150 "ldd [%%sp + 0x38], %%i6\n\t" \
151 "wr %%g4, 0x0, %%psr\n\t" \
154 "jmpl %%o7 + 0x8, %%g0\n\t" \
155 " ld [%%g3 + %5], %0\n\t" \
158 : "r" (&(current_set[hard_smp_processor_id()])), \
159 "r" (task_thread_info(next)), \
163 : "g1", "g2", "g3", "g4", "g5", "g7", \
164 "l0", "l1", "l3", "l4", "l5", "l6", "l7", \
165 "i0", "i1", "i2", "i3", "i4", "i5", \
166 "o0", "o1", "o2", "o3", "o7"); \
169 /* XXX Change this if we ever use a PSO mode kernel. */
170 #define mb() __asm__ __volatile__ ("" : : : "memory")
173 #define read_barrier_depends() do { } while(0)
174 #define set_mb(__var, __value) do { __var = __value; mb(); } while(0)
175 #define smp_mb() __asm__ __volatile__("":::"memory")
176 #define smp_rmb() __asm__ __volatile__("":::"memory")
177 #define smp_wmb() __asm__ __volatile__("":::"memory")
178 #define smp_read_barrier_depends() do { } while(0)
180 #define nop() __asm__ __volatile__ ("nop")
182 /* This has special calling conventions */
184 BTFIXUPDEF_CALL(void, ___xchg32
, void)
187 static inline unsigned long xchg_u32(__volatile__
unsigned long *m
, unsigned long val
)
190 __asm__
__volatile__("swap [%2], %0"
196 register unsigned long *ptr
asm("g1");
197 register unsigned long ret
asm("g2");
199 ptr
= (unsigned long *) m
;
202 /* Note: this is magic and the nop there is
204 __asm__
__volatile__(
206 "call ___f____xchg32\n\t"
209 : "0" (ret
), "r" (ptr
)
210 : "g3", "g4", "g7", "memory", "cc");
216 #define xchg(ptr,x) ((__typeof__(*(ptr)))__xchg((unsigned long)(x),(ptr),sizeof(*(ptr))))
218 extern void __xchg_called_with_bad_pointer(void);
220 static __inline__
unsigned long __xchg(unsigned long x
, __volatile__
void * ptr
, int size
)
224 return xchg_u32(ptr
, x
);
226 __xchg_called_with_bad_pointer();
230 extern void die_if_kernel(char *str
, struct pt_regs
*regs
) __attribute__ ((noreturn
));
232 #endif /* __KERNEL__ */
234 #endif /* __ASSEMBLY__ */
236 #define arch_align_stack(x) (x)
238 #endif /* !(__SPARC_SYSTEM_H) */