fs: use kmem_cache_zalloc instead
[pv_ops_mirror.git] / include / asm-sparc64 / pci.h
blob1393e57d50fb0c2bbee86edc1fb814d1bca90b39
1 #ifndef __SPARC64_PCI_H
2 #define __SPARC64_PCI_H
4 #ifdef __KERNEL__
6 #include <linux/dma-mapping.h>
8 /* Can be used to override the logic in pci_scan_bus for skipping
9 * already-configured bus numbers - to be used for buggy BIOSes
10 * or architectures with incomplete PCI setup by the loader.
12 #define pcibios_assign_all_busses() 0
13 #define pcibios_scan_all_fns(a, b) 0
15 #define PCIBIOS_MIN_IO 0UL
16 #define PCIBIOS_MIN_MEM 0UL
18 #define PCI_IRQ_NONE 0xffffffff
20 #define PCI_CACHE_LINE_BYTES 64
22 static inline void pcibios_set_master(struct pci_dev *dev)
24 /* No special bus mastering setup handling */
27 static inline void pcibios_penalize_isa_irq(int irq, int active)
29 /* We don't do dynamic PCI IRQ allocation */
32 /* The PCI address space does not equal the physical memory
33 * address space. The networking and block device layers use
34 * this boolean for bounce buffer decisions.
36 #define PCI_DMA_BUS_IS_PHYS (0)
38 static inline void *pci_alloc_consistent(struct pci_dev *pdev, size_t size,
39 dma_addr_t *dma_handle)
41 return dma_alloc_coherent(&pdev->dev, size, dma_handle, GFP_ATOMIC);
44 static inline void pci_free_consistent(struct pci_dev *pdev, size_t size,
45 void *vaddr, dma_addr_t dma_handle)
47 return dma_free_coherent(&pdev->dev, size, vaddr, dma_handle);
50 static inline dma_addr_t pci_map_single(struct pci_dev *pdev, void *ptr,
51 size_t size, int direction)
53 return dma_map_single(&pdev->dev, ptr, size,
54 (enum dma_data_direction) direction);
57 static inline void pci_unmap_single(struct pci_dev *pdev, dma_addr_t dma_addr,
58 size_t size, int direction)
60 dma_unmap_single(&pdev->dev, dma_addr, size,
61 (enum dma_data_direction) direction);
64 #define pci_map_page(dev, page, off, size, dir) \
65 pci_map_single(dev, (page_address(page) + (off)), size, dir)
66 #define pci_unmap_page(dev,addr,sz,dir) \
67 pci_unmap_single(dev,addr,sz,dir)
69 /* pci_unmap_{single,page} is not a nop, thus... */
70 #define DECLARE_PCI_UNMAP_ADDR(ADDR_NAME) \
71 dma_addr_t ADDR_NAME;
72 #define DECLARE_PCI_UNMAP_LEN(LEN_NAME) \
73 __u32 LEN_NAME;
74 #define pci_unmap_addr(PTR, ADDR_NAME) \
75 ((PTR)->ADDR_NAME)
76 #define pci_unmap_addr_set(PTR, ADDR_NAME, VAL) \
77 (((PTR)->ADDR_NAME) = (VAL))
78 #define pci_unmap_len(PTR, LEN_NAME) \
79 ((PTR)->LEN_NAME)
80 #define pci_unmap_len_set(PTR, LEN_NAME, VAL) \
81 (((PTR)->LEN_NAME) = (VAL))
83 static inline int pci_map_sg(struct pci_dev *pdev, struct scatterlist *sg,
84 int nents, int direction)
86 return dma_map_sg(&pdev->dev, sg, nents,
87 (enum dma_data_direction) direction);
90 static inline void pci_unmap_sg(struct pci_dev *pdev, struct scatterlist *sg,
91 int nents, int direction)
93 dma_unmap_sg(&pdev->dev, sg, nents,
94 (enum dma_data_direction) direction);
97 static inline void pci_dma_sync_single_for_cpu(struct pci_dev *pdev,
98 dma_addr_t dma_handle,
99 size_t size, int direction)
101 dma_sync_single_for_cpu(&pdev->dev, dma_handle, size,
102 (enum dma_data_direction) direction);
105 static inline void pci_dma_sync_single_for_device(struct pci_dev *pdev,
106 dma_addr_t dma_handle,
107 size_t size, int direction)
109 /* No flushing needed to sync cpu writes to the device. */
112 static inline void pci_dma_sync_sg_for_cpu(struct pci_dev *pdev,
113 struct scatterlist *sg,
114 int nents, int direction)
116 dma_sync_sg_for_cpu(&pdev->dev, sg, nents,
117 (enum dma_data_direction) direction);
120 static inline void pci_dma_sync_sg_for_device(struct pci_dev *pdev,
121 struct scatterlist *sg,
122 int nelems, int direction)
124 /* No flushing needed to sync cpu writes to the device. */
127 /* Return whether the given PCI device DMA address mask can
128 * be supported properly. For example, if your device can
129 * only drive the low 24-bits during PCI bus mastering, then
130 * you would pass 0x00ffffff as the mask to this function.
132 extern int pci_dma_supported(struct pci_dev *hwdev, u64 mask);
134 /* PCI IOMMU mapping bypass support. */
136 /* PCI 64-bit addressing works for all slots on all controller
137 * types on sparc64. However, it requires that the device
138 * can drive enough of the 64 bits.
140 #define PCI64_REQUIRED_MASK (~(dma64_addr_t)0)
141 #define PCI64_ADDR_BASE 0xfffc000000000000UL
143 static inline int pci_dma_mapping_error(dma_addr_t dma_addr)
145 return dma_mapping_error(dma_addr);
148 #ifdef CONFIG_PCI
149 static inline void pci_dma_burst_advice(struct pci_dev *pdev,
150 enum pci_dma_burst_strategy *strat,
151 unsigned long *strategy_parameter)
153 unsigned long cacheline_size;
154 u8 byte;
156 pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &byte);
157 if (byte == 0)
158 cacheline_size = 1024;
159 else
160 cacheline_size = (int) byte * 4;
162 *strat = PCI_DMA_BURST_BOUNDARY;
163 *strategy_parameter = cacheline_size;
165 #endif
167 /* Return the index of the PCI controller for device PDEV. */
169 extern int pci_domain_nr(struct pci_bus *bus);
170 static inline int pci_proc_domain(struct pci_bus *bus)
172 return 1;
175 /* Platform support for /proc/bus/pci/X/Y mmap()s. */
177 #define HAVE_PCI_MMAP
178 #define HAVE_ARCH_PCI_GET_UNMAPPED_AREA
179 #define get_pci_unmapped_area get_fb_unmapped_area
181 extern int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma,
182 enum pci_mmap_state mmap_state,
183 int write_combine);
185 extern void
186 pcibios_resource_to_bus(struct pci_dev *dev, struct pci_bus_region *region,
187 struct resource *res);
189 extern void
190 pcibios_bus_to_resource(struct pci_dev *dev, struct resource *res,
191 struct pci_bus_region *region);
193 extern struct resource *pcibios_select_root(struct pci_dev *, struct resource *);
195 static inline int pci_get_legacy_ide_irq(struct pci_dev *dev, int channel)
197 return PCI_IRQ_NONE;
200 struct device_node;
201 extern struct device_node *pci_device_to_OF_node(struct pci_dev *pdev);
203 #endif /* __KERNEL__ */
205 #endif /* __SPARC64_PCI_H */