fs: use kmem_cache_zalloc instead
[pv_ops_mirror.git] / include / asm-x86 / ipi.h
bloba7c75ea408a8072ed35aca77bf9be85b2ef525e5
1 #ifndef __ASM_IPI_H
2 #define __ASM_IPI_H
4 /*
5 * Copyright 2004 James Cleverdon, IBM.
6 * Subject to the GNU Public License, v.2
8 * Generic APIC InterProcessor Interrupt code.
10 * Moved to include file by James Cleverdon from
11 * arch/x86-64/kernel/smp.c
13 * Copyrights from kernel/smp.c:
15 * (c) 1995 Alan Cox, Building #3 <alan@redhat.com>
16 * (c) 1998-99, 2000 Ingo Molnar <mingo@redhat.com>
17 * (c) 2002,2003 Andi Kleen, SuSE Labs.
18 * Subject to the GNU Public License, v.2
21 #include <asm/hw_irq.h>
22 #include <asm/apic.h>
25 * the following functions deal with sending IPIs between CPUs.
27 * We use 'broadcast', CPU->CPU IPIs and self-IPIs too.
30 static inline unsigned int __prepare_ICR (unsigned int shortcut, int vector, unsigned int dest)
32 unsigned int icr = shortcut | dest;
34 switch (vector) {
35 default:
36 icr |= APIC_DM_FIXED | vector;
37 break;
38 case NMI_VECTOR:
39 icr |= APIC_DM_NMI;
40 break;
42 return icr;
45 static inline int __prepare_ICR2 (unsigned int mask)
47 return SET_APIC_DEST_FIELD(mask);
50 static inline void __send_IPI_shortcut(unsigned int shortcut, int vector, unsigned int dest)
53 * Subtle. In the case of the 'never do double writes' workaround
54 * we have to lock out interrupts to be safe. As we don't care
55 * of the value read we use an atomic rmw access to avoid costly
56 * cli/sti. Otherwise we use an even cheaper single atomic write
57 * to the APIC.
59 unsigned int cfg;
62 * Wait for idle.
64 apic_wait_icr_idle();
67 * No need to touch the target chip field
69 cfg = __prepare_ICR(shortcut, vector, dest);
72 * Send the IPI. The write to APIC_ICR fires this off.
74 apic_write(APIC_ICR, cfg);
78 * This is used to send an IPI with no shorthand notation (the destination is
79 * specified in bits 56 to 63 of the ICR).
81 static inline void __send_IPI_dest_field(unsigned int mask, int vector, unsigned int dest)
83 unsigned long cfg;
86 * Wait for idle.
88 if (unlikely(vector == NMI_VECTOR))
89 safe_apic_wait_icr_idle();
90 else
91 apic_wait_icr_idle();
94 * prepare target chip field
96 cfg = __prepare_ICR2(mask);
97 apic_write(APIC_ICR2, cfg);
100 * program the ICR
102 cfg = __prepare_ICR(0, vector, dest);
105 * Send the IPI. The write to APIC_ICR fires this off.
107 apic_write(APIC_ICR, cfg);
110 static inline void send_IPI_mask_sequence(cpumask_t mask, int vector)
112 unsigned long flags;
113 unsigned long query_cpu;
116 * Hack. The clustered APIC addressing mode doesn't allow us to send
117 * to an arbitrary mask, so I do a unicast to each CPU instead.
118 * - mbligh
120 local_irq_save(flags);
121 for_each_cpu_mask(query_cpu, mask) {
122 __send_IPI_dest_field(x86_cpu_to_apicid[query_cpu],
123 vector, APIC_DEST_PHYSICAL);
125 local_irq_restore(flags);
128 #endif /* __ASM_IPI_H */