4 #include <linux/kernel.h>
5 #include <asm/segment.h>
6 #include <asm/cpufeature.h>
7 #include <asm/cmpxchg.h>
11 struct task_struct
; /* one of the stranger aspects of C forward declarations.. */
12 extern struct task_struct
* FASTCALL(__switch_to(struct task_struct
*prev
, struct task_struct
*next
));
15 * Saving eflags is important. It switches not only IOPL between tasks,
16 * it also protects other tasks from NT leaking through sysenter etc.
18 #define switch_to(prev,next,last) do { \
19 unsigned long esi,edi; \
20 asm volatile("pushfl\n\t" /* Save flags */ \
22 "movl %%esp,%0\n\t" /* save ESP */ \
23 "movl %5,%%esp\n\t" /* restore ESP */ \
24 "movl $1f,%1\n\t" /* save EIP */ \
25 "pushl %6\n\t" /* restore EIP */ \
30 :"=m" (prev->thread.esp),"=m" (prev->thread.eip), \
31 "=a" (last),"=S" (esi),"=D" (edi) \
32 :"m" (next->thread.esp),"m" (next->thread.eip), \
33 "2" (prev), "d" (next)); \
36 #define _set_base(addr,base) do { unsigned long __pr; \
37 __asm__ __volatile__ ("movw %%dx,%1\n\t" \
38 "rorl $16,%%edx\n\t" \
48 #define _set_limit(addr,limit) do { unsigned long __lr; \
49 __asm__ __volatile__ ("movw %%dx,%1\n\t" \
50 "rorl $16,%%edx\n\t" \
52 "andb $0xf0,%%dh\n\t" \
61 #define set_base(ldt,base) _set_base( ((char *)&(ldt)) , (base) )
62 #define set_limit(ldt,limit) _set_limit( ((char *)&(ldt)) , ((limit)-1) )
65 * Load a segment. Fall back on loading the zero
66 * segment if something goes wrong..
68 #define loadsegment(seg,value) \
71 "mov %0,%%" #seg "\n" \
73 ".section .fixup,\"ax\"\n" \
76 "popl %%" #seg "\n\t" \
79 ".section __ex_table,\"a\"\n\t" \
86 * Save a segment register away
88 #define savesegment(seg, value) \
89 asm volatile("mov %%" #seg ",%0":"=rm" (value))
92 static inline void native_clts(void)
94 asm volatile ("clts");
97 static inline unsigned long native_read_cr0(void)
100 asm volatile("movl %%cr0,%0\n\t" :"=r" (val
));
104 static inline void native_write_cr0(unsigned long val
)
106 asm volatile("movl %0,%%cr0": :"r" (val
));
109 static inline unsigned long native_read_cr2(void)
112 asm volatile("movl %%cr2,%0\n\t" :"=r" (val
));
116 static inline void native_write_cr2(unsigned long val
)
118 asm volatile("movl %0,%%cr2": :"r" (val
));
121 static inline unsigned long native_read_cr3(void)
124 asm volatile("movl %%cr3,%0\n\t" :"=r" (val
));
128 static inline void native_write_cr3(unsigned long val
)
130 asm volatile("movl %0,%%cr3": :"r" (val
));
133 static inline unsigned long native_read_cr4(void)
136 asm volatile("movl %%cr4,%0\n\t" :"=r" (val
));
140 static inline unsigned long native_read_cr4_safe(void)
143 /* This could fault if %cr4 does not exist */
144 asm("1: movl %%cr4, %0 \n"
146 ".section __ex_table,\"a\" \n"
149 : "=r" (val
): "0" (0));
153 static inline void native_write_cr4(unsigned long val
)
155 asm volatile("movl %0,%%cr4": :"r" (val
));
158 static inline void native_wbinvd(void)
160 asm volatile("wbinvd": : :"memory");
164 #ifdef CONFIG_PARAVIRT
165 #include <asm/paravirt.h>
167 #define read_cr0() (native_read_cr0())
168 #define write_cr0(x) (native_write_cr0(x))
169 #define read_cr2() (native_read_cr2())
170 #define write_cr2(x) (native_write_cr2(x))
171 #define read_cr3() (native_read_cr3())
172 #define write_cr3(x) (native_write_cr3(x))
173 #define read_cr4() (native_read_cr4())
174 #define read_cr4_safe() (native_read_cr4_safe())
175 #define write_cr4(x) (native_write_cr4(x))
176 #define wbinvd() (native_wbinvd())
178 /* Clear the 'TS' bit */
179 #define clts() (native_clts())
181 #endif/* CONFIG_PARAVIRT */
183 /* Set the 'TS' bit */
184 #define stts() write_cr0(8 | read_cr0())
186 #endif /* __KERNEL__ */
188 static inline unsigned long get_limit(unsigned long segment
)
190 unsigned long __limit
;
192 :"=r" (__limit
):"r" (segment
));
196 #define nop() __asm__ __volatile__ ("nop")
199 * Force strict CPU ordering.
200 * And yes, this is required on UP too when we're talking
203 * For now, "wmb()" doesn't actually do anything, as all
204 * Intel CPU's follow what Intel calls a *Processor Order*,
205 * in which all writes are seen in the program order even
208 * I expect future Intel CPU's to have a weaker ordering,
209 * but I'd also expect them to finally get their act together
210 * and add some real memory barriers if so.
212 * Some non intel clones support out of order store. wmb() ceases to be a
217 #define mb() alternative("lock; addl $0,0(%%esp)", "mfence", X86_FEATURE_XMM2)
218 #define rmb() alternative("lock; addl $0,0(%%esp)", "lfence", X86_FEATURE_XMM2)
219 #define wmb() alternative("lock; addl $0,0(%%esp)", "sfence", X86_FEATURE_XMM)
222 * read_barrier_depends - Flush all pending reads that subsequents reads
225 * No data-dependent reads from memory-like regions are ever reordered
226 * over this barrier. All reads preceding this primitive are guaranteed
227 * to access memory (but not necessarily other CPUs' caches) before any
228 * reads following this primitive that depend on the data return by
229 * any of the preceding reads. This primitive is much lighter weight than
230 * rmb() on most CPUs, and is never heavier weight than is
233 * These ordering constraints are respected by both the local CPU
236 * Ordering is not guaranteed by anything other than these primitives,
237 * not even by data dependencies. See the documentation for
238 * memory_barrier() for examples and URLs to more information.
240 * For example, the following code would force ordering (the initial
241 * value of "a" is zero, "b" is one, and "p" is "&a"):
249 * read_barrier_depends();
253 * because the read of "*q" depends on the read of "p" and these
254 * two reads are separated by a read_barrier_depends(). However,
255 * the following code, with the same initial values for "a" and "b":
263 * read_barrier_depends();
267 * does not enforce ordering, since there is no data dependency between
268 * the read of "a" and the read of "b". Therefore, on some CPUs, such
269 * as Alpha, "y" could be set to 3 and "x" to 0. Use rmb()
270 * in cases like this where there are no data dependencies.
273 #define read_barrier_depends() do { } while(0)
276 #define smp_mb() mb()
277 #ifdef CONFIG_X86_PPRO_FENCE
278 # define smp_rmb() rmb()
280 # define smp_rmb() barrier()
282 #ifdef CONFIG_X86_OOSTORE
283 # define smp_wmb() wmb()
285 # define smp_wmb() barrier()
287 #define smp_read_barrier_depends() read_barrier_depends()
288 #define set_mb(var, value) do { (void) xchg(&var, value); } while (0)
290 #define smp_mb() barrier()
291 #define smp_rmb() barrier()
292 #define smp_wmb() barrier()
293 #define smp_read_barrier_depends() do { } while(0)
294 #define set_mb(var, value) do { var = value; barrier(); } while (0)
297 #include <linux/irqflags.h>
300 * disable hlt during certain critical i/o operations
302 #define HAVE_DISABLE_HLT
303 void disable_hlt(void);
304 void enable_hlt(void);
306 extern int es7000_plat
;
307 void cpu_idle_wait(void);
309 extern unsigned long arch_align_stack(unsigned long sp
);
310 extern void free_init_pages(char *what
, unsigned long begin
, unsigned long end
);
312 void default_idle(void);