fs: use kmem_cache_zalloc instead
[pv_ops_mirror.git] / include / asm-xtensa / cacheasm.h
blob2c20a58f94cdd8629164b3974e4a76d75eb90f66
1 /*
2 * include/asm-xtensa/cacheasm.h
4 * This file is subject to the terms and conditions of the GNU General Public
5 * License. See the file "COPYING" in the main directory of this archive
6 * for more details.
8 * Copyright (C) 2006 Tensilica Inc.
9 */
11 #include <asm/cache.h>
12 #include <asm/asmmacro.h>
13 #include <linux/stringify.h>
16 * Define cache functions as macros here so that they can be used
17 * by the kernel and boot loader. We should consider moving them to a
18 * library that can be linked by both.
20 * Locking
22 * ___unlock_dcache_all
23 * ___unlock_icache_all
25 * Flush and invaldating
27 * ___flush_invalidate_dcache_{all|range|page}
28 * ___flush_dcache_{all|range|page}
29 * ___invalidate_dcache_{all|range|page}
30 * ___invalidate_icache_{all|range|page}
34 .macro __loop_cache_all ar at insn size line_width
36 movi \ar, 0
38 __loopi \ar, \at, \size, (4 << (\line_width))
39 \insn \ar, 0 << (\line_width)
40 \insn \ar, 1 << (\line_width)
41 \insn \ar, 2 << (\line_width)
42 \insn \ar, 3 << (\line_width)
43 __endla \ar, \at, 4 << (\line_width)
45 .endm
48 .macro __loop_cache_range ar as at insn line_width
50 extui \at, \ar, 0, \line_width
51 add \as, \as, \at
53 __loops \ar, \as, \at, \line_width
54 \insn \ar, 0
55 __endla \ar, \at, (1 << (\line_width))
57 .endm
60 .macro __loop_cache_page ar at insn line_width
62 __loopi \ar, \at, PAGE_SIZE, 4 << (\line_width)
63 \insn \ar, 0 << (\line_width)
64 \insn \ar, 1 << (\line_width)
65 \insn \ar, 2 << (\line_width)
66 \insn \ar, 3 << (\line_width)
67 __endla \ar, \at, 4 << (\line_width)
69 .endm
72 #if XCHAL_DCACHE_LINE_LOCKABLE
74 .macro ___unlock_dcache_all ar at
76 __loop_cache_all \ar \at diu XCHAL_DCACHE_SIZE XCHAL_DCACHE_LINEWIDTH
78 .endm
80 #endif
82 #if XCHAL_ICACHE_LINE_LOCKABLE
84 .macro ___unlock_icache_all ar at
86 __loop_cache_all \ar \at iiu XCHAL_ICACHE_SIZE XCHAL_ICACHE_LINEWIDTH
88 .endm
89 #endif
91 .macro ___flush_invalidate_dcache_all ar at
93 __loop_cache_all \ar \at diwbi XCHAL_DCACHE_SIZE XCHAL_DCACHE_LINEWIDTH
95 .endm
98 .macro ___flush_dcache_all ar at
100 __loop_cache_all \ar \at diwb XCHAL_DCACHE_SIZE XCHAL_DCACHE_LINEWIDTH
102 .endm
105 .macro ___invalidate_dcache_all ar at
107 __loop_cache_all \ar \at dii __stringify(DCACHE_WAY_SIZE) \
108 XCHAL_DCACHE_LINEWIDTH
110 .endm
113 .macro ___invalidate_icache_all ar at
115 __loop_cache_all \ar \at iii __stringify(ICACHE_WAY_SIZE) \
116 XCHAL_ICACHE_LINEWIDTH
118 .endm
122 .macro ___flush_invalidate_dcache_range ar as at
124 __loop_cache_range \ar \as \at dhwbi XCHAL_DCACHE_LINEWIDTH
126 .endm
129 .macro ___flush_dcache_range ar as at
131 __loop_cache_range \ar \as \at dhwb XCHAL_DCACHE_LINEWIDTH
133 .endm
136 .macro ___invalidate_dcache_range ar as at
138 __loop_cache_range \ar \as \at dhi XCHAL_DCACHE_LINEWIDTH
140 .endm
143 .macro ___invalidate_icache_range ar as at
145 __loop_cache_range \ar \as \at ihi XCHAL_ICACHE_LINEWIDTH
147 .endm
151 .macro ___flush_invalidate_dcache_page ar as
153 __loop_cache_page \ar \as dhwbi XCHAL_DCACHE_LINEWIDTH
155 .endm
158 .macro ___flush_dcache_page ar as
160 __loop_cache_page \ar \as dhwb XCHAL_DCACHE_LINEWIDTH
162 .endm
165 .macro ___invalidate_dcache_page ar as
167 __loop_cache_page \ar \as dhi XCHAL_DCACHE_LINEWIDTH
169 .endm
172 .macro ___invalidate_icache_page ar as
174 __loop_cache_page \ar \as ihi XCHAL_ICACHE_LINEWIDTH
176 .endm