fs: use kmem_cache_zalloc instead
[pv_ops_mirror.git] / include / asm-xtensa / regs.h
blobc913d259faaaad3bf1728c33307db918daa4b0d9
1 /*
2 * Copyright (c) 2006 Tensilica, Inc. All Rights Reserved.
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of version 2.1 of the GNU Lesser General Public
6 * License as published by the Free Software Foundation.
8 * This program is distributed in the hope that it would be useful, but
9 * WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
12 * Further, this software is distributed without any warranty that it is
13 * free of the rightful claim of any third person regarding infringement
14 * or the like. Any license provided herein, whether implied or
15 * otherwise, applies only to this software file. Patent licenses, if
16 * any, provided herein do not apply to combinations of this program with
17 * other software, or any other product whatsoever.
19 * You should have received a copy of the GNU Lesser General Public
20 * License along with this program; if not, write the Free Software
21 * Foundation, Inc., 59 Temple Place - Suite 330, Boston MA 02111-1307,
22 * USA.
25 #ifndef _XTENSA_REGS_H
26 #define _XTENSA_REGS_H
28 /* Special registers. */
30 #define LBEG 0
31 #define LEND 1
32 #define LCOUNT 2
33 #define SAR 3
34 #define BR 4
35 #define SCOMPARE1 12
36 #define ACCHI 16
37 #define ACCLO 17
38 #define MR 32
39 #define WINDOWBASE 72
40 #define WINDOWSTART 73
41 #define PTEVADDR 83
42 #define RASID 90
43 #define ITLBCFG 91
44 #define DTLBCFG 92
45 #define IBREAKENABLE 96
46 #define DDR 104
47 #define IBREAKA 128
48 #define DBREAKA 144
49 #define DBREAKC 160
50 #define EPC 176
51 #define EPC_1 177
52 #define DEPC 192
53 #define EPS 192
54 #define EPS_1 193
55 #define EXCSAVE 208
56 #define EXCSAVE_1 209
57 #define INTERRUPT 226
58 #define INTENABLE 228
59 #define PS 230
60 #define THREADPTR 231
61 #define EXCCAUSE 232
62 #define DEBUGCAUSE 233
63 #define CCOUNT 234
64 #define PRID 235
65 #define ICOUNT 236
66 #define ICOUNTLEVEL 237
67 #define EXCVADDR 238
68 #define CCOMPARE 240
69 #define MISC 244
71 /* Special names for read-only and write-only interrupt registers. */
73 #define INTREAD 226
74 #define INTSET 226
75 #define INTCLEAR 227
77 /* EXCCAUSE register fields */
79 #define EXCCAUSE_EXCCAUSE_SHIFT 0
80 #define EXCCAUSE_EXCCAUSE_MASK 0x3F
82 #define EXCCAUSE_ILLEGAL_INSTRUCTION 0
83 #define EXCCAUSE_SYSTEM_CALL 1
84 #define EXCCAUSE_INSTRUCTION_FETCH_ERROR 2
85 #define EXCCAUSE_LOAD_STORE_ERROR 3
86 #define EXCCAUSE_LEVEL1_INTERRUPT 4
87 #define EXCCAUSE_ALLOCA 5
88 #define EXCCAUSE_INTEGER_DIVIDE_BY_ZERO 6
89 #define EXCCAUSE_SPECULATION 7
90 #define EXCCAUSE_PRIVILEGED 8
91 #define EXCCAUSE_UNALIGNED 9
92 #define EXCCAUSE_ITLB_MISS 16
93 #define EXCCAUSE_ITLB_MULTIHIT 17
94 #define EXCCAUSE_ITLB_PRIVILEGE 18
95 #define EXCCAUSE_ITLB_SIZE_RESTRICTION 19
96 #define EXCCAUSE_FETCH_CACHE_ATTRIBUTE 20
97 #define EXCCAUSE_DTLB_MISS 24
98 #define EXCCAUSE_DTLB_MULTIHIT 25
99 #define EXCCAUSE_DTLB_PRIVILEGE 26
100 #define EXCCAUSE_DTLB_SIZE_RESTRICTION 27
101 #define EXCCAUSE_LOAD_CACHE_ATTRIBUTE 28
102 #define EXCCAUSE_STORE_CACHE_ATTRIBUTE 29
103 #define EXCCAUSE_FLOATING_POINT 40
105 /* PS register fields. */
107 #define PS_WOE_BIT 18
108 #define PS_CALLINC_SHIFT 16
109 #define PS_CALLINC_MASK 0x00030000
110 #define PS_OWB_SHIFT 8
111 #define PS_OWB_MASK 0x00000F00
112 #define PS_RING_SHIFT 6
113 #define PS_RING_MASK 0x000000C0
114 #define PS_UM_BIT 5
115 #define PS_EXCM_BIT 4
116 #define PS_INTLEVEL_SHIFT 0
117 #define PS_INTLEVEL_MASK 0x0000000F
119 /* DBREAKCn register fields. */
121 #define DBREAKC_MASK_BIT 0
122 #define DBREAKC_MASK_MASK 0x0000003F
123 #define DBREAKC_LOAD_BIT 30
124 #define DBREAKC_LOAD_MASK 0x40000000
125 #define DBREAKC_STOR_BIT 31
126 #define DBREAKC_STOR_MASK 0x80000000
128 /* DEBUGCAUSE register fields. */
130 #define DEBUGCAUSE_DEBUGINT_BIT 5 /* External debug interrupt */
131 #define DEBUGCAUSE_BREAKN_BIT 4 /* BREAK.N instruction */
132 #define DEBUGCAUSE_BREAK_BIT 3 /* BREAK instruction */
133 #define DEBUGCAUSE_DBREAK_BIT 2 /* DBREAK match */
134 #define DEBUGCAUSE_IBREAK_BIT 1 /* IBREAK match */
135 #define DEBUGCAUSE_ICOUNT_BIT 0 /* ICOUNT would incr. to zero */
137 #endif /* _XTENSA_SPECREG_H */