fs: use kmem_cache_zalloc instead
[pv_ops_mirror.git] / include / asm-xtensa / system.h
blobddc970847ae9e406c3a9da69e04a190c1acc7151
1 /*
2 * include/asm-xtensa/system.h
4 * This file is subject to the terms and conditions of the GNU General Public
5 * License. See the file "COPYING" in the main directory of this archive
6 * for more details.
8 * Copyright (C) 2001 - 2005 Tensilica Inc.
9 */
11 #ifndef _XTENSA_SYSTEM_H
12 #define _XTENSA_SYSTEM_H
14 #include <linux/stringify.h>
16 #include <asm/processor.h>
18 /* interrupt control */
20 #define local_save_flags(x) \
21 __asm__ __volatile__ ("rsr %0,"__stringify(PS) : "=a" (x));
22 #define local_irq_restore(x) do { \
23 __asm__ __volatile__ ("wsr %0, "__stringify(PS)" ; rsync" \
24 :: "a" (x) : "memory"); } while(0);
25 #define local_irq_save(x) do { \
26 __asm__ __volatile__ ("rsil %0, "__stringify(LOCKLEVEL) \
27 : "=a" (x) :: "memory");} while(0);
29 static inline void local_irq_disable(void)
31 unsigned long flags;
32 __asm__ __volatile__ ("rsil %0, "__stringify(LOCKLEVEL)
33 : "=a" (flags) :: "memory");
35 static inline void local_irq_enable(void)
37 unsigned long flags;
38 __asm__ __volatile__ ("rsil %0, 0" : "=a" (flags) :: "memory");
42 static inline int irqs_disabled(void)
44 unsigned long flags;
45 local_save_flags(flags);
46 return flags & 0xf;
49 #define RSR_CPENABLE(x) do { \
50 __asm__ __volatile__("rsr %0," __stringify(CPENABLE) : "=a" (x)); \
51 } while(0);
52 #define WSR_CPENABLE(x) do { \
53 __asm__ __volatile__("wsr %0," __stringify(CPENABLE)";rsync" \
54 :: "a" (x));} while(0);
56 #define clear_cpenable() __clear_cpenable()
58 static inline void __clear_cpenable(void)
60 #if XCHAL_HAVE_CP
61 unsigned long i = 0;
62 WSR_CPENABLE(i);
63 #endif
66 static inline void enable_coprocessor(int i)
68 #if XCHAL_HAVE_CP
69 int cp;
70 RSR_CPENABLE(cp);
71 cp |= 1 << i;
72 WSR_CPENABLE(cp);
73 #endif
76 static inline void disable_coprocessor(int i)
78 #if XCHAL_HAVE_CP
79 int cp;
80 RSR_CPENABLE(cp);
81 cp &= ~(1 << i);
82 WSR_CPENABLE(cp);
83 #endif
86 #define smp_read_barrier_depends() do { } while(0)
87 #define read_barrier_depends() do { } while(0)
89 #define mb() barrier()
90 #define rmb() mb()
91 #define wmb() mb()
93 #ifdef CONFIG_SMP
94 #error smp_* not defined
95 #else
96 #define smp_mb() barrier()
97 #define smp_rmb() barrier()
98 #define smp_wmb() barrier()
99 #endif
101 #define set_mb(var, value) do { var = value; mb(); } while (0)
103 #if !defined (__ASSEMBLY__)
105 /* * switch_to(n) should switch tasks to task nr n, first
106 * checking that n isn't the current task, in which case it does nothing.
108 extern void *_switch_to(void *last, void *next);
110 #endif /* __ASSEMBLY__ */
112 #define switch_to(prev,next,last) \
113 do { \
114 clear_cpenable(); \
115 (last) = _switch_to(prev, next); \
116 } while(0)
119 * cmpxchg
122 static inline unsigned long
123 __cmpxchg_u32(volatile int *p, int old, int new)
125 __asm__ __volatile__("rsil a15, "__stringify(LOCKLEVEL)"\n\t"
126 "l32i %0, %1, 0 \n\t"
127 "bne %0, %2, 1f \n\t"
128 "s32i %3, %1, 0 \n\t"
129 "1: \n\t"
130 "wsr a15, "__stringify(PS)" \n\t"
131 "rsync \n\t"
132 : "=&a" (old)
133 : "a" (p), "a" (old), "r" (new)
134 : "a15", "memory");
135 return old;
137 /* This function doesn't exist, so you'll get a linker error
138 * if something tries to do an invalid cmpxchg(). */
140 extern void __cmpxchg_called_with_bad_pointer(void);
142 static __inline__ unsigned long
143 __cmpxchg(volatile void *ptr, unsigned long old, unsigned long new, int size)
145 switch (size) {
146 case 4: return __cmpxchg_u32(ptr, old, new);
147 default: __cmpxchg_called_with_bad_pointer();
148 return old;
152 #define cmpxchg(ptr,o,n) \
153 ({ __typeof__(*(ptr)) _o_ = (o); \
154 __typeof__(*(ptr)) _n_ = (n); \
155 (__typeof__(*(ptr))) __cmpxchg((ptr), (unsigned long)_o_, \
156 (unsigned long)_n_, sizeof (*(ptr))); \
163 * xchg_u32
165 * Note that a15 is used here because the register allocation
166 * done by the compiler is not guaranteed and a window overflow
167 * may not occur between the rsil and wsr instructions. By using
168 * a15 in the rsil, the machine is guaranteed to be in a state
169 * where no register reference will cause an overflow.
172 static inline unsigned long xchg_u32(volatile int * m, unsigned long val)
174 unsigned long tmp;
175 __asm__ __volatile__("rsil a15, "__stringify(LOCKLEVEL)"\n\t"
176 "l32i %0, %1, 0 \n\t"
177 "s32i %2, %1, 0 \n\t"
178 "wsr a15, "__stringify(PS)" \n\t"
179 "rsync \n\t"
180 : "=&a" (tmp)
181 : "a" (m), "a" (val)
182 : "a15", "memory");
183 return tmp;
186 #define xchg(ptr,x) ((__typeof__(*(ptr)))__xchg((unsigned long)(x),(ptr),sizeof(*(ptr))))
189 * This only works if the compiler isn't horribly bad at optimizing.
190 * gcc-2.5.8 reportedly can't handle this, but I define that one to
191 * be dead anyway.
194 extern void __xchg_called_with_bad_pointer(void);
196 static __inline__ unsigned long
197 __xchg(unsigned long x, volatile void * ptr, int size)
199 switch (size) {
200 case 4:
201 return xchg_u32(ptr, x);
203 __xchg_called_with_bad_pointer();
204 return x;
207 extern void set_except_vector(int n, void *addr);
209 static inline void spill_registers(void)
211 unsigned int a0, ps;
213 __asm__ __volatile__ (
214 "movi a14," __stringify (PS_EXCM_BIT) " | 1\n\t"
215 "mov a12, a0\n\t"
216 "rsr a13," __stringify(SAR) "\n\t"
217 "xsr a14," __stringify(PS) "\n\t"
218 "movi a0, _spill_registers\n\t"
219 "rsync\n\t"
220 "callx0 a0\n\t"
221 "mov a0, a12\n\t"
222 "wsr a13," __stringify(SAR) "\n\t"
223 "wsr a14," __stringify(PS) "\n\t"
224 :: "a" (&a0), "a" (&ps)
225 : "a2", "a3", "a12", "a13", "a14", "a15", "memory");
228 #define arch_align_stack(x) (x)
230 #endif /* _XTENSA_SYSTEM_H */