drivers/infiniband/hw/ehca/hipz_hw.h

   1 /*
   2  *  IBM eServer eHCA Infiniband device driver for Linux on POWER
   3  *
   4  *  eHCA register definitions
   5  *
   6  *  Authors: Waleri Fomin <fomin@de.ibm.com>
   7  *           Christoph Raisch <raisch@de.ibm.com>
   8  *           Reinhard Ernst <rernst@de.ibm.com>
   9  *
  10  *  Copyright (c) 2005 IBM Corporation
  11  *
  12  *  All rights reserved.
  13  *
  14  *  This source code is distributed under a dual license of GPL v2.0 and OpenIB
  15  *  BSD.
  16  *
  17  * OpenIB BSD License
  18  *
  19  * Redistribution and use in source and binary forms, with or without
  20  * modification, are permitted provided that the following conditions are met:
  21  *
  22  * Redistributions of source code must retain the above copyright notice, this
  23  * list of conditions and the following disclaimer.
  24  *
  25  * Redistributions in binary form must reproduce the above copyright notice,
  26  * this list of conditions and the following disclaimer in the documentation
  27  * and/or other materials
  28  * provided with the distribution.
  29  *
  30  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  31  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  32  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  33  * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
  34  * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  35  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  36  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
  37  * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
  38  * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  39  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  40  * POSSIBILITY OF SUCH DAMAGE.
  41  */
  42
  43 #ifndef __HIPZ_HW_H__
  44 #define __HIPZ_HW_H__
  45
  46 #include "ehca_tools.h"
  47
  48 #define EHCA_MAX_MTU 4
  49
  50 /* QP Table Entry Memory Map */
  51 struct hipz_qptemm {
  52         u64 qpx_hcr;
  53         u64 qpx_c;
  54         u64 qpx_herr;
  55         u64 qpx_aer;
  56 /* 0x20*/
  57         u64 qpx_sqa;
  58         u64 qpx_sqc;
  59         u64 qpx_rqa;
  60         u64 qpx_rqc;
  61 /* 0x40*/
  62         u64 qpx_st;
  63         u64 qpx_pmstate;
  64         u64 qpx_pmfa;
  65         u64 qpx_pkey;
  66 /* 0x60*/
  67         u64 qpx_pkeya;
  68         u64 qpx_pkeyb;
  69         u64 qpx_pkeyc;
  70         u64 qpx_pkeyd;
  71 /* 0x80*/
  72         u64 qpx_qkey;
  73         u64 qpx_dqp;
  74         u64 qpx_dlidp;
  75         u64 qpx_portp;
  76 /* 0xa0*/
  77         u64 qpx_slidp;
  78         u64 qpx_slidpp;
  79         u64 qpx_dlida;
  80         u64 qpx_porta;
  81 /* 0xc0*/
  82         u64 qpx_slida;
  83         u64 qpx_slidpa;
  84         u64 qpx_slvl;
  85         u64 qpx_ipd;
  86 /* 0xe0*/
  87         u64 qpx_mtu;
  88         u64 qpx_lato;
  89         u64 qpx_rlimit;
  90         u64 qpx_rnrlimit;
  91 /* 0x100*/
  92         u64 qpx_t;
  93         u64 qpx_sqhp;
  94         u64 qpx_sqptp;
  95         u64 qpx_nspsn;
  96 /* 0x120*/
  97         u64 qpx_nspsnhwm;
  98         u64 reserved1;
  99         u64 qpx_sdsi;
 100         u64 qpx_sdsbc;
 101 /* 0x140*/
 102         u64 qpx_sqwsize;
 103         u64 qpx_sqwts;
 104         u64 qpx_lsn;
 105         u64 qpx_nssn;
 106 /* 0x160 */
 107         u64 qpx_mor;
 108         u64 qpx_cor;
 109         u64 qpx_sqsize;
 110         u64 qpx_erc;
 111 /* 0x180*/
 112         u64 qpx_rnrrc;
 113         u64 qpx_ernrwt;
 114         u64 qpx_rnrresp;
 115         u64 qpx_lmsna;
 116 /* 0x1a0 */
 117         u64 qpx_sqhpc;
 118         u64 qpx_sqcptp;
 119         u64 qpx_sigt;
 120         u64 qpx_wqecnt;
 121 /* 0x1c0*/
 122         u64 qpx_rqhp;
 123         u64 qpx_rqptp;
 124         u64 qpx_rqsize;
 125         u64 qpx_nrr;
 126 /* 0x1e0*/
 127         u64 qpx_rdmac;
 128         u64 qpx_nrpsn;
 129         u64 qpx_lapsn;
 130         u64 qpx_lcr;
 131 /* 0x200*/
 132         u64 qpx_rwc;
 133         u64 qpx_rwva;
 134         u64 qpx_rdsi;
 135         u64 qpx_rdsbc;
 136 /* 0x220*/
 137         u64 qpx_rqwsize;
 138         u64 qpx_crmsn;
 139         u64 qpx_rdd;
 140         u64 qpx_larpsn;
 141 /* 0x240*/
 142         u64 qpx_pd;
 143         u64 qpx_scqn;
 144         u64 qpx_rcqn;
 145         u64 qpx_aeqn;
 146 /* 0x260*/
 147         u64 qpx_aaelog;
 148         u64 qpx_ram;
 149         u64 qpx_rdmaqe0;
 150         u64 qpx_rdmaqe1;
 151 /* 0x280*/
 152         u64 qpx_rdmaqe2;
 153         u64 qpx_rdmaqe3;
 154         u64 qpx_nrpsnhwm;
 155 /* 0x298*/
 156         u64 reserved[(0x400 - 0x298) / 8];
 157 /* 0x400 extended data */
 158         u64 reserved_ext[(0x500 - 0x400) / 8];
 159 /* 0x500 */
 160         u64 reserved2[(0x1000 - 0x500) / 8];
 161 /* 0x1000      */
 162 };
 163
 164 #define QPX_SQADDER EHCA_BMASK_IBM(48,63)
 165 #define QPX_RQADDER EHCA_BMASK_IBM(48,63)
 166
 167 #define QPTEMM_OFFSET(x) offsetof(struct hipz_qptemm,x)
 168
 169 /* MRMWPT Entry Memory Map */
 170 struct hipz_mrmwmm {
 171         /* 0x00 */
 172         u64 mrx_hcr;
 173
 174         u64 mrx_c;
 175         u64 mrx_herr;
 176         u64 mrx_aer;
 177         /* 0x20 */
 178         u64 mrx_pp;
 179         u64 reserved1;
 180         u64 reserved2;
 181         u64 reserved3;
 182         /* 0x40 */
 183         u64 reserved4[(0x200 - 0x40) / 8];
 184         /* 0x200 */
 185         u64 mrx_ctl[64];
 186
 187 };
 188
 189 #define MRMWMM_OFFSET(x) offsetof(struct hipz_mrmwmm,x)
 190
 191 struct hipz_qpedmm {
 192         /* 0x00 */
 193         u64 reserved0[(0x400) / 8];
 194         /* 0x400 */
 195         u64 qpedx_phh;
 196         u64 qpedx_ppsgp;
 197         /* 0x410 */
 198         u64 qpedx_ppsgu;
 199         u64 qpedx_ppdgp;
 200         /* 0x420 */
 201         u64 qpedx_ppdgu;
 202         u64 qpedx_aph;
 203         /* 0x430 */
 204         u64 qpedx_apsgp;
 205         u64 qpedx_apsgu;
 206         /* 0x440 */
 207         u64 qpedx_apdgp;
 208         u64 qpedx_apdgu;
 209         /* 0x450 */
 210         u64 qpedx_apav;
 211         u64 qpedx_apsav;
 212         /* 0x460  */
 213         u64 qpedx_hcr;
 214         u64 reserved1[4];
 215         /* 0x488 */
 216         u64 qpedx_rrl0;
 217         /* 0x490 */
 218         u64 qpedx_rrrkey0;
 219         u64 qpedx_rrva0;
 220         /* 0x4a0 */
 221         u64 reserved2;
 222         u64 qpedx_rrl1;
 223         /* 0x4b0 */
 224         u64 qpedx_rrrkey1;
 225         u64 qpedx_rrva1;
 226         /* 0x4c0 */
 227         u64 reserved3;
 228         u64 qpedx_rrl2;
 229         /* 0x4d0 */
 230         u64 qpedx_rrrkey2;
 231         u64 qpedx_rrva2;
 232         /* 0x4e0 */
 233         u64 reserved4;
 234         u64 qpedx_rrl3;
 235         /* 0x4f0 */
 236         u64 qpedx_rrrkey3;
 237         u64 qpedx_rrva3;
 238 };
 239
 240 #define QPEDMM_OFFSET(x) offsetof(struct hipz_qpedmm,x)
 241
 242 /* CQ Table Entry Memory Map */
 243 struct hipz_cqtemm {
 244         u64 cqx_hcr;
 245         u64 cqx_c;
 246         u64 cqx_herr;
 247         u64 cqx_aer;
 248 /* 0x20  */
 249         u64 cqx_ptp;
 250         u64 cqx_tp;
 251         u64 cqx_fec;
 252         u64 cqx_feca;
 253 /* 0x40  */
 254         u64 cqx_ep;
 255         u64 cqx_eq;
 256 /* 0x50  */
 257         u64 reserved1;
 258         u64 cqx_n0;
 259 /* 0x60  */
 260         u64 cqx_n1;
 261         u64 reserved2[(0x1000 - 0x60) / 8];
 262 /* 0x1000 */
 263 };
 264
 265 #define CQX_FEC_CQE_CNT           EHCA_BMASK_IBM(32,63)
 266 #define CQX_FECADDER              EHCA_BMASK_IBM(32,63)
 267 #define CQX_N0_GENERATE_SOLICITED_COMP_EVENT EHCA_BMASK_IBM(0,0)
 268 #define CQX_N1_GENERATE_COMP_EVENT EHCA_BMASK_IBM(0,0)
 269
 270 #define CQTEMM_OFFSET(x) offsetof(struct hipz_cqtemm,x)
 271
 272 /* EQ Table Entry Memory Map */
 273 struct hipz_eqtemm {
 274         u64 eqx_hcr;
 275         u64 eqx_c;
 276
 277         u64 eqx_herr;
 278         u64 eqx_aer;
 279 /* 0x20 */
 280         u64 eqx_ptp;
 281         u64 eqx_tp;
 282         u64 eqx_ssba;
 283         u64 eqx_psba;
 284
 285 /* 0x40 */
 286         u64 eqx_cec;
 287         u64 eqx_meql;
 288         u64 eqx_xisbi;
 289         u64 eqx_xisc;
 290 /* 0x60 */
 291         u64 eqx_it;
 292
 293 };
 294
 295 #define EQTEMM_OFFSET(x) offsetof(struct hipz_eqtemm,x)
 296
 297 /* access control defines for MR/MW */
 298 #define HIPZ_ACCESSCTRL_L_WRITE  0x00800000
 299 #define HIPZ_ACCESSCTRL_R_WRITE  0x00400000
 300 #define HIPZ_ACCESSCTRL_R_READ   0x00200000
 301 #define HIPZ_ACCESSCTRL_R_ATOMIC 0x00100000
 302 #define HIPZ_ACCESSCTRL_MW_BIND  0x00080000
 303
 304 /* query hca response block */
 305 struct hipz_query_hca {
 306         u32 cur_reliable_dg;
 307         u32 cur_qp;
 308         u32 cur_cq;
 309         u32 cur_eq;
 310         u32 cur_mr;
 311         u32 cur_mw;
 312         u32 cur_ee_context;
 313         u32 cur_mcast_grp;
 314         u32 cur_qp_attached_mcast_grp;
 315         u32 reserved1;
 316         u32 cur_ipv6_qp;
 317         u32 cur_eth_qp;
 318         u32 cur_hp_mr;
 319         u32 reserved2[3];
 320         u32 max_rd_domain;
 321         u32 max_qp;
 322         u32 max_cq;
 323         u32 max_eq;
 324         u32 max_mr;
 325         u32 max_hp_mr;
 326         u32 max_mw;
 327         u32 max_mrwpte;
 328         u32 max_special_mrwpte;
 329         u32 max_rd_ee_context;
 330         u32 max_mcast_grp;
 331         u32 max_total_mcast_qp_attach;
 332         u32 max_mcast_qp_attach;
 333         u32 max_raw_ipv6_qp;
 334         u32 max_raw_ethy_qp;
 335         u32 internal_clock_frequency;
 336         u32 max_pd;
 337         u32 max_ah;
 338         u32 max_cqe;
 339         u32 max_wqes_wq;
 340         u32 max_partitions;
 341         u32 max_rr_ee_context;
 342         u32 max_rr_qp;
 343         u32 max_rr_hca;
 344         u32 max_act_wqs_ee_context;
 345         u32 max_act_wqs_qp;
 346         u32 max_sge;
 347         u32 max_sge_rd;
 348         u32 memory_page_size_supported;
 349         u64 max_mr_size;
 350         u32 local_ca_ack_delay;
 351         u32 num_ports;
 352         u32 vendor_id;
 353         u32 vendor_part_id;
 354         u32 hw_ver;
 355         u64 node_guid;
 356         u64 hca_cap_indicators;
 357         u32 data_counter_register_size;
 358         u32 max_shared_rq;
 359         u32 max_isns_eq;
 360         u32 max_neq;
 361 } __attribute__ ((packed));
 362
 363 /* query port response block */
 364 struct hipz_query_port {
 365         u32 state;
 366         u32 bad_pkey_cntr;
 367         u32 lmc;
 368         u32 lid;
 369         u32 subnet_timeout;
 370         u32 qkey_viol_cntr;
 371         u32 sm_sl;
 372         u32 sm_lid;
 373         u32 capability_mask;
 374         u32 init_type_reply;
 375         u32 pkey_tbl_len;
 376         u32 gid_tbl_len;
 377         u64 gid_prefix;
 378         u32 port_nr;
 379         u16 pkey_entries[16];
 380         u8  reserved1[32];
 381         u32 trent_size;
 382         u32 trbuf_size;
 383         u64 max_msg_sz;
 384         u32 max_mtu;
 385         u32 vl_cap;
 386         u8  reserved2[1900];
 387         u64 guid_entries[255];
 388 } __attribute__ ((packed));
 389
 390 #endif