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Revert "[PATCH] paravirt: Add startup infrastructure for paravirtualization"
[pv_ops_mirror.git] / drivers / net / ns83820.c
blob3439f8c649f93e5281aed53ceb2a8b9067ff38c3
1 #define VERSION "0.22"
2 /* ns83820.c by Benjamin LaHaise with contributions.
3 *
4 * Questions/comments/discussion to linux-ns83820@kvack.org.
5 *
6 * $Revision: 1.34.2.23 $
7 *
8 * Copyright 2001 Benjamin LaHaise.
9 * Copyright 2001, 2002 Red Hat.
10 *
11 * Mmmm, chocolate vanilla mocha...
12 *
13 *
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License as published by
16 * the Free Software Foundation; either version 2 of the License, or
17 * (at your option) any later version.
18 *
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
23 *
24 * You should have received a copy of the GNU General Public License
25 * along with this program; if not, write to the Free Software
26 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
27 *
28 *
29 * ChangeLog
30 * =========
31 * 20010414 0.1 - created
32 * 20010622 0.2 - basic rx and tx.
33 * 20010711 0.3 - added duplex and link state detection support.
34 * 20010713 0.4 - zero copy, no hangs.
35 * 0.5 - 64 bit dma support (davem will hate me for this)
36 * - disable jumbo frames to avoid tx hangs
37 * - work around tx deadlocks on my 1.02 card via
38 * fiddling with TXCFG
39 * 20010810 0.6 - use pci dma api for ringbuffers, work on ia64
40 * 20010816 0.7 - misc cleanups
41 * 20010826 0.8 - fix critical zero copy bugs
42 * 0.9 - internal experiment
43 * 20010827 0.10 - fix ia64 unaligned access.
44 * 20010906 0.11 - accept all packets with checksum errors as
45 * otherwise fragments get lost
46 * - fix >> 32 bugs
47 * 0.12 - add statistics counters
48 * - add allmulti/promisc support
49 * 20011009 0.13 - hotplug support, other smaller pci api cleanups
50 * 20011204 0.13a - optical transceiver support added
51 * by Michael Clark <michael@metaparadigm.com>
52 * 20011205 0.13b - call register_netdev earlier in initialization
53 * suppress duplicate link status messages
54 * 20011117 0.14 - ethtool GDRVINFO, GLINK support from jgarzik
55 * 20011204 0.15 get ppc (big endian) working
56 * 20011218 0.16 various cleanups
57 * 20020310 0.17 speedups
58 * 20020610 0.18 - actually use the pci dma api for highmem
59 * - remove pci latency register fiddling
60 * 0.19 - better bist support
61 * - add ihr and reset_phy parameters
62 * - gmii bus probing
63 * - fix missed txok introduced during performance
64 * tuning
65 * 0.20 - fix stupid RFEN thinko. i am such a smurf.
66 * 20040828 0.21 - add hardware vlan accleration
67 * by Neil Horman <nhorman@redhat.com>
68 * 20050406 0.22 - improved DAC ifdefs from Andi Kleen
69 * - removal of dead code from Adrian Bunk
70 * - fix half duplex collision behaviour
71 * Driver Overview
72 * ===============
73 *
74 * This driver was originally written for the National Semiconductor
75 * 83820 chip, a 10/100/1000 Mbps 64 bit PCI ethernet NIC. Hopefully
76 * this code will turn out to be a) clean, b) correct, and c) fast.
77 * With that in mind, I'm aiming to split the code up as much as
78 * reasonably possible. At present there are X major sections that
79 * break down into a) packet receive, b) packet transmit, c) link
80 * management, d) initialization and configuration. Where possible,
81 * these code paths are designed to run in parallel.
82 *
83 * This driver has been tested and found to work with the following
84 * cards (in no particular order):
85 *
86 * Cameo SOHO-GA2000T SOHO-GA2500T
87 * D-Link DGE-500T
88 * PureData PDP8023Z-TG
89 * SMC SMC9452TX SMC9462TX
90 * Netgear GA621
91 *
92 * Special thanks to SMC for providing hardware to test this driver on.
93 *
94 * Reports of success or failure would be greatly appreciated.
95 */
96 //#define dprintk printk
97 #define dprintk(x...) do { } while (0)
98
99 #include <linux/module.h>
100 #include <linux/moduleparam.h>
101 #include <linux/types.h>
102 #include <linux/pci.h>
103 #include <linux/dma-mapping.h>
104 #include <linux/netdevice.h>
105 #include <linux/etherdevice.h>
106 #include <linux/delay.h>
107 #include <linux/workqueue.h>
108 #include <linux/init.h>
109 #include <linux/ip.h> /* for iph */
110 #include <linux/in.h> /* for IPPROTO_... */
111 #include <linux/compiler.h>
112 #include <linux/prefetch.h>
113 #include <linux/ethtool.h>
114 #include <linux/timer.h>
115 #include <linux/if_vlan.h>
116 #include <linux/rtnetlink.h>
117 #include <linux/jiffies.h>
118
119 #include <asm/io.h>
120 #include <asm/uaccess.h>
121 #include <asm/system.h>
122
123 #define DRV_NAME "ns83820"
124
125 /* Global parameters. See module_param near the bottom. */
126 static int ihr = 2;
127 static int reset_phy = 0;
128 static int lnksts = 0; /* CFG_LNKSTS bit polarity */
129
130 /* Dprintk is used for more interesting debug events */
131 #undef Dprintk
132 #define Dprintk dprintk
133
134 /* tunables */
135 #define RX_BUF_SIZE 1500 /* 8192 */
136 #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
137 #define NS83820_VLAN_ACCEL_SUPPORT
138 #endif
139
140 /* Must not exceed ~65000. */
141 #define NR_RX_DESC 64
142 #define NR_TX_DESC 128
143
144 /* not tunable */
145 #define REAL_RX_BUF_SIZE (RX_BUF_SIZE + 14) /* rx/tx mac addr + type */
146
147 #define MIN_TX_DESC_FREE 8
148
149 /* register defines */
150 #define CFGCS 0x04
151
152 #define CR_TXE 0x00000001
153 #define CR_TXD 0x00000002
154 /* Ramit : Here's a tip, don't do a RXD immediately followed by an RXE
155 * The Receive engine skips one descriptor and moves
156 * onto the next one!! */
157 #define CR_RXE 0x00000004
158 #define CR_RXD 0x00000008
159 #define CR_TXR 0x00000010
160 #define CR_RXR 0x00000020
161 #define CR_SWI 0x00000080
162 #define CR_RST 0x00000100
163
164 #define PTSCR_EEBIST_FAIL 0x00000001
165 #define PTSCR_EEBIST_EN 0x00000002
166 #define PTSCR_EELOAD_EN 0x00000004
167 #define PTSCR_RBIST_FAIL 0x000001b8
168 #define PTSCR_RBIST_DONE 0x00000200
169 #define PTSCR_RBIST_EN 0x00000400
170 #define PTSCR_RBIST_RST 0x00002000
171
172 #define MEAR_EEDI 0x00000001
173 #define MEAR_EEDO 0x00000002
174 #define MEAR_EECLK 0x00000004
175 #define MEAR_EESEL 0x00000008
176 #define MEAR_MDIO 0x00000010
177 #define MEAR_MDDIR 0x00000020
178 #define MEAR_MDC 0x00000040
179
180 #define ISR_TXDESC3 0x40000000
181 #define ISR_TXDESC2 0x20000000
182 #define ISR_TXDESC1 0x10000000
183 #define ISR_TXDESC0 0x08000000
184 #define ISR_RXDESC3 0x04000000
185 #define ISR_RXDESC2 0x02000000
186 #define ISR_RXDESC1 0x01000000
187 #define ISR_RXDESC0 0x00800000
188 #define ISR_TXRCMP 0x00400000
189 #define ISR_RXRCMP 0x00200000
190 #define ISR_DPERR 0x00100000
191 #define ISR_SSERR 0x00080000
192 #define ISR_RMABT 0x00040000
193 #define ISR_RTABT 0x00020000
194 #define ISR_RXSOVR 0x00010000
195 #define ISR_HIBINT 0x00008000
196 #define ISR_PHY 0x00004000
197 #define ISR_PME 0x00002000
198 #define ISR_SWI 0x00001000
199 #define ISR_MIB 0x00000800
200 #define ISR_TXURN 0x00000400
201 #define ISR_TXIDLE 0x00000200
202 #define ISR_TXERR 0x00000100
203 #define ISR_TXDESC 0x00000080
204 #define ISR_TXOK 0x00000040
205 #define ISR_RXORN 0x00000020
206 #define ISR_RXIDLE 0x00000010
207 #define ISR_RXEARLY 0x00000008
208 #define ISR_RXERR 0x00000004
209 #define ISR_RXDESC 0x00000002
210 #define ISR_RXOK 0x00000001
211
212 #define TXCFG_CSI 0x80000000
213 #define TXCFG_HBI 0x40000000
214 #define TXCFG_MLB 0x20000000
215 #define TXCFG_ATP 0x10000000
216 #define TXCFG_ECRETRY 0x00800000
217 #define TXCFG_BRST_DIS 0x00080000
218 #define TXCFG_MXDMA1024 0x00000000
219 #define TXCFG_MXDMA512 0x00700000
220 #define TXCFG_MXDMA256 0x00600000
221 #define TXCFG_MXDMA128 0x00500000
222 #define TXCFG_MXDMA64 0x00400000
223 #define TXCFG_MXDMA32 0x00300000
224 #define TXCFG_MXDMA16 0x00200000
225 #define TXCFG_MXDMA8 0x00100000
226
227 #define CFG_LNKSTS 0x80000000
228 #define CFG_SPDSTS 0x60000000
229 #define CFG_SPDSTS1 0x40000000
230 #define CFG_SPDSTS0 0x20000000
231 #define CFG_DUPSTS 0x10000000
232 #define CFG_TBI_EN 0x01000000
233 #define CFG_MODE_1000 0x00400000
234 /* Ramit : Dont' ever use AUTO_1000, it never works and is buggy.
235 * Read the Phy response and then configure the MAC accordingly */
236 #define CFG_AUTO_1000 0x00200000
237 #define CFG_PINT_CTL 0x001c0000
238 #define CFG_PINT_DUPSTS 0x00100000
239 #define CFG_PINT_LNKSTS 0x00080000
240 #define CFG_PINT_SPDSTS 0x00040000
241 #define CFG_TMRTEST 0x00020000
242 #define CFG_MRM_DIS 0x00010000
243 #define CFG_MWI_DIS 0x00008000
244 #define CFG_T64ADDR 0x00004000
245 #define CFG_PCI64_DET 0x00002000
246 #define CFG_DATA64_EN 0x00001000
247 #define CFG_M64ADDR 0x00000800
248 #define CFG_PHY_RST 0x00000400
249 #define CFG_PHY_DIS 0x00000200
250 #define CFG_EXTSTS_EN 0x00000100
251 #define CFG_REQALG 0x00000080
252 #define CFG_SB 0x00000040
253 #define CFG_POW 0x00000020
254 #define CFG_EXD 0x00000010
255 #define CFG_PESEL 0x00000008
256 #define CFG_BROM_DIS 0x00000004
257 #define CFG_EXT_125 0x00000002
258 #define CFG_BEM 0x00000001
259
260 #define EXTSTS_UDPPKT 0x00200000
261 #define EXTSTS_TCPPKT 0x00080000
262 #define EXTSTS_IPPKT 0x00020000
263 #define EXTSTS_VPKT 0x00010000
264 #define EXTSTS_VTG_MASK 0x0000ffff
265
266 #define SPDSTS_POLARITY (CFG_SPDSTS1 | CFG_SPDSTS0 | CFG_DUPSTS | (lnksts ? CFG_LNKSTS : 0))
267
268 #define MIBC_MIBS 0x00000008
269 #define MIBC_ACLR 0x00000004
270 #define MIBC_FRZ 0x00000002
271 #define MIBC_WRN 0x00000001
272
273 #define PCR_PSEN (1 << 31)
274 #define PCR_PS_MCAST (1 << 30)
275 #define PCR_PS_DA (1 << 29)
276 #define PCR_STHI_8 (3 << 23)
277 #define PCR_STLO_4 (1 << 23)
278 #define PCR_FFHI_8K (3 << 21)
279 #define PCR_FFLO_4K (1 << 21)
280 #define PCR_PAUSE_CNT 0xFFFE
281
282 #define RXCFG_AEP 0x80000000
283 #define RXCFG_ARP 0x40000000
284 #define RXCFG_STRIPCRC 0x20000000
285 #define RXCFG_RX_FD 0x10000000
286 #define RXCFG_ALP 0x08000000
287 #define RXCFG_AIRL 0x04000000
288 #define RXCFG_MXDMA512 0x00700000
289 #define RXCFG_DRTH 0x0000003e
290 #define RXCFG_DRTH0 0x00000002
291
292 #define RFCR_RFEN 0x80000000
293 #define RFCR_AAB 0x40000000
294 #define RFCR_AAM 0x20000000
295 #define RFCR_AAU 0x10000000
296 #define RFCR_APM 0x08000000
297 #define RFCR_APAT 0x07800000
298 #define RFCR_APAT3 0x04000000
299 #define RFCR_APAT2 0x02000000
300 #define RFCR_APAT1 0x01000000
301 #define RFCR_APAT0 0x00800000
302 #define RFCR_AARP 0x00400000
303 #define RFCR_MHEN 0x00200000
304 #define RFCR_UHEN 0x00100000
305 #define RFCR_ULM 0x00080000
306
307 #define VRCR_RUDPE 0x00000080
308 #define VRCR_RTCPE 0x00000040
309 #define VRCR_RIPE 0x00000020
310 #define VRCR_IPEN 0x00000010
311 #define VRCR_DUTF 0x00000008
312 #define VRCR_DVTF 0x00000004
313 #define VRCR_VTREN 0x00000002
314 #define VRCR_VTDEN 0x00000001
315
316 #define VTCR_PPCHK 0x00000008
317 #define VTCR_GCHK 0x00000004
318 #define VTCR_VPPTI 0x00000002
319 #define VTCR_VGTI 0x00000001
320
321 #define CR 0x00
322 #define CFG 0x04
323 #define MEAR 0x08
324 #define PTSCR 0x0c
325 #define ISR 0x10
326 #define IMR 0x14
327 #define IER 0x18
328 #define IHR 0x1c
329 #define TXDP 0x20
330 #define TXDP_HI 0x24
331 #define TXCFG 0x28
332 #define GPIOR 0x2c
333 #define RXDP 0x30
334 #define RXDP_HI 0x34
335 #define RXCFG 0x38
336 #define PQCR 0x3c
337 #define WCSR 0x40
338 #define PCR 0x44
339 #define RFCR 0x48
340 #define RFDR 0x4c
341
342 #define SRR 0x58
343
344 #define VRCR 0xbc
345 #define VTCR 0xc0
346 #define VDR 0xc4
347 #define CCSR 0xcc
348
349 #define TBICR 0xe0
350 #define TBISR 0xe4
351 #define TANAR 0xe8
352 #define TANLPAR 0xec
353 #define TANER 0xf0
354 #define TESR 0xf4
355
356 #define TBICR_MR_AN_ENABLE 0x00001000
357 #define TBICR_MR_RESTART_AN 0x00000200
358
359 #define TBISR_MR_LINK_STATUS 0x00000020
360 #define TBISR_MR_AN_COMPLETE 0x00000004
361
362 #define TANAR_PS2 0x00000100
363 #define TANAR_PS1 0x00000080
364 #define TANAR_HALF_DUP 0x00000040
365 #define TANAR_FULL_DUP 0x00000020
366
367 #define GPIOR_GP5_OE 0x00000200
368 #define GPIOR_GP4_OE 0x00000100
369 #define GPIOR_GP3_OE 0x00000080
370 #define GPIOR_GP2_OE 0x00000040
371 #define GPIOR_GP1_OE 0x00000020
372 #define GPIOR_GP3_OUT 0x00000004
373 #define GPIOR_GP1_OUT 0x00000001
374
375 #define LINK_AUTONEGOTIATE 0x01
376 #define LINK_DOWN 0x02
377 #define LINK_UP 0x04
378
379 #define HW_ADDR_LEN sizeof(dma_addr_t)
380 #define desc_addr_set(desc, addr) \
381 do { \
382 ((desc)[0] = cpu_to_le32(addr)); \
383 if (HW_ADDR_LEN == 8) \
384 (desc)[1] = cpu_to_le32(((u64)addr) >> 32); \
385 } while(0)
386 #define desc_addr_get(desc) \
387 (le32_to_cpu((desc)[0]) | \
388 (HW_ADDR_LEN == 8 ? ((dma_addr_t)le32_to_cpu((desc)[1]))<<32 : 0))
389
390 #define DESC_LINK 0
391 #define DESC_BUFPTR (DESC_LINK + HW_ADDR_LEN/4)
392 #define DESC_CMDSTS (DESC_BUFPTR + HW_ADDR_LEN/4)
393 #define DESC_EXTSTS (DESC_CMDSTS + 4/4)
394
395 #define CMDSTS_OWN 0x80000000
396 #define CMDSTS_MORE 0x40000000
397 #define CMDSTS_INTR 0x20000000
398 #define CMDSTS_ERR 0x10000000
399 #define CMDSTS_OK 0x08000000
400 #define CMDSTS_RUNT 0x00200000
401 #define CMDSTS_LEN_MASK 0x0000ffff
402
403 #define CMDSTS_DEST_MASK 0x01800000
404 #define CMDSTS_DEST_SELF 0x00800000
405 #define CMDSTS_DEST_MULTI 0x01000000
406
407 #define DESC_SIZE 8 /* Should be cache line sized */
408
409 struct rx_info {
410 spinlock_t lock;
411 int up;
412 long idle;
413
414 struct sk_buff *skbs[NR_RX_DESC];
415
416 __le32 *next_rx_desc;
417 u16 next_rx, next_empty;
418
419 __le32 *descs;
420 dma_addr_t phy_descs;
421 };
422
423
424 struct ns83820 {
425 struct net_device_stats stats;
426 u8 __iomem *base;
427
428 struct pci_dev *pci_dev;
429 struct net_device *ndev;
430
431 #ifdef NS83820_VLAN_ACCEL_SUPPORT
432 struct vlan_group *vlgrp;
433 #endif
434
435 struct rx_info rx_info;
436 struct tasklet_struct rx_tasklet;
437
438 unsigned ihr;
439 struct work_struct tq_refill;
440
441 /* protects everything below. irqsave when using. */
442 spinlock_t misc_lock;
443
444 u32 CFG_cache;
445
446 u32 MEAR_cache;
447 u32 IMR_cache;
448
449 unsigned linkstate;
450
451 spinlock_t tx_lock;
452
453 u16 tx_done_idx;
454 u16 tx_idx;
455 volatile u16 tx_free_idx; /* idx of free desc chain */
456 u16 tx_intr_idx;
457
458 atomic_t nr_tx_skbs;
459 struct sk_buff *tx_skbs[NR_TX_DESC];
460
461 char pad[16] __attribute__((aligned(16)));
462 __le32 *tx_descs;
463 dma_addr_t tx_phy_descs;
464
465 struct timer_list tx_watchdog;
466 };
467
468 static inline struct ns83820 *PRIV(struct net_device *dev)
469 {
470 return netdev_priv(dev);
471 }
472
473 #define __kick_rx(dev) writel(CR_RXE, dev->base + CR)
474
475 static inline void kick_rx(struct net_device *ndev)
476 {
477 struct ns83820 *dev = PRIV(ndev);
478 dprintk("kick_rx: maybe kicking\n");
479 if (test_and_clear_bit(0, &dev->rx_info.idle)) {
480 dprintk("actually kicking\n");
481 writel(dev->rx_info.phy_descs +
482 (4 * DESC_SIZE * dev->rx_info.next_rx),
483 dev->base + RXDP);
484 if (dev->rx_info.next_rx == dev->rx_info.next_empty)
485 printk(KERN_DEBUG "%s: uh-oh: next_rx == next_empty???\n",
486 ndev->name);
487 __kick_rx(dev);
488 }
489 }
490
491 //free = (tx_done_idx + NR_TX_DESC-2 - free_idx) % NR_TX_DESC
492 #define start_tx_okay(dev) \
493 (((NR_TX_DESC-2 + dev->tx_done_idx - dev->tx_free_idx) % NR_TX_DESC) > MIN_TX_DESC_FREE)
494
495
496 #ifdef NS83820_VLAN_ACCEL_SUPPORT
497 static void ns83820_vlan_rx_register(struct net_device *ndev, struct vlan_group *grp)
498 {
499 struct ns83820 *dev = PRIV(ndev);
500
501 spin_lock_irq(&dev->misc_lock);
502 spin_lock(&dev->tx_lock);
503
504 dev->vlgrp = grp;
505
506 spin_unlock(&dev->tx_lock);
507 spin_unlock_irq(&dev->misc_lock);
508 }
509
510 static void ns83820_vlan_rx_kill_vid(struct net_device *ndev, unsigned short vid)
511 {
512 struct ns83820 *dev = PRIV(ndev);
513
514 spin_lock_irq(&dev->misc_lock);
515 spin_lock(&dev->tx_lock);
516 vlan_group_set_device(dev->vlgrp, vid, NULL);
517 spin_unlock(&dev->tx_lock);
518 spin_unlock_irq(&dev->misc_lock);
519 }
520 #endif
521
522 /* Packet Receiver
523 *
524 * The hardware supports linked lists of receive descriptors for
525 * which ownership is transfered back and forth by means of an
526 * ownership bit. While the hardware does support the use of a
527 * ring for receive descriptors, we only make use of a chain in
528 * an attempt to reduce bus traffic under heavy load scenarios.
529 * This will also make bugs a bit more obvious. The current code
530 * only makes use of a single rx chain; I hope to implement
531 * priority based rx for version 1.0. Goal: even under overload
532 * conditions, still route realtime traffic with as low jitter as
533 * possible.
534 */
535 static inline void build_rx_desc(struct ns83820 *dev, __le32 *desc, dma_addr_t link, dma_addr_t buf, u32 cmdsts, u32 extsts)
536 {
537 desc_addr_set(desc + DESC_LINK, link);
538 desc_addr_set(desc + DESC_BUFPTR, buf);
539 desc[DESC_EXTSTS] = cpu_to_le32(extsts);
540 mb();
541 desc[DESC_CMDSTS] = cpu_to_le32(cmdsts);
542 }
543
544 #define nr_rx_empty(dev) ((NR_RX_DESC-2 + dev->rx_info.next_rx - dev->rx_info.next_empty) % NR_RX_DESC)
545 static inline int ns83820_add_rx_skb(struct ns83820 *dev, struct sk_buff *skb)
546 {
547 unsigned next_empty;
548 u32 cmdsts;
549 __le32 *sg;
550 dma_addr_t buf;
551
552 next_empty = dev->rx_info.next_empty;
553
554 /* don't overrun last rx marker */
555 if (unlikely(nr_rx_empty(dev) <= 2)) {
556 kfree_skb(skb);
557 return 1;
558 }
559
560 #if 0
561 dprintk("next_empty[%d] nr_used[%d] next_rx[%d]\n",
562 dev->rx_info.next_empty,
563 dev->rx_info.nr_used,
564 dev->rx_info.next_rx
565 );
566 #endif
567
568 sg = dev->rx_info.descs + (next_empty * DESC_SIZE);
569 BUG_ON(NULL != dev->rx_info.skbs[next_empty]);
570 dev->rx_info.skbs[next_empty] = skb;
571
572 dev->rx_info.next_empty = (next_empty + 1) % NR_RX_DESC;
573 cmdsts = REAL_RX_BUF_SIZE | CMDSTS_INTR;
574 buf = pci_map_single(dev->pci_dev, skb->data,
575 REAL_RX_BUF_SIZE, PCI_DMA_FROMDEVICE);
576 build_rx_desc(dev, sg, 0, buf, cmdsts, 0);
577 /* update link of previous rx */
578 if (likely(next_empty != dev->rx_info.next_rx))
579 dev->rx_info.descs[((NR_RX_DESC + next_empty - 1) % NR_RX_DESC) * DESC_SIZE] = cpu_to_le32(dev->rx_info.phy_descs + (next_empty * DESC_SIZE * 4));
580
581 return 0;
582 }
583
584 static inline int rx_refill(struct net_device *ndev, gfp_t gfp)
585 {
586 struct ns83820 *dev = PRIV(ndev);
587 unsigned i;
588 unsigned long flags = 0;
589
590 if (unlikely(nr_rx_empty(dev) <= 2))
591 return 0;
592
593 dprintk("rx_refill(%p)\n", ndev);
594 if (gfp == GFP_ATOMIC)
595 spin_lock_irqsave(&dev->rx_info.lock, flags);
596 for (i=0; i<NR_RX_DESC; i++) {
597 struct sk_buff *skb;
598 long res;
599 /* extra 16 bytes for alignment */
600 skb = __dev_alloc_skb(REAL_RX_BUF_SIZE+16, gfp);
601 if (unlikely(!skb))
602 break;
603
604 res = (long)skb->data & 0xf;
605 res = 0x10 - res;
606 res &= 0xf;
607 skb_reserve(skb, res);
608
609 if (gfp != GFP_ATOMIC)
610 spin_lock_irqsave(&dev->rx_info.lock, flags);
611 res = ns83820_add_rx_skb(dev, skb);
612 if (gfp != GFP_ATOMIC)
613 spin_unlock_irqrestore(&dev->rx_info.lock, flags);
614 if (res) {
615 i = 1;
616 break;
617 }
618 }
619 if (gfp == GFP_ATOMIC)
620 spin_unlock_irqrestore(&dev->rx_info.lock, flags);
621
622 return i ? 0 : -ENOMEM;
623 }
624
625 static void FASTCALL(rx_refill_atomic(struct net_device *ndev));
626 static void fastcall rx_refill_atomic(struct net_device *ndev)
627 {
628 rx_refill(ndev, GFP_ATOMIC);
629 }
630
631 /* REFILL */
632 static inline void queue_refill(struct work_struct *work)
633 {
634 struct ns83820 *dev = container_of(work, struct ns83820, tq_refill);
635 struct net_device *ndev = dev->ndev;
636
637 rx_refill(ndev, GFP_KERNEL);
638 if (dev->rx_info.up)
639 kick_rx(ndev);
640 }
641
642 static inline void clear_rx_desc(struct ns83820 *dev, unsigned i)
643 {
644 build_rx_desc(dev, dev->rx_info.descs + (DESC_SIZE * i), 0, 0, CMDSTS_OWN, 0);
645 }
646
647 static void FASTCALL(phy_intr(struct net_device *ndev));
648 static void fastcall phy_intr(struct net_device *ndev)
649 {
650 struct ns83820 *dev = PRIV(ndev);
651 static const char *speeds[] = { "10", "100", "1000", "1000(?)", "1000F" };
652 u32 cfg, new_cfg;
653 u32 tbisr, tanar, tanlpar;
654 int speed, fullduplex, newlinkstate;
655
656 cfg = readl(dev->base + CFG) ^ SPDSTS_POLARITY;
657
658 if (dev->CFG_cache & CFG_TBI_EN) {
659 /* we have an optical transceiver */
660 tbisr = readl(dev->base + TBISR);
661 tanar = readl(dev->base + TANAR);
662 tanlpar = readl(dev->base + TANLPAR);
663 dprintk("phy_intr: tbisr=%08x, tanar=%08x, tanlpar=%08x\n",
664 tbisr, tanar, tanlpar);
665
666 if ( (fullduplex = (tanlpar & TANAR_FULL_DUP)
667 && (tanar & TANAR_FULL_DUP)) ) {
668
669 /* both of us are full duplex */
670 writel(readl(dev->base + TXCFG)
671 | TXCFG_CSI | TXCFG_HBI | TXCFG_ATP,
672 dev->base + TXCFG);
673 writel(readl(dev->base + RXCFG) | RXCFG_RX_FD,
674 dev->base + RXCFG);
675 /* Light up full duplex LED */
676 writel(readl(dev->base + GPIOR) | GPIOR_GP1_OUT,
677 dev->base + GPIOR);
678
679 } else if(((tanlpar & TANAR_HALF_DUP)
680 && (tanar & TANAR_HALF_DUP))
681 || ((tanlpar & TANAR_FULL_DUP)
682 && (tanar & TANAR_HALF_DUP))
683 || ((tanlpar & TANAR_HALF_DUP)
684 && (tanar & TANAR_FULL_DUP))) {
685
686 /* one or both of us are half duplex */
687 writel((readl(dev->base + TXCFG)
688 & ~(TXCFG_CSI | TXCFG_HBI)) | TXCFG_ATP,
689 dev->base + TXCFG);
690 writel(readl(dev->base + RXCFG) & ~RXCFG_RX_FD,
691 dev->base + RXCFG);
692 /* Turn off full duplex LED */
693 writel(readl(dev->base + GPIOR) & ~GPIOR_GP1_OUT,
694 dev->base + GPIOR);
695 }
696
697 speed = 4; /* 1000F */
698
699 } else {
700 /* we have a copper transceiver */
701 new_cfg = dev->CFG_cache & ~(CFG_SB | CFG_MODE_1000 | CFG_SPDSTS);
702
703 if (cfg & CFG_SPDSTS1)
704 new_cfg |= CFG_MODE_1000;
705 else
706 new_cfg &= ~CFG_MODE_1000;
707
708 speed = ((cfg / CFG_SPDSTS0) & 3);
709 fullduplex = (cfg & CFG_DUPSTS);
710
711 if (fullduplex) {
712 new_cfg |= CFG_SB;
713 writel(readl(dev->base + TXCFG)
714 | TXCFG_CSI | TXCFG_HBI,
715 dev->base + TXCFG);
716 writel(readl(dev->base + RXCFG) | RXCFG_RX_FD,
717 dev->base + RXCFG);
718 } else {
719 writel(readl(dev->base + TXCFG)
720 & ~(TXCFG_CSI | TXCFG_HBI),
721 dev->base + TXCFG);
722 writel(readl(dev->base + RXCFG) & ~(RXCFG_RX_FD),
723 dev->base + RXCFG);
724 }
725
726 if ((cfg & CFG_LNKSTS) &&
727 ((new_cfg ^ dev->CFG_cache) != 0)) {
728 writel(new_cfg, dev->base + CFG);
729 dev->CFG_cache = new_cfg;
730 }
731
732 dev->CFG_cache &= ~CFG_SPDSTS;
733 dev->CFG_cache |= cfg & CFG_SPDSTS;
734 }
735
736 newlinkstate = (cfg & CFG_LNKSTS) ? LINK_UP : LINK_DOWN;
737
738 if (newlinkstate & LINK_UP
739 && dev->linkstate != newlinkstate) {
740 netif_start_queue(ndev);
741 netif_wake_queue(ndev);
742 printk(KERN_INFO "%s: link now %s mbps, %s duplex and up.\n",
743 ndev->name,
744 speeds[speed],
745 fullduplex ? "full" : "half");
746 } else if (newlinkstate & LINK_DOWN
747 && dev->linkstate != newlinkstate) {
748 netif_stop_queue(ndev);
749 printk(KERN_INFO "%s: link now down.\n", ndev->name);
750 }
751
752 dev->linkstate = newlinkstate;
753 }
754
755 static int ns83820_setup_rx(struct net_device *ndev)
756 {
757 struct ns83820 *dev = PRIV(ndev);
758 unsigned i;
759 int ret;
760
761 dprintk("ns83820_setup_rx(%p)\n", ndev);
762
763 dev->rx_info.idle = 1;
764 dev->rx_info.next_rx = 0;
765 dev->rx_info.next_rx_desc = dev->rx_info.descs;
766 dev->rx_info.next_empty = 0;
767
768 for (i=0; i<NR_RX_DESC; i++)
769 clear_rx_desc(dev, i);
770
771 writel(0, dev->base + RXDP_HI);
772 writel(dev->rx_info.phy_descs, dev->base + RXDP);
773
774 ret = rx_refill(ndev, GFP_KERNEL);
775 if (!ret) {
776 dprintk("starting receiver\n");
777 /* prevent the interrupt handler from stomping on us */
778 spin_lock_irq(&dev->rx_info.lock);
779
780 writel(0x0001, dev->base + CCSR);
781 writel(0, dev->base + RFCR);
782 writel(0x7fc00000, dev->base + RFCR);
783 writel(0xffc00000, dev->base + RFCR);
784
785 dev->rx_info.up = 1;
786
787 phy_intr(ndev);
788
789 /* Okay, let it rip */
790 spin_lock_irq(&dev->misc_lock);
791 dev->IMR_cache |= ISR_PHY;
792 dev->IMR_cache |= ISR_RXRCMP;
793 //dev->IMR_cache |= ISR_RXERR;
794 //dev->IMR_cache |= ISR_RXOK;
795 dev->IMR_cache |= ISR_RXORN;
796 dev->IMR_cache |= ISR_RXSOVR;
797 dev->IMR_cache |= ISR_RXDESC;
798 dev->IMR_cache |= ISR_RXIDLE;
799 dev->IMR_cache |= ISR_TXDESC;
800 dev->IMR_cache |= ISR_TXIDLE;
801
802 writel(dev->IMR_cache, dev->base + IMR);
803 writel(1, dev->base + IER);
804 spin_unlock(&dev->misc_lock);
805
806 kick_rx(ndev);
807
808 spin_unlock_irq(&dev->rx_info.lock);
809 }
810 return ret;
811 }
812
813 static void ns83820_cleanup_rx(struct ns83820 *dev)
814 {
815 unsigned i;
816 unsigned long flags;
817
818 dprintk("ns83820_cleanup_rx(%p)\n", dev);
819
820 /* disable receive interrupts */
821 spin_lock_irqsave(&dev->misc_lock, flags);
822 dev->IMR_cache &= ~(ISR_RXOK | ISR_RXDESC | ISR_RXERR | ISR_RXEARLY | ISR_RXIDLE);
823 writel(dev->IMR_cache, dev->base + IMR);
824 spin_unlock_irqrestore(&dev->misc_lock, flags);
825
826 /* synchronize with the interrupt handler and kill it */
827 dev->rx_info.up = 0;
828 synchronize_irq(dev->pci_dev->irq);
829
830 /* touch the pci bus... */
831 readl(dev->base + IMR);
832
833 /* assumes the transmitter is already disabled and reset */
834 writel(0, dev->base + RXDP_HI);
835 writel(0, dev->base + RXDP);
836
837 for (i=0; i<NR_RX_DESC; i++) {
838 struct sk_buff *skb = dev->rx_info.skbs[i];
839 dev->rx_info.skbs[i] = NULL;
840 clear_rx_desc(dev, i);
841 if (skb)
842 kfree_skb(skb);
843 }
844 }
845
846 static void FASTCALL(ns83820_rx_kick(struct net_device *ndev));
847 static void fastcall ns83820_rx_kick(struct net_device *ndev)
848 {
849 struct ns83820 *dev = PRIV(ndev);
850 /*if (nr_rx_empty(dev) >= NR_RX_DESC/4)*/ {
851 if (dev->rx_info.up) {
852 rx_refill_atomic(ndev);
853 kick_rx(ndev);
854 }
855 }
856
857 if (dev->rx_info.up && nr_rx_empty(dev) > NR_RX_DESC*3/4)
858 schedule_work(&dev->tq_refill);
859 else
860 kick_rx(ndev);
861 if (dev->rx_info.idle)
862 printk(KERN_DEBUG "%s: BAD\n", ndev->name);
863 }
864
865 /* rx_irq
866 *
867 */
868 static void FASTCALL(rx_irq(struct net_device *ndev));
869 static void fastcall rx_irq(struct net_device *ndev)
870 {
871 struct ns83820 *dev = PRIV(ndev);
872 struct rx_info *info = &dev->rx_info;
873 unsigned next_rx;
874 int rx_rc, len;
875 u32 cmdsts;
876 __le32 *desc;
877 unsigned long flags;
878 int nr = 0;
879
880 dprintk("rx_irq(%p)\n", ndev);
881 dprintk("rxdp: %08x, descs: %08lx next_rx[%d]: %p next_empty[%d]: %p\n",
882 readl(dev->base + RXDP),
883 (long)(dev->rx_info.phy_descs),
884 (int)dev->rx_info.next_rx,
885 (dev->rx_info.descs + (DESC_SIZE * dev->rx_info.next_rx)),
886 (int)dev->rx_info.next_empty,
887 (dev->rx_info.descs + (DESC_SIZE * dev->rx_info.next_empty))
888 );
889
890 spin_lock_irqsave(&info->lock, flags);
891 if (!info->up)
892 goto out;
893
894 dprintk("walking descs\n");
895 next_rx = info->next_rx;
896 desc = info->next_rx_desc;
897 while ((CMDSTS_OWN & (cmdsts = le32_to_cpu(desc[DESC_CMDSTS]))) &&
898 (cmdsts != CMDSTS_OWN)) {
899 struct sk_buff *skb;
900 u32 extsts = le32_to_cpu(desc[DESC_EXTSTS]);
901 dma_addr_t bufptr = desc_addr_get(desc + DESC_BUFPTR);
902
903 dprintk("cmdsts: %08x\n", cmdsts);
904 dprintk("link: %08x\n", cpu_to_le32(desc[DESC_LINK]));
905 dprintk("extsts: %08x\n", extsts);
906
907 skb = info->skbs[next_rx];
908 info->skbs[next_rx] = NULL;
909 info->next_rx = (next_rx + 1) % NR_RX_DESC;
910
911 mb();
912 clear_rx_desc(dev, next_rx);
913
914 pci_unmap_single(dev->pci_dev, bufptr,
915 RX_BUF_SIZE, PCI_DMA_FROMDEVICE);
916 len = cmdsts & CMDSTS_LEN_MASK;
917 #ifdef NS83820_VLAN_ACCEL_SUPPORT
918 /* NH: As was mentioned below, this chip is kinda
919 * brain dead about vlan tag stripping. Frames
920 * that are 64 bytes with a vlan header appended
921 * like arp frames, or pings, are flagged as Runts
922 * when the tag is stripped and hardware. This
923 * also means that the OK bit in the descriptor
924 * is cleared when the frame comes in so we have
925 * to do a specific length check here to make sure
926 * the frame would have been ok, had we not stripped
927 * the tag.
928 */
929 if (likely((CMDSTS_OK & cmdsts) ||
930 ((cmdsts & CMDSTS_RUNT) && len >= 56))) {
931 #else
932 if (likely(CMDSTS_OK & cmdsts)) {
933 #endif
934 skb_put(skb, len);
935 if (unlikely(!skb))
936 goto netdev_mangle_me_harder_failed;
937 if (cmdsts & CMDSTS_DEST_MULTI)
938 dev->stats.multicast ++;
939 dev->stats.rx_packets ++;
940 dev->stats.rx_bytes += len;
941 if ((extsts & 0x002a0000) && !(extsts & 0x00540000)) {
942 skb->ip_summed = CHECKSUM_UNNECESSARY;
943 } else {
944 skb->ip_summed = CHECKSUM_NONE;
945 }
946 skb->protocol = eth_type_trans(skb, ndev);
947 #ifdef NS83820_VLAN_ACCEL_SUPPORT
948 if(extsts & EXTSTS_VPKT) {
949 unsigned short tag;
950 tag = ntohs(extsts & EXTSTS_VTG_MASK);
951 rx_rc = vlan_hwaccel_rx(skb,dev->vlgrp,tag);
952 } else {
953 rx_rc = netif_rx(skb);
954 }
955 #else
956 rx_rc = netif_rx(skb);
957 #endif
958 if (NET_RX_DROP == rx_rc) {
959 netdev_mangle_me_harder_failed:
960 dev->stats.rx_dropped ++;
961 }
962 } else {
963 kfree_skb(skb);
964 }
965
966 nr++;
967 next_rx = info->next_rx;
968 desc = info->descs + (DESC_SIZE * next_rx);
969 }
970 info->next_rx = next_rx;
971 info->next_rx_desc = info->descs + (DESC_SIZE * next_rx);
972
973 out:
974 if (0 && !nr) {
975 Dprintk("dazed: cmdsts_f: %08x\n", cmdsts);
976 }
977
978 spin_unlock_irqrestore(&info->lock, flags);
979 }
980
981 static void rx_action(unsigned long _dev)
982 {
983 struct net_device *ndev = (void *)_dev;
984 struct ns83820 *dev = PRIV(ndev);
985 rx_irq(ndev);
986 writel(ihr, dev->base + IHR);
987
988 spin_lock_irq(&dev->misc_lock);
989 dev->IMR_cache |= ISR_RXDESC;
990 writel(dev->IMR_cache, dev->base + IMR);
991 spin_unlock_irq(&dev->misc_lock);
992
993 rx_irq(ndev);
994 ns83820_rx_kick(ndev);
995 }
996
997 /* Packet Transmit code
998 */
999 static inline void kick_tx(struct ns83820 *dev)
1000 {
1001 dprintk("kick_tx(%p): tx_idx=%d free_idx=%d\n",
1002 dev, dev->tx_idx, dev->tx_free_idx);
1003 writel(CR_TXE, dev->base + CR);
1004 }
1005
1006 /* No spinlock needed on the transmit irq path as the interrupt handler is
1007 * serialized.
1008 */
1009 static void do_tx_done(struct net_device *ndev)
1010 {
1011 struct ns83820 *dev = PRIV(ndev);
1012 u32 cmdsts, tx_done_idx;
1013 __le32 *desc;
1014
1015 dprintk("do_tx_done(%p)\n", ndev);
1016 tx_done_idx = dev->tx_done_idx;
1017 desc = dev->tx_descs + (tx_done_idx * DESC_SIZE);
1018
1019 dprintk("tx_done_idx=%d free_idx=%d cmdsts=%08x\n",
1020 tx_done_idx, dev->tx_free_idx, le32_to_cpu(desc[DESC_CMDSTS]));
1021 while ((tx_done_idx != dev->tx_free_idx) &&
1022 !(CMDSTS_OWN & (cmdsts = le32_to_cpu(desc[DESC_CMDSTS]))) ) {
1023 struct sk_buff *skb;
1024 unsigned len;
1025 dma_addr_t addr;
1026
1027 if (cmdsts & CMDSTS_ERR)
1028 dev->stats.tx_errors ++;
1029 if (cmdsts & CMDSTS_OK)
1030 dev->stats.tx_packets ++;
1031 if (cmdsts & CMDSTS_OK)
1032 dev->stats.tx_bytes += cmdsts & 0xffff;
1033
1034 dprintk("tx_done_idx=%d free_idx=%d cmdsts=%08x\n",
1035 tx_done_idx, dev->tx_free_idx, cmdsts);
1036 skb = dev->tx_skbs[tx_done_idx];
1037 dev->tx_skbs[tx_done_idx] = NULL;
1038 dprintk("done(%p)\n", skb);
1039
1040 len = cmdsts & CMDSTS_LEN_MASK;
1041 addr = desc_addr_get(desc + DESC_BUFPTR);
1042 if (skb) {
1043 pci_unmap_single(dev->pci_dev,
1044 addr,
1045 len,
1046 PCI_DMA_TODEVICE);
1047 dev_kfree_skb_irq(skb);
1048 atomic_dec(&dev->nr_tx_skbs);
1049 } else
1050 pci_unmap_page(dev->pci_dev,
1051 addr,
1052 len,
1053 PCI_DMA_TODEVICE);
1054
1055 tx_done_idx = (tx_done_idx + 1) % NR_TX_DESC;
1056 dev->tx_done_idx = tx_done_idx;
1057 desc[DESC_CMDSTS] = cpu_to_le32(0);
1058 mb();
1059 desc = dev->tx_descs + (tx_done_idx * DESC_SIZE);
1060 }
1061
1062 /* Allow network stack to resume queueing packets after we've
1063 * finished transmitting at least 1/4 of the packets in the queue.
1064 */
1065 if (netif_queue_stopped(ndev) && start_tx_okay(dev)) {
1066 dprintk("start_queue(%p)\n", ndev);
1067 netif_start_queue(ndev);
1068 netif_wake_queue(ndev);
1069 }
1070 }
1071
1072 static void ns83820_cleanup_tx(struct ns83820 *dev)
1073 {
1074 unsigned i;
1075
1076 for (i=0; i<NR_TX_DESC; i++) {
1077 struct sk_buff *skb = dev->tx_skbs[i];
1078 dev->tx_skbs[i] = NULL;
1079 if (skb) {
1080 __le32 *desc = dev->tx_descs + (i * DESC_SIZE);
1081 pci_unmap_single(dev->pci_dev,
1082 desc_addr_get(desc + DESC_BUFPTR),
1083 le32_to_cpu(desc[DESC_CMDSTS]) & CMDSTS_LEN_MASK,
1084 PCI_DMA_TODEVICE);
1085 dev_kfree_skb_irq(skb);
1086 atomic_dec(&dev->nr_tx_skbs);
1087 }
1088 }
1089
1090 memset(dev->tx_descs, 0, NR_TX_DESC * DESC_SIZE * 4);
1091 }
1092
1093 /* transmit routine. This code relies on the network layer serializing
1094 * its calls in, but will run happily in parallel with the interrupt
1095 * handler. This code currently has provisions for fragmenting tx buffers
1096 * while trying to track down a bug in either the zero copy code or
1097 * the tx fifo (hence the MAX_FRAG_LEN).
1098 */
1099 static int ns83820_hard_start_xmit(struct sk_buff *skb, struct net_device *ndev)
1100 {
1101 struct ns83820 *dev = PRIV(ndev);
1102 u32 free_idx, cmdsts, extsts;
1103 int nr_free, nr_frags;
1104 unsigned tx_done_idx, last_idx;
1105 dma_addr_t buf;
1106 unsigned len;
1107 skb_frag_t *frag;
1108 int stopped = 0;
1109 int do_intr = 0;
1110 volatile __le32 *first_desc;
1111
1112 dprintk("ns83820_hard_start_xmit\n");
1113
1114 nr_frags = skb_shinfo(skb)->nr_frags;
1115 again:
1116 if (unlikely(dev->CFG_cache & CFG_LNKSTS)) {
1117 netif_stop_queue(ndev);
1118 if (unlikely(dev->CFG_cache & CFG_LNKSTS))
1119 return 1;
1120 netif_start_queue(ndev);
1121 }
1122
1123 last_idx = free_idx = dev->tx_free_idx;
1124 tx_done_idx = dev->tx_done_idx;
1125 nr_free = (tx_done_idx + NR_TX_DESC-2 - free_idx) % NR_TX_DESC;
1126 nr_free -= 1;
1127 if (nr_free <= nr_frags) {
1128 dprintk("stop_queue - not enough(%p)\n", ndev);
1129 netif_stop_queue(ndev);
1130
1131 /* Check again: we may have raced with a tx done irq */
1132 if (dev->tx_done_idx != tx_done_idx) {
1133 dprintk("restart queue(%p)\n", ndev);
1134 netif_start_queue(ndev);
1135 goto again;
1136 }
1137 return 1;
1138 }
1139
1140 if (free_idx == dev->tx_intr_idx) {
1141 do_intr = 1;
1142 dev->tx_intr_idx = (dev->tx_intr_idx + NR_TX_DESC/4) % NR_TX_DESC;
1143 }
1144
1145 nr_free -= nr_frags;
1146 if (nr_free < MIN_TX_DESC_FREE) {
1147 dprintk("stop_queue - last entry(%p)\n", ndev);
1148 netif_stop_queue(ndev);
1149 stopped = 1;
1150 }
1151
1152 frag = skb_shinfo(skb)->frags;
1153 if (!nr_frags)
1154 frag = NULL;
1155 extsts = 0;
1156 if (skb->ip_summed == CHECKSUM_PARTIAL) {
1157 extsts |= EXTSTS_IPPKT;
1158 if (IPPROTO_TCP == ip_hdr(skb)->protocol)
1159 extsts |= EXTSTS_TCPPKT;
1160 else if (IPPROTO_UDP == ip_hdr(skb)->protocol)
1161 extsts |= EXTSTS_UDPPKT;
1162 }
1163
1164 #ifdef NS83820_VLAN_ACCEL_SUPPORT
1165 if(vlan_tx_tag_present(skb)) {
1166 /* fetch the vlan tag info out of the
1167 * ancilliary data if the vlan code
1168 * is using hw vlan acceleration
1169 */
1170 short tag = vlan_tx_tag_get(skb);
1171 extsts |= (EXTSTS_VPKT | htons(tag));
1172 }
1173 #endif
1174
1175 len = skb->len;
1176 if (nr_frags)
1177 len -= skb->data_len;
1178 buf = pci_map_single(dev->pci_dev, skb->data, len, PCI_DMA_TODEVICE);
1179
1180 first_desc = dev->tx_descs + (free_idx * DESC_SIZE);
1181
1182 for (;;) {
1183 volatile __le32 *desc = dev->tx_descs + (free_idx * DESC_SIZE);
1184
1185 dprintk("frag[%3u]: %4u @ 0x%08Lx\n", free_idx, len,
1186 (unsigned long long)buf);
1187 last_idx = free_idx;
1188 free_idx = (free_idx + 1) % NR_TX_DESC;
1189 desc[DESC_LINK] = cpu_to_le32(dev->tx_phy_descs + (free_idx * DESC_SIZE * 4));
1190 desc_addr_set(desc + DESC_BUFPTR, buf);
1191 desc[DESC_EXTSTS] = cpu_to_le32(extsts);
1192
1193 cmdsts = ((nr_frags) ? CMDSTS_MORE : do_intr ? CMDSTS_INTR : 0);
1194 cmdsts |= (desc == first_desc) ? 0 : CMDSTS_OWN;
1195 cmdsts |= len;
1196 desc[DESC_CMDSTS] = cpu_to_le32(cmdsts);
1197
1198 if (!nr_frags)
1199 break;
1200
1201 buf = pci_map_page(dev->pci_dev, frag->page,
1202 frag->page_offset,
1203 frag->size, PCI_DMA_TODEVICE);
1204 dprintk("frag: buf=%08Lx page=%08lx offset=%08lx\n",
1205 (long long)buf, (long) page_to_pfn(frag->page),
1206 frag->page_offset);
1207 len = frag->size;
1208 frag++;
1209 nr_frags--;
1210 }
1211 dprintk("done pkt\n");
1212
1213 spin_lock_irq(&dev->tx_lock);
1214 dev->tx_skbs[last_idx] = skb;
1215 first_desc[DESC_CMDSTS] |= cpu_to_le32(CMDSTS_OWN);
1216 dev->tx_free_idx = free_idx;
1217 atomic_inc(&dev->nr_tx_skbs);
1218 spin_unlock_irq(&dev->tx_lock);
1219
1220 kick_tx(dev);
1221
1222 /* Check again: we may have raced with a tx done irq */
1223 if (stopped && (dev->tx_done_idx != tx_done_idx) && start_tx_okay(dev))
1224 netif_start_queue(ndev);
1225
1226 /* set the transmit start time to catch transmit timeouts */
1227 ndev->trans_start = jiffies;
1228 return 0;
1229 }
1230
1231 static void ns83820_update_stats(struct ns83820 *dev)
1232 {
1233 u8 __iomem *base = dev->base;
1234
1235 /* the DP83820 will freeze counters, so we need to read all of them */
1236 dev->stats.rx_errors += readl(base + 0x60) & 0xffff;
1237 dev->stats.rx_crc_errors += readl(base + 0x64) & 0xffff;
1238 dev->stats.rx_missed_errors += readl(base + 0x68) & 0xffff;
1239 dev->stats.rx_frame_errors += readl(base + 0x6c) & 0xffff;
1240 /*dev->stats.rx_symbol_errors +=*/ readl(base + 0x70);
1241 dev->stats.rx_length_errors += readl(base + 0x74) & 0xffff;
1242 dev->stats.rx_length_errors += readl(base + 0x78) & 0xffff;
1243 /*dev->stats.rx_badopcode_errors += */ readl(base + 0x7c);
1244 /*dev->stats.rx_pause_count += */ readl(base + 0x80);
1245 /*dev->stats.tx_pause_count += */ readl(base + 0x84);
1246 dev->stats.tx_carrier_errors += readl(base + 0x88) & 0xff;
1247 }
1248
1249 static struct net_device_stats *ns83820_get_stats(struct net_device *ndev)
1250 {
1251 struct ns83820 *dev = PRIV(ndev);
1252
1253 /* somewhat overkill */
1254 spin_lock_irq(&dev->misc_lock);
1255 ns83820_update_stats(dev);
1256 spin_unlock_irq(&dev->misc_lock);
1257
1258 return &dev->stats;
1259 }
1260
1261 static void ns83820_get_drvinfo(struct net_device *ndev, struct ethtool_drvinfo *info)
1262 {
1263 struct ns83820 *dev = PRIV(ndev);
1264 strcpy(info->driver, "ns83820");
1265 strcpy(info->version, VERSION);
1266 strcpy(info->bus_info, pci_name(dev->pci_dev));
1267 }
1268
1269 static u32 ns83820_get_link(struct net_device *ndev)
1270 {
1271 struct ns83820 *dev = PRIV(ndev);
1272 u32 cfg = readl(dev->base + CFG) ^ SPDSTS_POLARITY;
1273 return cfg & CFG_LNKSTS ? 1 : 0;
1274 }
1275
1276 static const struct ethtool_ops ops = {
1277 .get_drvinfo = ns83820_get_drvinfo,
1278 .get_link = ns83820_get_link
1279 };
1280
1281 /* this function is called in irq context from the ISR */
1282 static void ns83820_mib_isr(struct ns83820 *dev)
1283 {
1284 unsigned long flags;
1285 spin_lock_irqsave(&dev->misc_lock, flags);
1286 ns83820_update_stats(dev);
1287 spin_unlock_irqrestore(&dev->misc_lock, flags);
1288 }
1289
1290 static void ns83820_do_isr(struct net_device *ndev, u32 isr);
1291 static irqreturn_t ns83820_irq(int foo, void *data)
1292 {
1293 struct net_device *ndev = data;
1294 struct ns83820 *dev = PRIV(ndev);
1295 u32 isr;
1296 dprintk("ns83820_irq(%p)\n", ndev);
1297
1298 dev->ihr = 0;
1299
1300 isr = readl(dev->base + ISR);
1301 dprintk("irq: %08x\n", isr);
1302 ns83820_do_isr(ndev, isr);
1303 return IRQ_HANDLED;
1304 }
1305
1306 static void ns83820_do_isr(struct net_device *ndev, u32 isr)
1307 {
1308 struct ns83820 *dev = PRIV(ndev);
1309 unsigned long flags;
1310
1311 #ifdef DEBUG
1312 if (isr & ~(ISR_PHY | ISR_RXDESC | ISR_RXEARLY | ISR_RXOK | ISR_RXERR | ISR_TXIDLE | ISR_TXOK | ISR_TXDESC))
1313 Dprintk("odd isr? 0x%08x\n", isr);
1314 #endif
1315
1316 if (ISR_RXIDLE & isr) {
1317 dev->rx_info.idle = 1;
1318 Dprintk("oh dear, we are idle\n");
1319 ns83820_rx_kick(ndev);
1320 }
1321
1322 if ((ISR_RXDESC | ISR_RXOK) & isr) {
1323 prefetch(dev->rx_info.next_rx_desc);
1324
1325 spin_lock_irqsave(&dev->misc_lock, flags);
1326 dev->IMR_cache &= ~(ISR_RXDESC | ISR_RXOK);
1327 writel(dev->IMR_cache, dev->base + IMR);
1328 spin_unlock_irqrestore(&dev->misc_lock, flags);
1329
1330 tasklet_schedule(&dev->rx_tasklet);
1331 //rx_irq(ndev);
1332 //writel(4, dev->base + IHR);
1333 }
1334
1335 if ((ISR_RXIDLE | ISR_RXORN | ISR_RXDESC | ISR_RXOK | ISR_RXERR) & isr)
1336 ns83820_rx_kick(ndev);
1337
1338 if (unlikely(ISR_RXSOVR & isr)) {
1339 //printk("overrun: rxsovr\n");
1340 dev->stats.rx_fifo_errors ++;
1341 }
1342
1343 if (unlikely(ISR_RXORN & isr)) {
1344 //printk("overrun: rxorn\n");
1345 dev->stats.rx_fifo_errors ++;
1346 }
1347
1348 if ((ISR_RXRCMP & isr) && dev->rx_info.up)
1349 writel(CR_RXE, dev->base + CR);
1350
1351 if (ISR_TXIDLE & isr) {
1352 u32 txdp;
1353 txdp = readl(dev->base + TXDP);
1354 dprintk("txdp: %08x\n", txdp);
1355 txdp -= dev->tx_phy_descs;
1356 dev->tx_idx = txdp / (DESC_SIZE * 4);
1357 if (dev->tx_idx >= NR_TX_DESC) {
1358 printk(KERN_ALERT "%s: BUG -- txdp out of range\n", ndev->name);
1359 dev->tx_idx = 0;
1360 }
1361 /* The may have been a race between a pci originated read
1362 * and the descriptor update from the cpu. Just in case,
1363 * kick the transmitter if the hardware thinks it is on a
1364 * different descriptor than we are.
1365 */
1366 if (dev->tx_idx != dev->tx_free_idx)
1367 kick_tx(dev);
1368 }
1369
1370 /* Defer tx ring processing until more than a minimum amount of
1371 * work has accumulated
1372 */
1373 if ((ISR_TXDESC | ISR_TXIDLE | ISR_TXOK | ISR_TXERR) & isr) {
1374 spin_lock_irqsave(&dev->tx_lock, flags);
1375 do_tx_done(ndev);
1376 spin_unlock_irqrestore(&dev->tx_lock, flags);
1377
1378 /* Disable TxOk if there are no outstanding tx packets.
1379 */
1380 if ((dev->tx_done_idx == dev->tx_free_idx) &&
1381 (dev->IMR_cache & ISR_TXOK)) {
1382 spin_lock_irqsave(&dev->misc_lock, flags);
1383 dev->IMR_cache &= ~ISR_TXOK;
1384 writel(dev->IMR_cache, dev->base + IMR);
1385 spin_unlock_irqrestore(&dev->misc_lock, flags);
1386 }
1387 }
1388
1389 /* The TxIdle interrupt can come in before the transmit has
1390 * completed. Normally we reap packets off of the combination
1391 * of TxDesc and TxIdle and leave TxOk disabled (since it
1392 * occurs on every packet), but when no further irqs of this
1393 * nature are expected, we must enable TxOk.
1394 */
1395 if ((ISR_TXIDLE & isr) && (dev->tx_done_idx != dev->tx_free_idx)) {
1396 spin_lock_irqsave(&dev->misc_lock, flags);
1397 dev->IMR_cache |= ISR_TXOK;
1398 writel(dev->IMR_cache, dev->base + IMR);
1399 spin_unlock_irqrestore(&dev->misc_lock, flags);
1400 }
1401
1402 /* MIB interrupt: one of the statistics counters is about to overflow */
1403 if (unlikely(ISR_MIB & isr))
1404 ns83820_mib_isr(dev);
1405
1406 /* PHY: Link up/down/negotiation state change */
1407 if (unlikely(ISR_PHY & isr))
1408 phy_intr(ndev);
1409
1410 #if 0 /* Still working on the interrupt mitigation strategy */
1411 if (dev->ihr)
1412 writel(dev->ihr, dev->base + IHR);
1413 #endif
1414 }
1415
1416 static void ns83820_do_reset(struct ns83820 *dev, u32 which)
1417 {
1418 Dprintk("resetting chip...\n");
1419 writel(which, dev->base + CR);
1420 do {
1421 schedule();
1422 } while (readl(dev->base + CR) & which);
1423 Dprintk("okay!\n");
1424 }
1425
1426 static int ns83820_stop(struct net_device *ndev)
1427 {
1428 struct ns83820 *dev = PRIV(ndev);
1429
1430 /* FIXME: protect against interrupt handler? */
1431 del_timer_sync(&dev->tx_watchdog);
1432
1433 /* disable interrupts */
1434 writel(0, dev->base + IMR);
1435 writel(0, dev->base + IER);
1436 readl(dev->base + IER);
1437
1438 dev->rx_info.up = 0;
1439 synchronize_irq(dev->pci_dev->irq);
1440
1441 ns83820_do_reset(dev, CR_RST);
1442
1443 synchronize_irq(dev->pci_dev->irq);
1444
1445 spin_lock_irq(&dev->misc_lock);
1446 dev->IMR_cache &= ~(ISR_TXURN | ISR_TXIDLE | ISR_TXERR | ISR_TXDESC | ISR_TXOK);
1447 spin_unlock_irq(&dev->misc_lock);
1448
1449 ns83820_cleanup_rx(dev);
1450 ns83820_cleanup_tx(dev);
1451
1452 return 0;
1453 }
1454
1455 static void ns83820_tx_timeout(struct net_device *ndev)
1456 {
1457 struct ns83820 *dev = PRIV(ndev);
1458 u32 tx_done_idx;
1459 __le32 *desc;
1460 unsigned long flags;
1461
1462 spin_lock_irqsave(&dev->tx_lock, flags);
1463
1464 tx_done_idx = dev->tx_done_idx;
1465 desc = dev->tx_descs + (tx_done_idx * DESC_SIZE);
1466
1467 printk(KERN_INFO "%s: tx_timeout: tx_done_idx=%d free_idx=%d cmdsts=%08x\n",
1468 ndev->name,
1469 tx_done_idx, dev->tx_free_idx, le32_to_cpu(desc[DESC_CMDSTS]));
1470
1471 #if defined(DEBUG)
1472 {
1473 u32 isr;
1474 isr = readl(dev->base + ISR);
1475 printk("irq: %08x imr: %08x\n", isr, dev->IMR_cache);
1476 ns83820_do_isr(ndev, isr);
1477 }
1478 #endif
1479
1480 do_tx_done(ndev);
1481
1482 tx_done_idx = dev->tx_done_idx;
1483 desc = dev->tx_descs + (tx_done_idx * DESC_SIZE);
1484
1485 printk(KERN_INFO "%s: after: tx_done_idx=%d free_idx=%d cmdsts=%08x\n",
1486 ndev->name,
1487 tx_done_idx, dev->tx_free_idx, le32_to_cpu(desc[DESC_CMDSTS]));
1488
1489 spin_unlock_irqrestore(&dev->tx_lock, flags);
1490 }
1491
1492 static void ns83820_tx_watch(unsigned long data)
1493 {
1494 struct net_device *ndev = (void *)data;
1495 struct ns83820 *dev = PRIV(ndev);
1496
1497 #if defined(DEBUG)
1498 printk("ns83820_tx_watch: %u %u %d\n",
1499 dev->tx_done_idx, dev->tx_free_idx, atomic_read(&dev->nr_tx_skbs)
1500 );
1501 #endif
1502
1503 if (time_after(jiffies, ndev->trans_start + 1*HZ) &&
1504 dev->tx_done_idx != dev->tx_free_idx) {
1505 printk(KERN_DEBUG "%s: ns83820_tx_watch: %u %u %d\n",
1506 ndev->name,
1507 dev->tx_done_idx, dev->tx_free_idx,
1508 atomic_read(&dev->nr_tx_skbs));
1509 ns83820_tx_timeout(ndev);
1510 }
1511
1512 mod_timer(&dev->tx_watchdog, jiffies + 2*HZ);
1513 }
1514
1515 static int ns83820_open(struct net_device *ndev)
1516 {
1517 struct ns83820 *dev = PRIV(ndev);
1518 unsigned i;
1519 u32 desc;
1520 int ret;
1521
1522 dprintk("ns83820_open\n");
1523
1524 writel(0, dev->base + PQCR);
1525
1526 ret = ns83820_setup_rx(ndev);
1527 if (ret)
1528 goto failed;
1529
1530 memset(dev->tx_descs, 0, 4 * NR_TX_DESC * DESC_SIZE);
1531 for (i=0; i<NR_TX_DESC; i++) {
1532 dev->tx_descs[(i * DESC_SIZE) + DESC_LINK]
1533 = cpu_to_le32(
1534 dev->tx_phy_descs
1535 + ((i+1) % NR_TX_DESC) * DESC_SIZE * 4);
1536 }
1537
1538 dev->tx_idx = 0;
1539 dev->tx_done_idx = 0;
1540 desc = dev->tx_phy_descs;
1541 writel(0, dev->base + TXDP_HI);
1542 writel(desc, dev->base + TXDP);
1543
1544 init_timer(&dev->tx_watchdog);
1545 dev->tx_watchdog.data = (unsigned long)ndev;
1546 dev->tx_watchdog.function = ns83820_tx_watch;
1547 mod_timer(&dev->tx_watchdog, jiffies + 2*HZ);
1548
1549 netif_start_queue(ndev); /* FIXME: wait for phy to come up */
1550
1551 return 0;
1552
1553 failed:
1554 ns83820_stop(ndev);
1555 return ret;
1556 }
1557
1558 static void ns83820_getmac(struct ns83820 *dev, u8 *mac)
1559 {
1560 unsigned i;
1561 for (i=0; i<3; i++) {
1562 u32 data;
1563
1564 /* Read from the perfect match memory: this is loaded by
1565 * the chip from the EEPROM via the EELOAD self test.
1566 */
1567 writel(i*2, dev->base + RFCR);
1568 data = readl(dev->base + RFDR);
1569
1570 *mac++ = data;
1571 *mac++ = data >> 8;
1572 }
1573 }
1574
1575 static int ns83820_change_mtu(struct net_device *ndev, int new_mtu)
1576 {
1577 if (new_mtu > RX_BUF_SIZE)
1578 return -EINVAL;
1579 ndev->mtu = new_mtu;
1580 return 0;
1581 }
1582
1583 static void ns83820_set_multicast(struct net_device *ndev)
1584 {
1585 struct ns83820 *dev = PRIV(ndev);
1586 u8 __iomem *rfcr = dev->base + RFCR;
1587 u32 and_mask = 0xffffffff;
1588 u32 or_mask = 0;
1589 u32 val;
1590
1591 if (ndev->flags & IFF_PROMISC)
1592 or_mask |= RFCR_AAU | RFCR_AAM;
1593 else
1594 and_mask &= ~(RFCR_AAU | RFCR_AAM);
1595
1596 if (ndev->flags & IFF_ALLMULTI)
1597 or_mask |= RFCR_AAM;
1598 else
1599 and_mask &= ~RFCR_AAM;
1600
1601 spin_lock_irq(&dev->misc_lock);
1602 val = (readl(rfcr) & and_mask) | or_mask;
1603 /* Ramit : RFCR Write Fix doc says RFEN must be 0 modify other bits */
1604 writel(val & ~RFCR_RFEN, rfcr);
1605 writel(val, rfcr);
1606 spin_unlock_irq(&dev->misc_lock);
1607 }
1608
1609 static void ns83820_run_bist(struct net_device *ndev, const char *name, u32 enable, u32 done, u32 fail)
1610 {
1611 struct ns83820 *dev = PRIV(ndev);
1612 int timed_out = 0;
1613 unsigned long start;
1614 u32 status;
1615 int loops = 0;
1616
1617 dprintk("%s: start %s\n", ndev->name, name);
1618
1619 start = jiffies;
1620
1621 writel(enable, dev->base + PTSCR);
1622 for (;;) {
1623 loops++;
1624 status = readl(dev->base + PTSCR);
1625 if (!(status & enable))
1626 break;
1627 if (status & done)
1628 break;
1629 if (status & fail)
1630 break;
1631 if (time_after_eq(jiffies, start + HZ)) {
1632 timed_out = 1;
1633 break;
1634 }
1635 schedule_timeout_uninterruptible(1);
1636 }
1637
1638 if (status & fail)
1639 printk(KERN_INFO "%s: %s failed! (0x%08x & 0x%08x)\n",
1640 ndev->name, name, status, fail);
1641 else if (timed_out)
1642 printk(KERN_INFO "%s: run_bist %s timed out! (%08x)\n",
1643 ndev->name, name, status);
1644
1645 dprintk("%s: done %s in %d loops\n", ndev->name, name, loops);
1646 }
1647
1648 #ifdef PHY_CODE_IS_FINISHED
1649 static void ns83820_mii_write_bit(struct ns83820 *dev, int bit)
1650 {
1651 /* drive MDC low */
1652 dev->MEAR_cache &= ~MEAR_MDC;
1653 writel(dev->MEAR_cache, dev->base + MEAR);
1654 readl(dev->base + MEAR);
1655
1656 /* enable output, set bit */
1657 dev->MEAR_cache |= MEAR_MDDIR;
1658 if (bit)
1659 dev->MEAR_cache |= MEAR_MDIO;
1660 else
1661 dev->MEAR_cache &= ~MEAR_MDIO;
1662
1663 /* set the output bit */
1664 writel(dev->MEAR_cache, dev->base + MEAR);
1665 readl(dev->base + MEAR);
1666
1667 /* Wait. Max clock rate is 2.5MHz, this way we come in under 1MHz */
1668 udelay(1);
1669
1670 /* drive MDC high causing the data bit to be latched */
1671 dev->MEAR_cache |= MEAR_MDC;
1672 writel(dev->MEAR_cache, dev->base + MEAR);
1673 readl(dev->base + MEAR);
1674
1675 /* Wait again... */
1676 udelay(1);
1677 }
1678
1679 static int ns83820_mii_read_bit(struct ns83820 *dev)
1680 {
1681 int bit;
1682
1683 /* drive MDC low, disable output */
1684 dev->MEAR_cache &= ~MEAR_MDC;
1685 dev->MEAR_cache &= ~MEAR_MDDIR;
1686 writel(dev->MEAR_cache, dev->base + MEAR);
1687 readl(dev->base + MEAR);
1688
1689 /* Wait. Max clock rate is 2.5MHz, this way we come in under 1MHz */
1690 udelay(1);
1691
1692 /* drive MDC high causing the data bit to be latched */
1693 bit = (readl(dev->base + MEAR) & MEAR_MDIO) ? 1 : 0;
1694 dev->MEAR_cache |= MEAR_MDC;
1695 writel(dev->MEAR_cache, dev->base + MEAR);
1696
1697 /* Wait again... */
1698 udelay(1);
1699
1700 return bit;
1701 }
1702
1703 static unsigned ns83820_mii_read_reg(struct ns83820 *dev, unsigned phy, unsigned reg)
1704 {
1705 unsigned data = 0;
1706 int i;
1707
1708 /* read some garbage so that we eventually sync up */
1709 for (i=0; i<64; i++)
1710 ns83820_mii_read_bit(dev);
1711
1712 ns83820_mii_write_bit(dev, 0); /* start */
1713 ns83820_mii_write_bit(dev, 1);
1714 ns83820_mii_write_bit(dev, 1); /* opcode read */
1715 ns83820_mii_write_bit(dev, 0);
1716
1717 /* write out the phy address: 5 bits, msb first */
1718 for (i=0; i<5; i++)
1719 ns83820_mii_write_bit(dev, phy & (0x10 >> i));
1720
1721 /* write out the register address, 5 bits, msb first */
1722 for (i=0; i<5; i++)
1723 ns83820_mii_write_bit(dev, reg & (0x10 >> i));
1724
1725 ns83820_mii_read_bit(dev); /* turn around cycles */
1726 ns83820_mii_read_bit(dev);
1727
1728 /* read in the register data, 16 bits msb first */
1729 for (i=0; i<16; i++) {
1730 data <<= 1;
1731 data |= ns83820_mii_read_bit(dev);
1732 }
1733
1734 return data;
1735 }
1736
1737 static unsigned ns83820_mii_write_reg(struct ns83820 *dev, unsigned phy, unsigned reg, unsigned data)
1738 {
1739 int i;
1740
1741 /* read some garbage so that we eventually sync up */
1742 for (i=0; i<64; i++)
1743 ns83820_mii_read_bit(dev);
1744
1745 ns83820_mii_write_bit(dev, 0); /* start */
1746 ns83820_mii_write_bit(dev, 1);
1747 ns83820_mii_write_bit(dev, 0); /* opcode read */
1748 ns83820_mii_write_bit(dev, 1);
1749
1750 /* write out the phy address: 5 bits, msb first */
1751 for (i=0; i<5; i++)
1752 ns83820_mii_write_bit(dev, phy & (0x10 >> i));
1753
1754 /* write out the register address, 5 bits, msb first */
1755 for (i=0; i<5; i++)
1756 ns83820_mii_write_bit(dev, reg & (0x10 >> i));
1757
1758 ns83820_mii_read_bit(dev); /* turn around cycles */
1759 ns83820_mii_read_bit(dev);
1760
1761 /* read in the register data, 16 bits msb first */
1762 for (i=0; i<16; i++)
1763 ns83820_mii_write_bit(dev, (data >> (15 - i)) & 1);
1764
1765 return data;
1766 }
1767
1768 static void ns83820_probe_phy(struct net_device *ndev)
1769 {
1770 struct ns83820 *dev = PRIV(ndev);
1771 static int first;
1772 int i;
1773 #define MII_PHYIDR1 0x02
1774 #define MII_PHYIDR2 0x03
1775
1776 #if 0
1777 if (!first) {
1778 unsigned tmp;
1779 ns83820_mii_read_reg(dev, 1, 0x09);
1780 ns83820_mii_write_reg(dev, 1, 0x10, 0x0d3e);
1781
1782 tmp = ns83820_mii_read_reg(dev, 1, 0x00);
1783 ns83820_mii_write_reg(dev, 1, 0x00, tmp | 0x8000);
1784 udelay(1300);
1785 ns83820_mii_read_reg(dev, 1, 0x09);
1786 }
1787 #endif
1788 first = 1;
1789
1790 for (i=1; i<2; i++) {
1791 int j;
1792 unsigned a, b;
1793 a = ns83820_mii_read_reg(dev, i, MII_PHYIDR1);
1794 b = ns83820_mii_read_reg(dev, i, MII_PHYIDR2);
1795
1796 //printk("%s: phy %d: 0x%04x 0x%04x\n",
1797 // ndev->name, i, a, b);
1798
1799 for (j=0; j<0x16; j+=4) {
1800 dprintk("%s: [0x%02x] %04x %04x %04x %04x\n",
1801 ndev->name, j,
1802 ns83820_mii_read_reg(dev, i, 0 + j),
1803 ns83820_mii_read_reg(dev, i, 1 + j),
1804 ns83820_mii_read_reg(dev, i, 2 + j),
1805 ns83820_mii_read_reg(dev, i, 3 + j)
1806 );
1807 }
1808 }
1809 {
1810 unsigned a, b;
1811 /* read firmware version: memory addr is 0x8402 and 0x8403 */
1812 ns83820_mii_write_reg(dev, 1, 0x16, 0x000d);
1813 ns83820_mii_write_reg(dev, 1, 0x1e, 0x810e);
1814 a = ns83820_mii_read_reg(dev, 1, 0x1d);
1815
1816 ns83820_mii_write_reg(dev, 1, 0x16, 0x000d);
1817 ns83820_mii_write_reg(dev, 1, 0x1e, 0x810e);
1818 b = ns83820_mii_read_reg(dev, 1, 0x1d);
1819 dprintk("version: 0x%04x 0x%04x\n", a, b);
1820 }
1821 }
1822 #endif
1823
1824 static int __devinit ns83820_init_one(struct pci_dev *pci_dev, const struct pci_device_id *id)
1825 {
1826 struct net_device *ndev;
1827 struct ns83820 *dev;
1828 long addr;
1829 int err;
1830 int using_dac = 0;
1831
1832 /* See if we can set the dma mask early on; failure is fatal. */
1833 if (sizeof(dma_addr_t) == 8 &&
1834 !pci_set_dma_mask(pci_dev, DMA_64BIT_MASK)) {
1835 using_dac = 1;
1836 } else if (!pci_set_dma_mask(pci_dev, DMA_32BIT_MASK)) {
1837 using_dac = 0;
1838 } else {
1839 dev_warn(&pci_dev->dev, "pci_set_dma_mask failed!\n");
1840 return -ENODEV;
1841 }
1842
1843 ndev = alloc_etherdev(sizeof(struct ns83820));
1844 dev = PRIV(ndev);
1845 dev->ndev = ndev;
1846 err = -ENOMEM;
1847 if (!dev)
1848 goto out;
1849
1850 spin_lock_init(&dev->rx_info.lock);
1851 spin_lock_init(&dev->tx_lock);
1852 spin_lock_init(&dev->misc_lock);
1853 dev->pci_dev = pci_dev;
1854
1855 SET_MODULE_OWNER(ndev);
1856 SET_NETDEV_DEV(ndev, &pci_dev->dev);
1857
1858 INIT_WORK(&dev->tq_refill, queue_refill);
1859 tasklet_init(&dev->rx_tasklet, rx_action, (unsigned long)ndev);
1860
1861 err = pci_enable_device(pci_dev);
1862 if (err) {
1863 dev_info(&pci_dev->dev, "pci_enable_dev failed: %d\n", err);
1864 goto out_free;
1865 }
1866
1867 pci_set_master(pci_dev);
1868 addr = pci_resource_start(pci_dev, 1);
1869 dev->base = ioremap_nocache(addr, PAGE_SIZE);
1870 dev->tx_descs = pci_alloc_consistent(pci_dev,
1871 4 * DESC_SIZE * NR_TX_DESC, &dev->tx_phy_descs);
1872 dev->rx_info.descs = pci_alloc_consistent(pci_dev,
1873 4 * DESC_SIZE * NR_RX_DESC, &dev->rx_info.phy_descs);
1874 err = -ENOMEM;
1875 if (!dev->base || !dev->tx_descs || !dev->rx_info.descs)
1876 goto out_disable;
1877
1878 dprintk("%p: %08lx %p: %08lx\n",
1879 dev->tx_descs, (long)dev->tx_phy_descs,
1880 dev->rx_info.descs, (long)dev->rx_info.phy_descs);
1881
1882 /* disable interrupts */
1883 writel(0, dev->base + IMR);
1884 writel(0, dev->base + IER);
1885 readl(dev->base + IER);
1886
1887 dev->IMR_cache = 0;
1888
1889 err = request_irq(pci_dev->irq, ns83820_irq, IRQF_SHARED,
1890 DRV_NAME, ndev);
1891 if (err) {
1892 dev_info(&pci_dev->dev, "unable to register irq %d, err %d\n",
1893 pci_dev->irq, err);
1894 goto out_disable;
1895 }
1896
1897 /*
1898 * FIXME: we are holding rtnl_lock() over obscenely long area only
1899 * because some of the setup code uses dev->name. It's Wrong(tm) -
1900 * we should be using driver-specific names for all that stuff.
1901 * For now that will do, but we really need to come back and kill
1902 * most of the dev_alloc_name() users later.
1903 */
1904 rtnl_lock();
1905 err = dev_alloc_name(ndev, ndev->name);
1906 if (err < 0) {
1907 dev_info(&pci_dev->dev, "unable to get netdev name: %d\n", err);
1908 goto out_free_irq;
1909 }
1910
1911 printk("%s: ns83820.c: 0x22c: %08x, subsystem: %04x:%04x\n",
1912 ndev->name, le32_to_cpu(readl(dev->base + 0x22c)),
1913 pci_dev->subsystem_vendor, pci_dev->subsystem_device);
1914
1915 ndev->open = ns83820_open;
1916 ndev->stop = ns83820_stop;
1917 ndev->hard_start_xmit = ns83820_hard_start_xmit;
1918 ndev->get_stats = ns83820_get_stats;
1919 ndev->change_mtu = ns83820_change_mtu;
1920 ndev->set_multicast_list = ns83820_set_multicast;
1921 SET_ETHTOOL_OPS(ndev, &ops);
1922 ndev->tx_timeout = ns83820_tx_timeout;
1923 ndev->watchdog_timeo = 5 * HZ;
1924 pci_set_drvdata(pci_dev, ndev);
1925
1926 ns83820_do_reset(dev, CR_RST);
1927
1928 /* Must reset the ram bist before running it */
1929 writel(PTSCR_RBIST_RST, dev->base + PTSCR);
1930 ns83820_run_bist(ndev, "sram bist", PTSCR_RBIST_EN,
1931 PTSCR_RBIST_DONE, PTSCR_RBIST_FAIL);
1932 ns83820_run_bist(ndev, "eeprom bist", PTSCR_EEBIST_EN, 0,
1933 PTSCR_EEBIST_FAIL);
1934 ns83820_run_bist(ndev, "eeprom load", PTSCR_EELOAD_EN, 0, 0);
1935
1936 /* I love config registers */
1937 dev->CFG_cache = readl(dev->base + CFG);
1938
1939 if ((dev->CFG_cache & CFG_PCI64_DET)) {
1940 printk(KERN_INFO "%s: detected 64 bit PCI data bus.\n",
1941 ndev->name);
1942 /*dev->CFG_cache |= CFG_DATA64_EN;*/
1943 if (!(dev->CFG_cache & CFG_DATA64_EN))
1944 printk(KERN_INFO "%s: EEPROM did not enable 64 bit bus. Disabled.\n",
1945 ndev->name);
1946 } else
1947 dev->CFG_cache &= ~(CFG_DATA64_EN);
1948
1949 dev->CFG_cache &= (CFG_TBI_EN | CFG_MRM_DIS | CFG_MWI_DIS |
1950 CFG_T64ADDR | CFG_DATA64_EN | CFG_EXT_125 |
1951 CFG_M64ADDR);
1952 dev->CFG_cache |= CFG_PINT_DUPSTS | CFG_PINT_LNKSTS | CFG_PINT_SPDSTS |
1953 CFG_EXTSTS_EN | CFG_EXD | CFG_PESEL;
1954 dev->CFG_cache |= CFG_REQALG;
1955 dev->CFG_cache |= CFG_POW;
1956 dev->CFG_cache |= CFG_TMRTEST;
1957
1958 /* When compiled with 64 bit addressing, we must always enable
1959 * the 64 bit descriptor format.
1960 */
1961 if (sizeof(dma_addr_t) == 8)
1962 dev->CFG_cache |= CFG_M64ADDR;
1963 if (using_dac)
1964 dev->CFG_cache |= CFG_T64ADDR;
1965
1966 /* Big endian mode does not seem to do what the docs suggest */
1967 dev->CFG_cache &= ~CFG_BEM;
1968
1969 /* setup optical transceiver if we have one */
1970 if (dev->CFG_cache & CFG_TBI_EN) {
1971 printk(KERN_INFO "%s: enabling optical transceiver\n",
1972 ndev->name);
1973 writel(readl(dev->base + GPIOR) | 0x3e8, dev->base + GPIOR);
1974
1975 /* setup auto negotiation feature advertisement */
1976 writel(readl(dev->base + TANAR)
1977 | TANAR_HALF_DUP | TANAR_FULL_DUP,
1978 dev->base + TANAR);
1979
1980 /* start auto negotiation */
1981 writel(TBICR_MR_AN_ENABLE | TBICR_MR_RESTART_AN,
1982 dev->base + TBICR);
1983 writel(TBICR_MR_AN_ENABLE, dev->base + TBICR);
1984 dev->linkstate = LINK_AUTONEGOTIATE;
1985
1986 dev->CFG_cache |= CFG_MODE_1000;
1987 }
1988
1989 writel(dev->CFG_cache, dev->base + CFG);
1990 dprintk("CFG: %08x\n", dev->CFG_cache);
1991
1992 if (reset_phy) {
1993 printk(KERN_INFO "%s: resetting phy\n", ndev->name);
1994 writel(dev->CFG_cache | CFG_PHY_RST, dev->base + CFG);
1995 msleep(10);
1996 writel(dev->CFG_cache, dev->base + CFG);
1997 }
1998
1999 #if 0 /* Huh? This sets the PCI latency register. Should be done via
2000 * the PCI layer. FIXME.
2001 */
2002 if (readl(dev->base + SRR))
2003 writel(readl(dev->base+0x20c) | 0xfe00, dev->base + 0x20c);
2004 #endif
2005
2006 /* Note! The DMA burst size interacts with packet
2007 * transmission, such that the largest packet that
2008 * can be transmitted is 8192 - FLTH - burst size.
2009 * If only the transmit fifo was larger...
2010 */
2011 /* Ramit : 1024 DMA is not a good idea, it ends up banging
2012 * some DELL and COMPAQ SMP systems */
2013 writel(TXCFG_CSI | TXCFG_HBI | TXCFG_ATP | TXCFG_MXDMA512
2014 | ((1600 / 32) * 0x100),
2015 dev->base + TXCFG);
2016
2017 /* Flush the interrupt holdoff timer */
2018 writel(0x000, dev->base + IHR);
2019 writel(0x100, dev->base + IHR);
2020 writel(0x000, dev->base + IHR);
2021
2022 /* Set Rx to full duplex, don't accept runt, errored, long or length
2023 * range errored packets. Use 512 byte DMA.
2024 */
2025 /* Ramit : 1024 DMA is not a good idea, it ends up banging
2026 * some DELL and COMPAQ SMP systems
2027 * Turn on ALP, only we are accpeting Jumbo Packets */
2028 writel(RXCFG_AEP | RXCFG_ARP | RXCFG_AIRL | RXCFG_RX_FD
2029 | RXCFG_STRIPCRC
2030 //| RXCFG_ALP
2031 | (RXCFG_MXDMA512) | 0, dev->base + RXCFG);
2032
2033 /* Disable priority queueing */
2034 writel(0, dev->base + PQCR);
2035
2036 /* Enable IP checksum validation and detetion of VLAN headers.
2037 * Note: do not set the reject options as at least the 0x102
2038 * revision of the chip does not properly accept IP fragments
2039 * at least for UDP.
2040 */
2041 /* Ramit : Be sure to turn on RXCFG_ARP if VLAN's are enabled, since
2042 * the MAC it calculates the packetsize AFTER stripping the VLAN
2043 * header, and if a VLAN Tagged packet of 64 bytes is received (like
2044 * a ping with a VLAN header) then the card, strips the 4 byte VLAN
2045 * tag and then checks the packet size, so if RXCFG_ARP is not enabled,
2046 * it discrards it!. These guys......
2047 * also turn on tag stripping if hardware acceleration is enabled
2048 */
2049 #ifdef NS83820_VLAN_ACCEL_SUPPORT
2050 #define VRCR_INIT_VALUE (VRCR_IPEN|VRCR_VTDEN|VRCR_VTREN)
2051 #else
2052 #define VRCR_INIT_VALUE (VRCR_IPEN|VRCR_VTDEN)
2053 #endif
2054 writel(VRCR_INIT_VALUE, dev->base + VRCR);
2055
2056 /* Enable per-packet TCP/UDP/IP checksumming
2057 * and per packet vlan tag insertion if
2058 * vlan hardware acceleration is enabled
2059 */
2060 #ifdef NS83820_VLAN_ACCEL_SUPPORT
2061 #define VTCR_INIT_VALUE (VTCR_PPCHK|VTCR_VPPTI)
2062 #else
2063 #define VTCR_INIT_VALUE VTCR_PPCHK
2064 #endif
2065 writel(VTCR_INIT_VALUE, dev->base + VTCR);
2066
2067 /* Ramit : Enable async and sync pause frames */
2068 /* writel(0, dev->base + PCR); */
2069 writel((PCR_PS_MCAST | PCR_PS_DA | PCR_PSEN | PCR_FFLO_4K |
2070 PCR_FFHI_8K | PCR_STLO_4 | PCR_STHI_8 | PCR_PAUSE_CNT),
2071 dev->base + PCR);
2072
2073 /* Disable Wake On Lan */
2074 writel(0, dev->base + WCSR);
2075
2076 ns83820_getmac(dev, ndev->dev_addr);
2077
2078 /* Yes, we support dumb IP checksum on transmit */
2079 ndev->features |= NETIF_F_SG;
2080 ndev->features |= NETIF_F_IP_CSUM;
2081
2082 #ifdef NS83820_VLAN_ACCEL_SUPPORT
2083 /* We also support hardware vlan acceleration */
2084 ndev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
2085 ndev->vlan_rx_register = ns83820_vlan_rx_register;
2086 ndev->vlan_rx_kill_vid = ns83820_vlan_rx_kill_vid;
2087 #endif
2088
2089 if (using_dac) {
2090 printk(KERN_INFO "%s: using 64 bit addressing.\n",
2091 ndev->name);
2092 ndev->features |= NETIF_F_HIGHDMA;
2093 }
2094
2095 printk(KERN_INFO "%s: ns83820 v" VERSION ": DP83820 v%u.%u: %02x:%02x:%02x:%02x:%02x:%02x io=0x%08lx irq=%d f=%s\n",
2096 ndev->name,
2097 (unsigned)readl(dev->base + SRR) >> 8,
2098 (unsigned)readl(dev->base + SRR) & 0xff,
2099 ndev->dev_addr[0], ndev->dev_addr[1],
2100 ndev->dev_addr[2], ndev->dev_addr[3],
2101 ndev->dev_addr[4], ndev->dev_addr[5],
2102 addr, pci_dev->irq,
2103 (ndev->features & NETIF_F_HIGHDMA) ? "h,sg" : "sg"
2104 );
2105
2106 #ifdef PHY_CODE_IS_FINISHED
2107 ns83820_probe_phy(ndev);
2108 #endif
2109
2110 err = register_netdevice(ndev);
2111 if (err) {
2112 printk(KERN_INFO "ns83820: unable to register netdev: %d\n", err);
2113 goto out_cleanup;
2114 }
2115 rtnl_unlock();
2116
2117 return 0;
2118
2119 out_cleanup:
2120 writel(0, dev->base + IMR); /* paranoia */
2121 writel(0, dev->base + IER);
2122 readl(dev->base + IER);
2123 out_free_irq:
2124 rtnl_unlock();
2125 free_irq(pci_dev->irq, ndev);
2126 out_disable:
2127 if (dev->base)
2128 iounmap(dev->base);
2129 pci_free_consistent(pci_dev, 4 * DESC_SIZE * NR_TX_DESC, dev->tx_descs, dev->tx_phy_descs);
2130 pci_free_consistent(pci_dev, 4 * DESC_SIZE * NR_RX_DESC, dev->rx_info.descs, dev->rx_info.phy_descs);
2131 pci_disable_device(pci_dev);
2132 out_free:
2133 free_netdev(ndev);
2134 pci_set_drvdata(pci_dev, NULL);
2135 out:
2136 return err;
2137 }
2138
2139 static void __devexit ns83820_remove_one(struct pci_dev *pci_dev)
2140 {
2141 struct net_device *ndev = pci_get_drvdata(pci_dev);
2142 struct ns83820 *dev = PRIV(ndev); /* ok even if NULL */
2143
2144 if (!ndev) /* paranoia */
2145 return;
2146
2147 writel(0, dev->base + IMR); /* paranoia */
2148 writel(0, dev->base + IER);
2149 readl(dev->base + IER);
2150
2151 unregister_netdev(ndev);
2152 free_irq(dev->pci_dev->irq, ndev);
2153 iounmap(dev->base);
2154 pci_free_consistent(dev->pci_dev, 4 * DESC_SIZE * NR_TX_DESC,
2155 dev->tx_descs, dev->tx_phy_descs);
2156 pci_free_consistent(dev->pci_dev, 4 * DESC_SIZE * NR_RX_DESC,
2157 dev->rx_info.descs, dev->rx_info.phy_descs);
2158 pci_disable_device(dev->pci_dev);
2159 free_netdev(ndev);
2160 pci_set_drvdata(pci_dev, NULL);
2161 }
2162
2163 static struct pci_device_id ns83820_pci_tbl[] = {
2164 { 0x100b, 0x0022, PCI_ANY_ID, PCI_ANY_ID, 0, .driver_data = 0, },
2165 { 0, },
2166 };
2167
2168 static struct pci_driver driver = {
2169 .name = "ns83820",
2170 .id_table = ns83820_pci_tbl,
2171 .probe = ns83820_init_one,
2172 .remove = __devexit_p(ns83820_remove_one),
2173 #if 0 /* FIXME: implement */
2174 .suspend = ,
2175 .resume = ,
2176 #endif
2177 };
2178
2179
2180 static int __init ns83820_init(void)
2181 {
2182 printk(KERN_INFO "ns83820.c: National Semiconductor DP83820 10/100/1000 driver.\n");
2183 return pci_register_driver(&driver);
2184 }
2185
2186 static void __exit ns83820_exit(void)
2187 {
2188 pci_unregister_driver(&driver);
2189 }
2190
2191 MODULE_AUTHOR("Benjamin LaHaise <bcrl@kvack.org>");
2192 MODULE_DESCRIPTION("National Semiconductor DP83820 10/100/1000 driver");
2193 MODULE_LICENSE("GPL");
2194
2195 MODULE_DEVICE_TABLE(pci, ns83820_pci_tbl);
2196
2197 module_param(lnksts, int, 0);
2198 MODULE_PARM_DESC(lnksts, "Polarity of LNKSTS bit");
2199
2200 module_param(ihr, int, 0);
2201 MODULE_PARM_DESC(ihr, "Time in 100 us increments to delay interrupts (range 0-127)");
2202
2203 module_param(reset_phy, int, 0);
2204 MODULE_PARM_DESC(reset_phy, "Set to 1 to reset the PHY on startup");
2205
2206 module_init(ns83820_init);
2207 module_exit(ns83820_exit);
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