2 * linux/arch/m32r/mm/fault.c
4 * Copyright (c) 2001, 2002 Hitoshi Yamamoto, and H. Kondo
5 * Copyright (c) 2004 Naoto Sugai, NIIBE Yutaka
7 * Some code taken from i386 version.
8 * Copyright (C) 1995 Linus Torvalds
11 #include <linux/signal.h>
12 #include <linux/sched.h>
13 #include <linux/kernel.h>
14 #include <linux/errno.h>
15 #include <linux/string.h>
16 #include <linux/types.h>
17 #include <linux/ptrace.h>
18 #include <linux/mman.h>
20 #include <linux/smp.h>
21 #include <linux/smp_lock.h>
22 #include <linux/interrupt.h>
23 #include <linux/init.h>
24 #include <linux/tty.h>
25 #include <linux/vt_kern.h> /* For unblank_screen() */
26 #include <linux/highmem.h>
27 #include <linux/module.h>
30 #include <asm/system.h>
31 #include <asm/uaccess.h>
32 #include <asm/hardirq.h>
33 #include <asm/mmu_context.h>
34 #include <asm/tlbflush.h>
36 extern void die(const char *, struct pt_regs
*, long);
39 asmlinkage
unsigned int tlb_entry_i_dat
;
40 asmlinkage
unsigned int tlb_entry_d_dat
;
41 #define tlb_entry_i tlb_entry_i_dat
42 #define tlb_entry_d tlb_entry_d_dat
44 unsigned int tlb_entry_i_dat
[NR_CPUS
];
45 unsigned int tlb_entry_d_dat
[NR_CPUS
];
46 #define tlb_entry_i tlb_entry_i_dat[smp_processor_id()]
47 #define tlb_entry_d tlb_entry_d_dat[smp_processor_id()]
50 extern void init_tlb(void);
53 * Unlock any spinlocks which will prevent us from getting the
56 void bust_spinlocks(int yes
)
58 int loglevel_save
= console_loglevel
;
69 * OK, the message is on the console. Now we call printk()
70 * without oops_in_progress set so that printk will give klogd
71 * a poke. Hold onto your hats...
73 console_loglevel
= 15; /* NMI oopser may have shut the console up */
75 console_loglevel
= loglevel_save
;
78 /*======================================================================*
80 *======================================================================*
81 * This routine handles page faults. It determines the address,
82 * and the problem, and then passes it off to one of the appropriate
87 * error_code : See below
88 * address : M32R MMU MDEVA reg. (Operand ACE)
89 * : M32R BPC reg. (Instruction ACE)
92 * bit 0 == 0 means no page found, 1 means protection fault
93 * bit 1 == 0 means read, 1 means write
94 * bit 2 == 0 means kernel, 1 means user-mode
95 * bit 3 == 0 means data, 1 means instruction
96 *======================================================================*/
97 #define ACE_PROTECTION 1
99 #define ACE_USERMODE 4
100 #define ACE_INSTRUCTION 8
102 asmlinkage
void do_page_fault(struct pt_regs
*regs
, unsigned long error_code
,
103 unsigned long address
)
105 struct task_struct
*tsk
;
106 struct mm_struct
*mm
;
107 struct vm_area_struct
* vma
;
108 unsigned long page
, addr
;
113 * If BPSW IE bit enable --> set PSW IE bit
115 if (regs
->psw
& M32R_PSW_BIE
)
120 info
.si_code
= SEGV_MAPERR
;
123 * We fault-in kernel-space virtual memory on-demand. The
124 * 'reference' page table is init_mm.pgd.
126 * NOTE! We MUST NOT take any locks for this case. We may
127 * be in an interrupt or a critical region, and should
128 * only copy the information from the master page table,
131 * This verifies that the fault happens in kernel space
132 * (error_code & ACE_USERMODE) == 0, and that the fault was not a
133 * protection error (error_code & ACE_PROTECTION) == 0.
135 if (address
>= TASK_SIZE
&& !(error_code
& ACE_USERMODE
))
141 * If we're in an interrupt or have no user context or are running in an
142 * atomic region then we must not take the fault..
144 if (in_atomic() || !mm
)
145 goto bad_area_nosemaphore
;
147 /* When running in the kernel we expect faults to occur only to
148 * addresses in user space. All other faults represent errors in the
149 * kernel and should generate an OOPS. Unfortunatly, in the case of an
150 * erroneous fault occurring in a code path which already holds mmap_sem
151 * we will deadlock attempting to validate the fault against the
152 * address space. Luckily the kernel only validly references user
153 * space from well defined areas of code, which are listed in the
156 * As the vast majority of faults will be valid we will only perform
157 * the source reference check when there is a possibilty of a deadlock.
158 * Attempt to lock the address space, if we cannot we then validate the
159 * source. If this is invalid we can skip the address space check,
160 * thus avoiding the deadlock.
162 if (!down_read_trylock(&mm
->mmap_sem
)) {
163 if ((error_code
& ACE_USERMODE
) == 0 &&
164 !search_exception_tables(regs
->psw
))
165 goto bad_area_nosemaphore
;
166 down_read(&mm
->mmap_sem
);
169 vma
= find_vma(mm
, address
);
172 if (vma
->vm_start
<= address
)
174 if (!(vma
->vm_flags
& VM_GROWSDOWN
))
177 if (error_code
& ACE_USERMODE
) {
179 * accessing the stack below "spu" is always a bug.
180 * The "+ 4" is there due to the push instruction
181 * doing pre-decrement on the stack and that
182 * doesn't show up until later..
184 if (address
+ 4 < regs
->spu
)
188 if (expand_stack(vma
, address
))
191 * Ok, we have a good vm_area for this memory access, so
195 info
.si_code
= SEGV_ACCERR
;
197 switch (error_code
& (ACE_WRITE
|ACE_PROTECTION
)) {
198 default: /* 3: write, present */
200 case ACE_WRITE
: /* write, not present */
201 if (!(vma
->vm_flags
& VM_WRITE
))
205 case ACE_PROTECTION
: /* read, present */
206 case 0: /* read, not present */
207 if (!(vma
->vm_flags
& (VM_READ
| VM_EXEC
)))
212 * For instruction access exception, check if the area is executable
214 if ((error_code
& ACE_INSTRUCTION
) && !(vma
->vm_flags
& VM_EXEC
))
219 * If for any reason at all we couldn't handle the fault,
220 * make sure we exit gracefully rather than endlessly redo
223 addr
= (address
& PAGE_MASK
);
224 set_thread_fault_code(error_code
);
225 switch (handle_mm_fault(mm
, vma
, addr
, write
)) {
232 case VM_FAULT_SIGBUS
:
239 set_thread_fault_code(0);
240 up_read(&mm
->mmap_sem
);
244 * Something tried to access memory that isn't in our memory map..
245 * Fix it, but check if it's kernel or user first..
248 up_read(&mm
->mmap_sem
);
250 bad_area_nosemaphore
:
251 /* User mode accesses just cause a SIGSEGV */
252 if (error_code
& ACE_USERMODE
) {
253 tsk
->thread
.address
= address
;
254 tsk
->thread
.error_code
= error_code
| (address
>= TASK_SIZE
);
255 tsk
->thread
.trap_no
= 14;
256 info
.si_signo
= SIGSEGV
;
258 /* info.si_code has been set above */
259 info
.si_addr
= (void __user
*)address
;
260 force_sig_info(SIGSEGV
, &info
, tsk
);
265 /* Are we prepared to handle this kernel fault? */
266 if (fixup_exception(regs
))
270 * Oops. The kernel tried to access some bad page. We'll have to
271 * terminate things with extreme prejudice.
276 if (address
< PAGE_SIZE
)
277 printk(KERN_ALERT
"Unable to handle kernel NULL pointer dereference");
279 printk(KERN_ALERT
"Unable to handle kernel paging request");
280 printk(" at virtual address %08lx\n",address
);
281 printk(KERN_ALERT
" printing bpc:\n");
282 printk("%08lx\n", regs
->bpc
);
283 page
= *(unsigned long *)MPTB
;
284 page
= ((unsigned long *) page
)[address
>> PGDIR_SHIFT
];
285 printk(KERN_ALERT
"*pde = %08lx\n", page
);
286 if (page
& _PAGE_PRESENT
) {
288 address
&= 0x003ff000;
289 page
= ((unsigned long *) __va(page
))[address
>> PAGE_SHIFT
];
290 printk(KERN_ALERT
"*pte = %08lx\n", page
);
292 die("Oops", regs
, error_code
);
297 * We ran out of memory, or some other thing happened to us that made
298 * us unable to handle the page fault gracefully.
301 up_read(&mm
->mmap_sem
);
304 down_read(&mm
->mmap_sem
);
307 printk("VM: killing process %s\n", tsk
->comm
);
308 if (error_code
& ACE_USERMODE
)
313 up_read(&mm
->mmap_sem
);
315 /* Kernel mode? Handle exception or die */
316 if (!(error_code
& ACE_USERMODE
))
319 tsk
->thread
.address
= address
;
320 tsk
->thread
.error_code
= error_code
;
321 tsk
->thread
.trap_no
= 14;
322 info
.si_signo
= SIGBUS
;
324 info
.si_code
= BUS_ADRERR
;
325 info
.si_addr
= (void __user
*)address
;
326 force_sig_info(SIGBUS
, &info
, tsk
);
332 * Synchronize this task's top level page-table
333 * with the 'reference' page table.
335 * Do _not_ use "tsk" here. We might be inside
336 * an interrupt in the middle of a task switch..
338 int offset
= pgd_index(address
);
343 pgd
= (pgd_t
*)*(unsigned long *)MPTB
;
344 pgd
= offset
+ (pgd_t
*)pgd
;
345 pgd_k
= init_mm
.pgd
+ offset
;
347 if (!pgd_present(*pgd_k
))
351 * set_pgd(pgd, *pgd_k); here would be useless on PAE
352 * and redundant with the set_pmd() on non-PAE.
355 pmd
= pmd_offset(pgd
, address
);
356 pmd_k
= pmd_offset(pgd_k
, address
);
357 if (!pmd_present(*pmd_k
))
359 set_pmd(pmd
, *pmd_k
);
361 pte_k
= pte_offset_kernel(pmd_k
, address
);
362 if (!pte_present(*pte_k
))
365 addr
= (address
& PAGE_MASK
) | (error_code
& ACE_INSTRUCTION
);
366 update_mmu_cache(NULL
, addr
, *pte_k
);
371 /*======================================================================*
373 *======================================================================*/
374 #define TLB_MASK (NR_TLB_ENTRIES - 1)
375 #define ITLB_END (unsigned long *)(ITLB_BASE + (NR_TLB_ENTRIES * 8))
376 #define DTLB_END (unsigned long *)(DTLB_BASE + (NR_TLB_ENTRIES * 8))
377 void update_mmu_cache(struct vm_area_struct
*vma
, unsigned long vaddr
,
380 unsigned long *entry1
, *entry2
;
381 unsigned long pte_data
, flags
;
382 unsigned int *entry_dat
;
383 int inst
= get_thread_fault_code() & ACE_INSTRUCTION
;
386 /* Ptrace may call this routine. */
387 if (vma
&& current
->active_mm
!= vma
->vm_mm
)
390 local_irq_save(flags
);
392 vaddr
= (vaddr
& PAGE_MASK
) | get_asid();
394 #ifdef CONFIG_CHIP_OPSP
395 entry1
= (unsigned long *)ITLB_BASE
;
396 for(i
= 0 ; i
< NR_TLB_ENTRIES
; i
++) {
397 if(*entry1
++ == vaddr
) {
398 pte_data
= pte_val(pte
);
399 set_tlb_data(entry1
, pte_data
);
404 entry2
= (unsigned long *)DTLB_BASE
;
405 for(i
= 0 ; i
< NR_TLB_ENTRIES
; i
++) {
406 if(*entry2
++ == vaddr
) {
407 pte_data
= pte_val(pte
);
408 set_tlb_data(entry2
, pte_data
);
413 local_irq_restore(flags
);
416 pte_data
= pte_val(pte
);
420 * entry1: ITLB entry address
421 * entry2: DTLB entry address
423 __asm__
__volatile__ (
424 "seth %0, #high(%4) \n\t"
425 "st %2, @(%5, %0) \n\t"
427 "st %1, @(%6, %0) \n\t"
428 "add3 r4, %0, %7 \n\t"
431 "ld %1, @(%6, %0) \n\t"
437 : "=&r" (entry1
), "=&r" (entry2
)
438 : "r" (vaddr
), "r" (pte_data
), "i" (MMU_REG_BASE
),
439 "i" (MSVA_offset
), "i" (MTOP_offset
), "i" (MIDXI_offset
)
443 if ((!inst
&& entry2
>= DTLB_END
) || (inst
&& entry1
>= ITLB_END
))
447 local_irq_restore(flags
);
451 /* Valid entry not found */
454 * Update ITLB or DTLB entry
455 * entry1: TLB entry address
456 * entry2: TLB base address
459 entry2
= (unsigned long *)DTLB_BASE
;
460 entry_dat
= &tlb_entry_d
;
462 entry2
= (unsigned long *)ITLB_BASE
;
463 entry_dat
= &tlb_entry_i
;
465 entry1
= entry2
+ (((*entry_dat
- 1) & TLB_MASK
) << 1);
467 for (i
= 0 ; i
< NR_TLB_ENTRIES
; i
++) {
468 if (!(entry1
[1] & 2)) /* Valid bit check */
471 if (entry1
!= entry2
)
474 entry1
+= TLB_MASK
<< 1;
477 if (i
>= NR_TLB_ENTRIES
) { /* Empty entry not found */
478 entry1
= entry2
+ (*entry_dat
<< 1);
479 *entry_dat
= (*entry_dat
+ 1) & TLB_MASK
;
481 *entry1
++ = vaddr
; /* Set TLB tag */
482 set_tlb_data(entry1
, pte_data
);
488 /*======================================================================*
489 * flush_tlb_page() : flushes one page
490 *======================================================================*/
491 void local_flush_tlb_page(struct vm_area_struct
*vma
, unsigned long page
)
493 if (vma
->vm_mm
&& mm_context(vma
->vm_mm
) != NO_CONTEXT
) {
496 local_irq_save(flags
);
498 page
|= (mm_context(vma
->vm_mm
) & MMU_CONTEXT_ASID_MASK
);
499 __flush_tlb_page(page
);
500 local_irq_restore(flags
);
504 /*======================================================================*
505 * flush_tlb_range() : flushes a range of pages
506 *======================================================================*/
507 void local_flush_tlb_range(struct vm_area_struct
*vma
, unsigned long start
,
510 struct mm_struct
*mm
;
513 if (mm_context(mm
) != NO_CONTEXT
) {
517 local_irq_save(flags
);
518 size
= (end
- start
+ (PAGE_SIZE
- 1)) >> PAGE_SHIFT
;
519 if (size
> (NR_TLB_ENTRIES
/ 4)) { /* Too many TLB to flush */
520 mm_context(mm
) = NO_CONTEXT
;
521 if (mm
== current
->mm
)
522 activate_context(mm
);
526 asid
= mm_context(mm
) & MMU_CONTEXT_ASID_MASK
;
528 end
+= (PAGE_SIZE
- 1);
533 while (start
< end
) {
534 __flush_tlb_page(start
);
538 local_irq_restore(flags
);
542 /*======================================================================*
543 * flush_tlb_mm() : flushes the specified mm context TLB's
544 *======================================================================*/
545 void local_flush_tlb_mm(struct mm_struct
*mm
)
547 /* Invalidate all TLB of this process. */
548 /* Instead of invalidating each TLB, we get new MMU context. */
549 if (mm_context(mm
) != NO_CONTEXT
) {
552 local_irq_save(flags
);
553 mm_context(mm
) = NO_CONTEXT
;
554 if (mm
== current
->mm
)
555 activate_context(mm
);
556 local_irq_restore(flags
);
560 /*======================================================================*
561 * flush_tlb_all() : flushes all processes TLBs
562 *======================================================================*/
563 void local_flush_tlb_all(void)
567 local_irq_save(flags
);
569 local_irq_restore(flags
);
572 /*======================================================================*
574 *======================================================================*/
575 void __init
init_mmu(void)
579 mmu_context_cache
= MMU_CONTEXT_FIRST_VERSION
;
580 set_asid(mmu_context_cache
& MMU_CONTEXT_ASID_MASK
);
581 *(volatile unsigned long *)MPTB
= (unsigned long)swapper_pg_dir
;