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update checkpatch.pl to version 0.05
[pv_ops_mirror.git] / drivers / net / sky2.c
blobfe01b961b597263dc20aad6b331b384c3830d549
1 /*
2 * New driver for Marvell Yukon 2 chipset.
3 * Based on earlier sk98lin, and skge driver.
4 *
5 * This driver intentionally does not support all the features
6 * of the original driver such as link fail-over and link management because
7 * those should be done at higher levels.
8 *
9 * Copyright (C) 2005 Stephen Hemminger <shemminger@osdl.org>
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
23 */
24
25 #include <linux/crc32.h>
26 #include <linux/kernel.h>
27 #include <linux/version.h>
28 #include <linux/module.h>
29 #include <linux/netdevice.h>
30 #include <linux/dma-mapping.h>
31 #include <linux/etherdevice.h>
32 #include <linux/ethtool.h>
33 #include <linux/pci.h>
34 #include <linux/ip.h>
35 #include <net/ip.h>
36 #include <linux/tcp.h>
37 #include <linux/in.h>
38 #include <linux/delay.h>
39 #include <linux/workqueue.h>
40 #include <linux/if_vlan.h>
41 #include <linux/prefetch.h>
42 #include <linux/mii.h>
43
44 #include <asm/irq.h>
45
46 #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
47 #define SKY2_VLAN_TAG_USED 1
48 #endif
49
50 #include "sky2.h"
51
52 #define DRV_NAME "sky2"
53 #define DRV_VERSION "1.14"
54 #define PFX DRV_NAME " "
55
56 /*
57 * The Yukon II chipset takes 64 bit command blocks (called list elements)
58 * that are organized into three (receive, transmit, status) different rings
59 * similar to Tigon3.
60 */
61
62 #define RX_LE_SIZE 1024
63 #define RX_LE_BYTES (RX_LE_SIZE*sizeof(struct sky2_rx_le))
64 #define RX_MAX_PENDING (RX_LE_SIZE/6 - 2)
65 #define RX_DEF_PENDING RX_MAX_PENDING
66 #define RX_SKB_ALIGN 8
67 #define RX_BUF_WRITE 16
68
69 #define TX_RING_SIZE 512
70 #define TX_DEF_PENDING (TX_RING_SIZE - 1)
71 #define TX_MIN_PENDING 64
72 #define MAX_SKB_TX_LE (4 + (sizeof(dma_addr_t)/sizeof(u32))*MAX_SKB_FRAGS)
73
74 #define STATUS_RING_SIZE 2048 /* 2 ports * (TX + 2*RX) */
75 #define STATUS_LE_BYTES (STATUS_RING_SIZE*sizeof(struct sky2_status_le))
76 #define TX_WATCHDOG (5 * HZ)
77 #define NAPI_WEIGHT 64
78 #define PHY_RETRIES 1000
79
80 #define RING_NEXT(x,s) (((x)+1) & ((s)-1))
81
82 static const u32 default_msg =
83 NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK
84 | NETIF_MSG_TIMER | NETIF_MSG_TX_ERR | NETIF_MSG_RX_ERR
85 | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN;
86
87 static int debug = -1; /* defaults above */
88 module_param(debug, int, 0);
89 MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
90
91 static int copybreak __read_mostly = 128;
92 module_param(copybreak, int, 0);
93 MODULE_PARM_DESC(copybreak, "Receive copy threshold");
94
95 static int disable_msi = 0;
96 module_param(disable_msi, int, 0);
97 MODULE_PARM_DESC(disable_msi, "Disable Message Signaled Interrupt (MSI)");
98
99 static int idle_timeout = 0;
100 module_param(idle_timeout, int, 0);
101 MODULE_PARM_DESC(idle_timeout, "Watchdog timer for lost interrupts (ms)");
102
103 static const struct pci_device_id sky2_id_table[] = {
104 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9000) }, /* SK-9Sxx */
105 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9E00) }, /* SK-9Exx */
106 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4b00) }, /* DGE-560T */
107 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4001) }, /* DGE-550SX */
108 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4B02) }, /* DGE-560SX */
109 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4B03) }, /* DGE-550T */
110 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4340) }, /* 88E8021 */
111 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4341) }, /* 88E8022 */
112 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4342) }, /* 88E8061 */
113 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4343) }, /* 88E8062 */
114 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4344) }, /* 88E8021 */
115 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4345) }, /* 88E8022 */
116 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4346) }, /* 88E8061 */
117 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4347) }, /* 88E8062 */
118 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4350) }, /* 88E8035 */
119 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4351) }, /* 88E8036 */
120 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4352) }, /* 88E8038 */
121 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4353) }, /* 88E8039 */
122 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4356) }, /* 88EC033 */
123 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4360) }, /* 88E8052 */
124 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4361) }, /* 88E8050 */
125 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4362) }, /* 88E8053 */
126 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4363) }, /* 88E8055 */
127 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4364) }, /* 88E8056 */
128 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4366) }, /* 88EC036 */
129 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4367) }, /* 88EC032 */
130 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4368) }, /* 88EC034 */
131 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4369) }, /* 88EC042 */
132 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436A) }, /* 88E8058 */
133 // { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436B) }, /* 88E8071 */
134 { 0 }
135 };
136
137 MODULE_DEVICE_TABLE(pci, sky2_id_table);
138
139 /* Avoid conditionals by using array */
140 static const unsigned txqaddr[] = { Q_XA1, Q_XA2 };
141 static const unsigned rxqaddr[] = { Q_R1, Q_R2 };
142 static const u32 portirq_msk[] = { Y2_IS_PORT_1, Y2_IS_PORT_2 };
143
144 /* This driver supports yukon2 chipset only */
145 static const char *yukon2_name[] = {
146 "XL", /* 0xb3 */
147 "EC Ultra", /* 0xb4 */
148 "Extreme", /* 0xb5 */
149 "EC", /* 0xb6 */
150 "FE", /* 0xb7 */
151 };
152
153 /* Access to external PHY */
154 static int gm_phy_write(struct sky2_hw *hw, unsigned port, u16 reg, u16 val)
155 {
156 int i;
157
158 gma_write16(hw, port, GM_SMI_DATA, val);
159 gma_write16(hw, port, GM_SMI_CTRL,
160 GM_SMI_CT_PHY_AD(PHY_ADDR_MARV) | GM_SMI_CT_REG_AD(reg));
161
162 for (i = 0; i < PHY_RETRIES; i++) {
163 if (!(gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_BUSY))
164 return 0;
165 udelay(1);
166 }
167
168 printk(KERN_WARNING PFX "%s: phy write timeout\n", hw->dev[port]->name);
169 return -ETIMEDOUT;
170 }
171
172 static int __gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg, u16 *val)
173 {
174 int i;
175
176 gma_write16(hw, port, GM_SMI_CTRL, GM_SMI_CT_PHY_AD(PHY_ADDR_MARV)
177 | GM_SMI_CT_REG_AD(reg) | GM_SMI_CT_OP_RD);
178
179 for (i = 0; i < PHY_RETRIES; i++) {
180 if (gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_RD_VAL) {
181 *val = gma_read16(hw, port, GM_SMI_DATA);
182 return 0;
183 }
184
185 udelay(1);
186 }
187
188 return -ETIMEDOUT;
189 }
190
191 static u16 gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg)
192 {
193 u16 v;
194
195 if (__gm_phy_read(hw, port, reg, &v) != 0)
196 printk(KERN_WARNING PFX "%s: phy read timeout\n", hw->dev[port]->name);
197 return v;
198 }
199
200
201 static void sky2_power_on(struct sky2_hw *hw)
202 {
203 /* switch power to VCC (WA for VAUX problem) */
204 sky2_write8(hw, B0_POWER_CTRL,
205 PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_OFF | PC_VCC_ON);
206
207 /* disable Core Clock Division, */
208 sky2_write32(hw, B2_Y2_CLK_CTRL, Y2_CLK_DIV_DIS);
209
210 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
211 /* enable bits are inverted */
212 sky2_write8(hw, B2_Y2_CLK_GATE,
213 Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
214 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
215 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
216 else
217 sky2_write8(hw, B2_Y2_CLK_GATE, 0);
218
219 if (hw->chip_id == CHIP_ID_YUKON_EC_U || hw->chip_id == CHIP_ID_YUKON_EX) {
220 u32 reg1;
221
222 sky2_pci_write32(hw, PCI_DEV_REG3, 0);
223 reg1 = sky2_pci_read32(hw, PCI_DEV_REG4);
224 reg1 &= P_ASPM_CONTROL_MSK;
225 sky2_pci_write32(hw, PCI_DEV_REG4, reg1);
226 sky2_pci_write32(hw, PCI_DEV_REG5, 0);
227 }
228 }
229
230 static void sky2_power_aux(struct sky2_hw *hw)
231 {
232 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
233 sky2_write8(hw, B2_Y2_CLK_GATE, 0);
234 else
235 /* enable bits are inverted */
236 sky2_write8(hw, B2_Y2_CLK_GATE,
237 Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
238 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
239 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
240
241 /* switch power to VAUX */
242 if (sky2_read16(hw, B0_CTST) & Y2_VAUX_AVAIL)
243 sky2_write8(hw, B0_POWER_CTRL,
244 (PC_VAUX_ENA | PC_VCC_ENA |
245 PC_VAUX_ON | PC_VCC_OFF));
246 }
247
248 static void sky2_gmac_reset(struct sky2_hw *hw, unsigned port)
249 {
250 u16 reg;
251
252 /* disable all GMAC IRQ's */
253 sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0);
254 /* disable PHY IRQs */
255 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);
256
257 gma_write16(hw, port, GM_MC_ADDR_H1, 0); /* clear MC hash */
258 gma_write16(hw, port, GM_MC_ADDR_H2, 0);
259 gma_write16(hw, port, GM_MC_ADDR_H3, 0);
260 gma_write16(hw, port, GM_MC_ADDR_H4, 0);
261
262 reg = gma_read16(hw, port, GM_RX_CTRL);
263 reg |= GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA;
264 gma_write16(hw, port, GM_RX_CTRL, reg);
265 }
266
267 /* flow control to advertise bits */
268 static const u16 copper_fc_adv[] = {
269 [FC_NONE] = 0,
270 [FC_TX] = PHY_M_AN_ASP,
271 [FC_RX] = PHY_M_AN_PC,
272 [FC_BOTH] = PHY_M_AN_PC | PHY_M_AN_ASP,
273 };
274
275 /* flow control to advertise bits when using 1000BaseX */
276 static const u16 fiber_fc_adv[] = {
277 [FC_BOTH] = PHY_M_P_BOTH_MD_X,
278 [FC_TX] = PHY_M_P_ASYM_MD_X,
279 [FC_RX] = PHY_M_P_SYM_MD_X,
280 [FC_NONE] = PHY_M_P_NO_PAUSE_X,
281 };
282
283 /* flow control to GMA disable bits */
284 static const u16 gm_fc_disable[] = {
285 [FC_NONE] = GM_GPCR_FC_RX_DIS | GM_GPCR_FC_TX_DIS,
286 [FC_TX] = GM_GPCR_FC_RX_DIS,
287 [FC_RX] = GM_GPCR_FC_TX_DIS,
288 [FC_BOTH] = 0,
289 };
290
291
292 static void sky2_phy_init(struct sky2_hw *hw, unsigned port)
293 {
294 struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
295 u16 ctrl, ct1000, adv, pg, ledctrl, ledover, reg;
296
297 if (sky2->autoneg == AUTONEG_ENABLE
298 && !(hw->chip_id == CHIP_ID_YUKON_XL
299 || hw->chip_id == CHIP_ID_YUKON_EC_U
300 || hw->chip_id == CHIP_ID_YUKON_EX)) {
301 u16 ectrl = gm_phy_read(hw, port, PHY_MARV_EXT_CTRL);
302
303 ectrl &= ~(PHY_M_EC_M_DSC_MSK | PHY_M_EC_S_DSC_MSK |
304 PHY_M_EC_MAC_S_MSK);
305 ectrl |= PHY_M_EC_MAC_S(MAC_TX_CLK_25_MHZ);
306
307 /* on PHY 88E1040 Rev.D0 (and newer) downshift control changed */
308 if (hw->chip_id == CHIP_ID_YUKON_EC)
309 /* set downshift counter to 3x and enable downshift */
310 ectrl |= PHY_M_EC_DSC_2(2) | PHY_M_EC_DOWN_S_ENA;
311 else
312 /* set master & slave downshift counter to 1x */
313 ectrl |= PHY_M_EC_M_DSC(0) | PHY_M_EC_S_DSC(1);
314
315 gm_phy_write(hw, port, PHY_MARV_EXT_CTRL, ectrl);
316 }
317
318 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
319 if (sky2_is_copper(hw)) {
320 if (hw->chip_id == CHIP_ID_YUKON_FE) {
321 /* enable automatic crossover */
322 ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO) >> 1;
323 } else {
324 /* disable energy detect */
325 ctrl &= ~PHY_M_PC_EN_DET_MSK;
326
327 /* enable automatic crossover */
328 ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO);
329
330 /* downshift on PHY 88E1112 and 88E1149 is changed */
331 if (sky2->autoneg == AUTONEG_ENABLE
332 && (hw->chip_id == CHIP_ID_YUKON_XL
333 || hw->chip_id == CHIP_ID_YUKON_EC_U
334 || hw->chip_id == CHIP_ID_YUKON_EX)) {
335 /* set downshift counter to 3x and enable downshift */
336 ctrl &= ~PHY_M_PC_DSC_MSK;
337 ctrl |= PHY_M_PC_DSC(2) | PHY_M_PC_DOWN_S_ENA;
338 }
339 }
340 } else {
341 /* workaround for deviation #4.88 (CRC errors) */
342 /* disable Automatic Crossover */
343
344 ctrl &= ~PHY_M_PC_MDIX_MSK;
345 }
346
347 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
348
349 /* special setup for PHY 88E1112 Fiber */
350 if (hw->chip_id == CHIP_ID_YUKON_XL && !sky2_is_copper(hw)) {
351 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
352
353 /* Fiber: select 1000BASE-X only mode MAC Specific Ctrl Reg. */
354 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 2);
355 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
356 ctrl &= ~PHY_M_MAC_MD_MSK;
357 ctrl |= PHY_M_MAC_MODE_SEL(PHY_M_MAC_MD_1000BX);
358 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
359
360 if (hw->pmd_type == 'P') {
361 /* select page 1 to access Fiber registers */
362 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 1);
363
364 /* for SFP-module set SIGDET polarity to low */
365 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
366 ctrl |= PHY_M_FIB_SIGD_POL;
367 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
368 }
369
370 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
371 }
372
373 ctrl = PHY_CT_RESET;
374 ct1000 = 0;
375 adv = PHY_AN_CSMA;
376 reg = 0;
377
378 if (sky2->autoneg == AUTONEG_ENABLE) {
379 if (sky2_is_copper(hw)) {
380 if (sky2->advertising & ADVERTISED_1000baseT_Full)
381 ct1000 |= PHY_M_1000C_AFD;
382 if (sky2->advertising & ADVERTISED_1000baseT_Half)
383 ct1000 |= PHY_M_1000C_AHD;
384 if (sky2->advertising & ADVERTISED_100baseT_Full)
385 adv |= PHY_M_AN_100_FD;
386 if (sky2->advertising & ADVERTISED_100baseT_Half)
387 adv |= PHY_M_AN_100_HD;
388 if (sky2->advertising & ADVERTISED_10baseT_Full)
389 adv |= PHY_M_AN_10_FD;
390 if (sky2->advertising & ADVERTISED_10baseT_Half)
391 adv |= PHY_M_AN_10_HD;
392
393 adv |= copper_fc_adv[sky2->flow_mode];
394 } else { /* special defines for FIBER (88E1040S only) */
395 if (sky2->advertising & ADVERTISED_1000baseT_Full)
396 adv |= PHY_M_AN_1000X_AFD;
397 if (sky2->advertising & ADVERTISED_1000baseT_Half)
398 adv |= PHY_M_AN_1000X_AHD;
399
400 adv |= fiber_fc_adv[sky2->flow_mode];
401 }
402
403 /* Restart Auto-negotiation */
404 ctrl |= PHY_CT_ANE | PHY_CT_RE_CFG;
405 } else {
406 /* forced speed/duplex settings */
407 ct1000 = PHY_M_1000C_MSE;
408
409 /* Disable auto update for duplex flow control and speed */
410 reg |= GM_GPCR_AU_ALL_DIS;
411
412 switch (sky2->speed) {
413 case SPEED_1000:
414 ctrl |= PHY_CT_SP1000;
415 reg |= GM_GPCR_SPEED_1000;
416 break;
417 case SPEED_100:
418 ctrl |= PHY_CT_SP100;
419 reg |= GM_GPCR_SPEED_100;
420 break;
421 }
422
423 if (sky2->duplex == DUPLEX_FULL) {
424 reg |= GM_GPCR_DUP_FULL;
425 ctrl |= PHY_CT_DUP_MD;
426 } else if (sky2->speed < SPEED_1000)
427 sky2->flow_mode = FC_NONE;
428
429
430 reg |= gm_fc_disable[sky2->flow_mode];
431
432 /* Forward pause packets to GMAC? */
433 if (sky2->flow_mode & FC_RX)
434 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
435 else
436 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
437 }
438
439 gma_write16(hw, port, GM_GP_CTRL, reg);
440
441 if (hw->chip_id != CHIP_ID_YUKON_FE)
442 gm_phy_write(hw, port, PHY_MARV_1000T_CTRL, ct1000);
443
444 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, adv);
445 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
446
447 /* Setup Phy LED's */
448 ledctrl = PHY_M_LED_PULS_DUR(PULS_170MS);
449 ledover = 0;
450
451 switch (hw->chip_id) {
452 case CHIP_ID_YUKON_FE:
453 /* on 88E3082 these bits are at 11..9 (shifted left) */
454 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) << 1;
455
456 ctrl = gm_phy_read(hw, port, PHY_MARV_FE_LED_PAR);
457
458 /* delete ACT LED control bits */
459 ctrl &= ~PHY_M_FELP_LED1_MSK;
460 /* change ACT LED control to blink mode */
461 ctrl |= PHY_M_FELP_LED1_CTRL(LED_PAR_CTRL_ACT_BL);
462 gm_phy_write(hw, port, PHY_MARV_FE_LED_PAR, ctrl);
463 break;
464
465 case CHIP_ID_YUKON_XL:
466 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
467
468 /* select page 3 to access LED control register */
469 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
470
471 /* set LED Function Control register */
472 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
473 (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
474 PHY_M_LEDC_INIT_CTRL(7) | /* 10 Mbps */
475 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
476 PHY_M_LEDC_STA0_CTRL(7))); /* 1000 Mbps */
477
478 /* set Polarity Control register */
479 gm_phy_write(hw, port, PHY_MARV_PHY_STAT,
480 (PHY_M_POLC_LS1_P_MIX(4) |
481 PHY_M_POLC_IS0_P_MIX(4) |
482 PHY_M_POLC_LOS_CTRL(2) |
483 PHY_M_POLC_INIT_CTRL(2) |
484 PHY_M_POLC_STA1_CTRL(2) |
485 PHY_M_POLC_STA0_CTRL(2)));
486
487 /* restore page register */
488 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
489 break;
490
491 case CHIP_ID_YUKON_EC_U:
492 case CHIP_ID_YUKON_EX:
493 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
494
495 /* select page 3 to access LED control register */
496 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
497
498 /* set LED Function Control register */
499 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
500 (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
501 PHY_M_LEDC_INIT_CTRL(8) | /* 10 Mbps */
502 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
503 PHY_M_LEDC_STA0_CTRL(7)));/* 1000 Mbps */
504
505 /* set Blink Rate in LED Timer Control Register */
506 gm_phy_write(hw, port, PHY_MARV_INT_MASK,
507 ledctrl | PHY_M_LED_BLINK_RT(BLINK_84MS));
508 /* restore page register */
509 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
510 break;
511
512 default:
513 /* set Tx LED (LED_TX) to blink mode on Rx OR Tx activity */
514 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) | PHY_M_LEDC_TX_CTRL;
515 /* turn off the Rx LED (LED_RX) */
516 ledover &= ~PHY_M_LED_MO_RX;
517 }
518
519 if (hw->chip_id == CHIP_ID_YUKON_EC_U &&
520 hw->chip_rev == CHIP_REV_YU_EC_U_A1) {
521 /* apply fixes in PHY AFE */
522 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 255);
523
524 /* increase differential signal amplitude in 10BASE-T */
525 gm_phy_write(hw, port, 0x18, 0xaa99);
526 gm_phy_write(hw, port, 0x17, 0x2011);
527
528 /* fix for IEEE A/B Symmetry failure in 1000BASE-T */
529 gm_phy_write(hw, port, 0x18, 0xa204);
530 gm_phy_write(hw, port, 0x17, 0x2002);
531
532 /* set page register to 0 */
533 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0);
534 } else if (hw->chip_id != CHIP_ID_YUKON_EX) {
535 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl);
536
537 if (sky2->autoneg == AUTONEG_DISABLE || sky2->speed == SPEED_100) {
538 /* turn on 100 Mbps LED (LED_LINK100) */
539 ledover |= PHY_M_LED_MO_100;
540 }
541
542 if (ledover)
543 gm_phy_write(hw, port, PHY_MARV_LED_OVER, ledover);
544
545 }
546
547 /* Enable phy interrupt on auto-negotiation complete (or link up) */
548 if (sky2->autoneg == AUTONEG_ENABLE)
549 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_AN_COMPL);
550 else
551 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
552 }
553
554 static void sky2_phy_power(struct sky2_hw *hw, unsigned port, int onoff)
555 {
556 u32 reg1;
557 static const u32 phy_power[]
558 = { PCI_Y2_PHY1_POWD, PCI_Y2_PHY2_POWD };
559
560 /* looks like this XL is back asswards .. */
561 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
562 onoff = !onoff;
563
564 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
565 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);
566 if (onoff)
567 /* Turn off phy power saving */
568 reg1 &= ~phy_power[port];
569 else
570 reg1 |= phy_power[port];
571
572 sky2_pci_write32(hw, PCI_DEV_REG1, reg1);
573 sky2_pci_read32(hw, PCI_DEV_REG1);
574 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
575 udelay(100);
576 }
577
578 /* Force a renegotiation */
579 static void sky2_phy_reinit(struct sky2_port *sky2)
580 {
581 spin_lock_bh(&sky2->phy_lock);
582 sky2_phy_init(sky2->hw, sky2->port);
583 spin_unlock_bh(&sky2->phy_lock);
584 }
585
586 /* Put device in state to listen for Wake On Lan */
587 static void sky2_wol_init(struct sky2_port *sky2)
588 {
589 struct sky2_hw *hw = sky2->hw;
590 unsigned port = sky2->port;
591 enum flow_control save_mode;
592 u16 ctrl;
593 u32 reg1;
594
595 /* Bring hardware out of reset */
596 sky2_write16(hw, B0_CTST, CS_RST_CLR);
597 sky2_write16(hw, SK_REG(port, GMAC_LINK_CTRL), GMLC_RST_CLR);
598
599 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
600 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
601
602 /* Force to 10/100
603 * sky2_reset will re-enable on resume
604 */
605 save_mode = sky2->flow_mode;
606 ctrl = sky2->advertising;
607
608 sky2->advertising &= ~(ADVERTISED_1000baseT_Half|ADVERTISED_1000baseT_Full);
609 sky2->flow_mode = FC_NONE;
610 sky2_phy_power(hw, port, 1);
611 sky2_phy_reinit(sky2);
612
613 sky2->flow_mode = save_mode;
614 sky2->advertising = ctrl;
615
616 /* Set GMAC to no flow control and auto update for speed/duplex */
617 gma_write16(hw, port, GM_GP_CTRL,
618 GM_GPCR_FC_TX_DIS|GM_GPCR_TX_ENA|GM_GPCR_RX_ENA|
619 GM_GPCR_DUP_FULL|GM_GPCR_FC_RX_DIS|GM_GPCR_AU_FCT_DIS);
620
621 /* Set WOL address */
622 memcpy_toio(hw->regs + WOL_REGS(port, WOL_MAC_ADDR),
623 sky2->netdev->dev_addr, ETH_ALEN);
624
625 /* Turn on appropriate WOL control bits */
626 sky2_write16(hw, WOL_REGS(port, WOL_CTRL_STAT), WOL_CTL_CLEAR_RESULT);
627 ctrl = 0;
628 if (sky2->wol & WAKE_PHY)
629 ctrl |= WOL_CTL_ENA_PME_ON_LINK_CHG|WOL_CTL_ENA_LINK_CHG_UNIT;
630 else
631 ctrl |= WOL_CTL_DIS_PME_ON_LINK_CHG|WOL_CTL_DIS_LINK_CHG_UNIT;
632
633 if (sky2->wol & WAKE_MAGIC)
634 ctrl |= WOL_CTL_ENA_PME_ON_MAGIC_PKT|WOL_CTL_ENA_MAGIC_PKT_UNIT;
635 else
636 ctrl |= WOL_CTL_DIS_PME_ON_MAGIC_PKT|WOL_CTL_DIS_MAGIC_PKT_UNIT;;
637
638 ctrl |= WOL_CTL_DIS_PME_ON_PATTERN|WOL_CTL_DIS_PATTERN_UNIT;
639 sky2_write16(hw, WOL_REGS(port, WOL_CTRL_STAT), ctrl);
640
641 /* Turn on legacy PCI-Express PME mode */
642 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
643 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);
644 reg1 |= PCI_Y2_PME_LEGACY;
645 sky2_pci_write32(hw, PCI_DEV_REG1, reg1);
646 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
647
648 /* block receiver */
649 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
650
651 }
652
653 static void sky2_mac_init(struct sky2_hw *hw, unsigned port)
654 {
655 struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
656 u16 reg;
657 int i;
658 const u8 *addr = hw->dev[port]->dev_addr;
659
660 sky2_write32(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
661 sky2_write32(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
662
663 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
664
665 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0 && port == 1) {
666 /* WA DEV_472 -- looks like crossed wires on port 2 */
667 /* clear GMAC 1 Control reset */
668 sky2_write8(hw, SK_REG(0, GMAC_CTRL), GMC_RST_CLR);
669 do {
670 sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_SET);
671 sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_CLR);
672 } while (gm_phy_read(hw, 1, PHY_MARV_ID0) != PHY_MARV_ID0_VAL ||
673 gm_phy_read(hw, 1, PHY_MARV_ID1) != PHY_MARV_ID1_Y2 ||
674 gm_phy_read(hw, 1, PHY_MARV_INT_MASK) != 0);
675 }
676
677 sky2_read16(hw, SK_REG(port, GMAC_IRQ_SRC));
678
679 /* Enable Transmit FIFO Underrun */
680 sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), GMAC_DEF_MSK);
681
682 spin_lock_bh(&sky2->phy_lock);
683 sky2_phy_init(hw, port);
684 spin_unlock_bh(&sky2->phy_lock);
685
686 /* MIB clear */
687 reg = gma_read16(hw, port, GM_PHY_ADDR);
688 gma_write16(hw, port, GM_PHY_ADDR, reg | GM_PAR_MIB_CLR);
689
690 for (i = GM_MIB_CNT_BASE; i <= GM_MIB_CNT_END; i += 4)
691 gma_read16(hw, port, i);
692 gma_write16(hw, port, GM_PHY_ADDR, reg);
693
694 /* transmit control */
695 gma_write16(hw, port, GM_TX_CTRL, TX_COL_THR(TX_COL_DEF));
696
697 /* receive control reg: unicast + multicast + no FCS */
698 gma_write16(hw, port, GM_RX_CTRL,
699 GM_RXCR_UCF_ENA | GM_RXCR_CRC_DIS | GM_RXCR_MCF_ENA);
700
701 /* transmit flow control */
702 gma_write16(hw, port, GM_TX_FLOW_CTRL, 0xffff);
703
704 /* transmit parameter */
705 gma_write16(hw, port, GM_TX_PARAM,
706 TX_JAM_LEN_VAL(TX_JAM_LEN_DEF) |
707 TX_JAM_IPG_VAL(TX_JAM_IPG_DEF) |
708 TX_IPG_JAM_DATA(TX_IPG_JAM_DEF) |
709 TX_BACK_OFF_LIM(TX_BOF_LIM_DEF));
710
711 /* serial mode register */
712 reg = DATA_BLIND_VAL(DATA_BLIND_DEF) |
713 GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
714
715 if (hw->dev[port]->mtu > ETH_DATA_LEN)
716 reg |= GM_SMOD_JUMBO_ENA;
717
718 gma_write16(hw, port, GM_SERIAL_MODE, reg);
719
720 /* virtual address for data */
721 gma_set_addr(hw, port, GM_SRC_ADDR_2L, addr);
722
723 /* physical address: used for pause frames */
724 gma_set_addr(hw, port, GM_SRC_ADDR_1L, addr);
725
726 /* ignore counter overflows */
727 gma_write16(hw, port, GM_TX_IRQ_MSK, 0);
728 gma_write16(hw, port, GM_RX_IRQ_MSK, 0);
729 gma_write16(hw, port, GM_TR_IRQ_MSK, 0);
730
731 /* Configure Rx MAC FIFO */
732 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_CLR);
733 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T),
734 GMF_OPER_ON | GMF_RX_F_FL_ON);
735
736 /* Flush Rx MAC FIFO on any flow control or error */
737 sky2_write16(hw, SK_REG(port, RX_GMF_FL_MSK), GMR_FS_ANY_ERR);
738
739 /* Set threshold to 0xa (64 bytes) + 1 to workaround pause bug */
740 sky2_write16(hw, SK_REG(port, RX_GMF_FL_THR), RX_GMF_FL_THR_DEF+1);
741
742 /* Configure Tx MAC FIFO */
743 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_CLR);
744 sky2_write16(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_OPER_ON);
745
746 if (hw->chip_id == CHIP_ID_YUKON_EC_U || hw->chip_id == CHIP_ID_YUKON_EX) {
747 sky2_write8(hw, SK_REG(port, RX_GMF_LP_THR), 768/8);
748 sky2_write8(hw, SK_REG(port, RX_GMF_UP_THR), 1024/8);
749
750 /* set Tx GMAC FIFO Almost Empty Threshold */
751 sky2_write32(hw, SK_REG(port, TX_GMF_AE_THR),
752 (ECU_JUMBO_WM << 16) | ECU_AE_THR);
753
754 if (hw->dev[port]->mtu > ETH_DATA_LEN)
755 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
756 TX_JUMBO_ENA | TX_STFW_DIS);
757 else
758 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
759 TX_JUMBO_DIS | TX_STFW_ENA);
760 }
761
762 }
763
764 /* Assign Ram Buffer allocation to queue */
765 static void sky2_ramset(struct sky2_hw *hw, u16 q, u32 start, u32 space)
766 {
767 u32 end;
768
769 /* convert from K bytes to qwords used for hw register */
770 start *= 1024/8;
771 space *= 1024/8;
772 end = start + space - 1;
773
774 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_RST_CLR);
775 sky2_write32(hw, RB_ADDR(q, RB_START), start);
776 sky2_write32(hw, RB_ADDR(q, RB_END), end);
777 sky2_write32(hw, RB_ADDR(q, RB_WP), start);
778 sky2_write32(hw, RB_ADDR(q, RB_RP), start);
779
780 if (q == Q_R1 || q == Q_R2) {
781 u32 tp = space - space/4;
782
783 /* On receive queue's set the thresholds
784 * give receiver priority when > 3/4 full
785 * send pause when down to 2K
786 */
787 sky2_write32(hw, RB_ADDR(q, RB_RX_UTHP), tp);
788 sky2_write32(hw, RB_ADDR(q, RB_RX_LTHP), space/2);
789
790 tp = space - 2048/8;
791 sky2_write32(hw, RB_ADDR(q, RB_RX_UTPP), tp);
792 sky2_write32(hw, RB_ADDR(q, RB_RX_LTPP), space/4);
793 } else {
794 /* Enable store & forward on Tx queue's because
795 * Tx FIFO is only 1K on Yukon
796 */
797 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_STFWD);
798 }
799
800 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_OP_MD);
801 sky2_read8(hw, RB_ADDR(q, RB_CTRL));
802 }
803
804 /* Setup Bus Memory Interface */
805 static void sky2_qset(struct sky2_hw *hw, u16 q)
806 {
807 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_CLR_RESET);
808 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_OPER_INIT);
809 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_FIFO_OP_ON);
810 sky2_write32(hw, Q_ADDR(q, Q_WM), BMU_WM_DEFAULT);
811 }
812
813 /* Setup prefetch unit registers. This is the interface between
814 * hardware and driver list elements
815 */
816 static void sky2_prefetch_init(struct sky2_hw *hw, u32 qaddr,
817 u64 addr, u32 last)
818 {
819 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
820 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_CLR);
821 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_HI), addr >> 32);
822 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_LO), (u32) addr);
823 sky2_write16(hw, Y2_QADDR(qaddr, PREF_UNIT_LAST_IDX), last);
824 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_OP_ON);
825
826 sky2_read32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL));
827 }
828
829 static inline struct sky2_tx_le *get_tx_le(struct sky2_port *sky2)
830 {
831 struct sky2_tx_le *le = sky2->tx_le + sky2->tx_prod;
832
833 sky2->tx_prod = RING_NEXT(sky2->tx_prod, TX_RING_SIZE);
834 le->ctrl = 0;
835 return le;
836 }
837
838 static inline struct tx_ring_info *tx_le_re(struct sky2_port *sky2,
839 struct sky2_tx_le *le)
840 {
841 return sky2->tx_ring + (le - sky2->tx_le);
842 }
843
844 /* Update chip's next pointer */
845 static inline void sky2_put_idx(struct sky2_hw *hw, unsigned q, u16 idx)
846 {
847 /* Make sure write' to descriptors are complete before we tell hardware */
848 wmb();
849 sky2_write16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX), idx);
850
851 /* Synchronize I/O on since next processor may write to tail */
852 mmiowb();
853 }
854
855
856 static inline struct sky2_rx_le *sky2_next_rx(struct sky2_port *sky2)
857 {
858 struct sky2_rx_le *le = sky2->rx_le + sky2->rx_put;
859 sky2->rx_put = RING_NEXT(sky2->rx_put, RX_LE_SIZE);
860 le->ctrl = 0;
861 return le;
862 }
863
864 /* Return high part of DMA address (could be 32 or 64 bit) */
865 static inline u32 high32(dma_addr_t a)
866 {
867 return sizeof(a) > sizeof(u32) ? (a >> 16) >> 16 : 0;
868 }
869
870 /* Build description to hardware for one receive segment */
871 static void sky2_rx_add(struct sky2_port *sky2, u8 op,
872 dma_addr_t map, unsigned len)
873 {
874 struct sky2_rx_le *le;
875 u32 hi = high32(map);
876
877 if (sky2->rx_addr64 != hi) {
878 le = sky2_next_rx(sky2);
879 le->addr = cpu_to_le32(hi);
880 le->opcode = OP_ADDR64 | HW_OWNER;
881 sky2->rx_addr64 = high32(map + len);
882 }
883
884 le = sky2_next_rx(sky2);
885 le->addr = cpu_to_le32((u32) map);
886 le->length = cpu_to_le16(len);
887 le->opcode = op | HW_OWNER;
888 }
889
890 /* Build description to hardware for one possibly fragmented skb */
891 static void sky2_rx_submit(struct sky2_port *sky2,
892 const struct rx_ring_info *re)
893 {
894 int i;
895
896 sky2_rx_add(sky2, OP_PACKET, re->data_addr, sky2->rx_data_size);
897
898 for (i = 0; i < skb_shinfo(re->skb)->nr_frags; i++)
899 sky2_rx_add(sky2, OP_BUFFER, re->frag_addr[i], PAGE_SIZE);
900 }
901
902
903 static void sky2_rx_map_skb(struct pci_dev *pdev, struct rx_ring_info *re,
904 unsigned size)
905 {
906 struct sk_buff *skb = re->skb;
907 int i;
908
909 re->data_addr = pci_map_single(pdev, skb->data, size, PCI_DMA_FROMDEVICE);
910 pci_unmap_len_set(re, data_size, size);
911
912 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++)
913 re->frag_addr[i] = pci_map_page(pdev,
914 skb_shinfo(skb)->frags[i].page,
915 skb_shinfo(skb)->frags[i].page_offset,
916 skb_shinfo(skb)->frags[i].size,
917 PCI_DMA_FROMDEVICE);
918 }
919
920 static void sky2_rx_unmap_skb(struct pci_dev *pdev, struct rx_ring_info *re)
921 {
922 struct sk_buff *skb = re->skb;
923 int i;
924
925 pci_unmap_single(pdev, re->data_addr, pci_unmap_len(re, data_size),
926 PCI_DMA_FROMDEVICE);
927
928 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++)
929 pci_unmap_page(pdev, re->frag_addr[i],
930 skb_shinfo(skb)->frags[i].size,
931 PCI_DMA_FROMDEVICE);
932 }
933
934 /* Tell chip where to start receive checksum.
935 * Actually has two checksums, but set both same to avoid possible byte
936 * order problems.
937 */
938 static void rx_set_checksum(struct sky2_port *sky2)
939 {
940 struct sky2_rx_le *le;
941
942 le = sky2_next_rx(sky2);
943 le->addr = cpu_to_le32((ETH_HLEN << 16) | ETH_HLEN);
944 le->ctrl = 0;
945 le->opcode = OP_TCPSTART | HW_OWNER;
946
947 sky2_write32(sky2->hw,
948 Q_ADDR(rxqaddr[sky2->port], Q_CSR),
949 sky2->rx_csum ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);
950
951 }
952
953 /*
954 * The RX Stop command will not work for Yukon-2 if the BMU does not
955 * reach the end of packet and since we can't make sure that we have
956 * incoming data, we must reset the BMU while it is not doing a DMA
957 * transfer. Since it is possible that the RX path is still active,
958 * the RX RAM buffer will be stopped first, so any possible incoming
959 * data will not trigger a DMA. After the RAM buffer is stopped, the
960 * BMU is polled until any DMA in progress is ended and only then it
961 * will be reset.
962 */
963 static void sky2_rx_stop(struct sky2_port *sky2)
964 {
965 struct sky2_hw *hw = sky2->hw;
966 unsigned rxq = rxqaddr[sky2->port];
967 int i;
968
969 /* disable the RAM Buffer receive queue */
970 sky2_write8(hw, RB_ADDR(rxq, RB_CTRL), RB_DIS_OP_MD);
971
972 for (i = 0; i < 0xffff; i++)
973 if (sky2_read8(hw, RB_ADDR(rxq, Q_RSL))
974 == sky2_read8(hw, RB_ADDR(rxq, Q_RL)))
975 goto stopped;
976
977 printk(KERN_WARNING PFX "%s: receiver stop failed\n",
978 sky2->netdev->name);
979 stopped:
980 sky2_write32(hw, Q_ADDR(rxq, Q_CSR), BMU_RST_SET | BMU_FIFO_RST);
981
982 /* reset the Rx prefetch unit */
983 sky2_write32(hw, Y2_QADDR(rxq, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
984 mmiowb();
985 }
986
987 /* Clean out receive buffer area, assumes receiver hardware stopped */
988 static void sky2_rx_clean(struct sky2_port *sky2)
989 {
990 unsigned i;
991
992 memset(sky2->rx_le, 0, RX_LE_BYTES);
993 for (i = 0; i < sky2->rx_pending; i++) {
994 struct rx_ring_info *re = sky2->rx_ring + i;
995
996 if (re->skb) {
997 sky2_rx_unmap_skb(sky2->hw->pdev, re);
998 kfree_skb(re->skb);
999 re->skb = NULL;
1000 }
1001 }
1002 }
1003
1004 /* Basic MII support */
1005 static int sky2_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1006 {
1007 struct mii_ioctl_data *data = if_mii(ifr);
1008 struct sky2_port *sky2 = netdev_priv(dev);
1009 struct sky2_hw *hw = sky2->hw;
1010 int err = -EOPNOTSUPP;
1011
1012 if (!netif_running(dev))
1013 return -ENODEV; /* Phy still in reset */
1014
1015 switch (cmd) {
1016 case SIOCGMIIPHY:
1017 data->phy_id = PHY_ADDR_MARV;
1018
1019 /* fallthru */
1020 case SIOCGMIIREG: {
1021 u16 val = 0;
1022
1023 spin_lock_bh(&sky2->phy_lock);
1024 err = __gm_phy_read(hw, sky2->port, data->reg_num & 0x1f, &val);
1025 spin_unlock_bh(&sky2->phy_lock);
1026
1027 data->val_out = val;
1028 break;
1029 }
1030
1031 case SIOCSMIIREG:
1032 if (!capable(CAP_NET_ADMIN))
1033 return -EPERM;
1034
1035 spin_lock_bh(&sky2->phy_lock);
1036 err = gm_phy_write(hw, sky2->port, data->reg_num & 0x1f,
1037 data->val_in);
1038 spin_unlock_bh(&sky2->phy_lock);
1039 break;
1040 }
1041 return err;
1042 }
1043
1044 #ifdef SKY2_VLAN_TAG_USED
1045 static void sky2_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
1046 {
1047 struct sky2_port *sky2 = netdev_priv(dev);
1048 struct sky2_hw *hw = sky2->hw;
1049 u16 port = sky2->port;
1050
1051 netif_tx_lock_bh(dev);
1052 netif_poll_disable(sky2->hw->dev[0]);
1053
1054 sky2->vlgrp = grp;
1055 if (grp) {
1056 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T),
1057 RX_VLAN_STRIP_ON);
1058 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
1059 TX_VLAN_TAG_ON);
1060 } else {
1061 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T),
1062 RX_VLAN_STRIP_OFF);
1063 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
1064 TX_VLAN_TAG_OFF);
1065 }
1066
1067 netif_poll_enable(sky2->hw->dev[0]);
1068 netif_tx_unlock_bh(dev);
1069 }
1070 #endif
1071
1072 /*
1073 * Allocate an skb for receiving. If the MTU is large enough
1074 * make the skb non-linear with a fragment list of pages.
1075 *
1076 * It appears the hardware has a bug in the FIFO logic that
1077 * cause it to hang if the FIFO gets overrun and the receive buffer
1078 * is not 64 byte aligned. The buffer returned from netdev_alloc_skb is
1079 * aligned except if slab debugging is enabled.
1080 */
1081 static struct sk_buff *sky2_rx_alloc(struct sky2_port *sky2)
1082 {
1083 struct sk_buff *skb;
1084 unsigned long p;
1085 int i;
1086
1087 skb = netdev_alloc_skb(sky2->netdev, sky2->rx_data_size + RX_SKB_ALIGN);
1088 if (!skb)
1089 goto nomem;
1090
1091 p = (unsigned long) skb->data;
1092 skb_reserve(skb, ALIGN(p, RX_SKB_ALIGN) - p);
1093
1094 for (i = 0; i < sky2->rx_nfrags; i++) {
1095 struct page *page = alloc_page(GFP_ATOMIC);
1096
1097 if (!page)
1098 goto free_partial;
1099 skb_fill_page_desc(skb, i, page, 0, PAGE_SIZE);
1100 }
1101
1102 return skb;
1103 free_partial:
1104 kfree_skb(skb);
1105 nomem:
1106 return NULL;
1107 }
1108
1109 /*
1110 * Allocate and setup receiver buffer pool.
1111 * Normal case this ends up creating one list element for skb
1112 * in the receive ring. Worst case if using large MTU and each
1113 * allocation falls on a different 64 bit region, that results
1114 * in 6 list elements per ring entry.
1115 * One element is used for checksum enable/disable, and one
1116 * extra to avoid wrap.
1117 */
1118 static int sky2_rx_start(struct sky2_port *sky2)
1119 {
1120 struct sky2_hw *hw = sky2->hw;
1121 struct rx_ring_info *re;
1122 unsigned rxq = rxqaddr[sky2->port];
1123 unsigned i, size, space, thresh;
1124
1125 sky2->rx_put = sky2->rx_next = 0;
1126 sky2_qset(hw, rxq);
1127
1128 /* On PCI express lowering the watermark gives better performance */
1129 if (pci_find_capability(hw->pdev, PCI_CAP_ID_EXP))
1130 sky2_write32(hw, Q_ADDR(rxq, Q_WM), BMU_WM_PEX);
1131
1132 /* These chips have no ram buffer?
1133 * MAC Rx RAM Read is controlled by hardware */
1134 if (hw->chip_id == CHIP_ID_YUKON_EC_U &&
1135 (hw->chip_rev == CHIP_REV_YU_EC_U_A1
1136 || hw->chip_rev == CHIP_REV_YU_EC_U_B0))
1137 sky2_write32(hw, Q_ADDR(rxq, Q_F), F_M_RX_RAM_DIS);
1138
1139 sky2_prefetch_init(hw, rxq, sky2->rx_le_map, RX_LE_SIZE - 1);
1140
1141 rx_set_checksum(sky2);
1142
1143 /* Space needed for frame data + headers rounded up */
1144 size = ALIGN(sky2->netdev->mtu + ETH_HLEN + VLAN_HLEN, 8)
1145 + 8;
1146
1147 /* Stopping point for hardware truncation */
1148 thresh = (size - 8) / sizeof(u32);
1149
1150 /* Account for overhead of skb - to avoid order > 0 allocation */
1151 space = SKB_DATA_ALIGN(size) + NET_SKB_PAD
1152 + sizeof(struct skb_shared_info);
1153
1154 sky2->rx_nfrags = space >> PAGE_SHIFT;
1155 BUG_ON(sky2->rx_nfrags > ARRAY_SIZE(re->frag_addr));
1156
1157 if (sky2->rx_nfrags != 0) {
1158 /* Compute residue after pages */
1159 space = sky2->rx_nfrags << PAGE_SHIFT;
1160
1161 if (space < size)
1162 size -= space;
1163 else
1164 size = 0;
1165
1166 /* Optimize to handle small packets and headers */
1167 if (size < copybreak)
1168 size = copybreak;
1169 if (size < ETH_HLEN)
1170 size = ETH_HLEN;
1171 }
1172 sky2->rx_data_size = size;
1173
1174 /* Fill Rx ring */
1175 for (i = 0; i < sky2->rx_pending; i++) {
1176 re = sky2->rx_ring + i;
1177
1178 re->skb = sky2_rx_alloc(sky2);
1179 if (!re->skb)
1180 goto nomem;
1181
1182 sky2_rx_map_skb(hw->pdev, re, sky2->rx_data_size);
1183 sky2_rx_submit(sky2, re);
1184 }
1185
1186 /*
1187 * The receiver hangs if it receives frames larger than the
1188 * packet buffer. As a workaround, truncate oversize frames, but
1189 * the register is limited to 9 bits, so if you do frames > 2052
1190 * you better get the MTU right!
1191 */
1192 if (thresh > 0x1ff)
1193 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_TRUNC_OFF);
1194 else {
1195 sky2_write16(hw, SK_REG(sky2->port, RX_GMF_TR_THR), thresh);
1196 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_TRUNC_ON);
1197 }
1198
1199 /* Tell chip about available buffers */
1200 sky2_put_idx(hw, rxq, sky2->rx_put);
1201 return 0;
1202 nomem:
1203 sky2_rx_clean(sky2);
1204 return -ENOMEM;
1205 }
1206
1207 /* Bring up network interface. */
1208 static int sky2_up(struct net_device *dev)
1209 {
1210 struct sky2_port *sky2 = netdev_priv(dev);
1211 struct sky2_hw *hw = sky2->hw;
1212 unsigned port = sky2->port;
1213 u32 ramsize, imask;
1214 int cap, err = -ENOMEM;
1215 struct net_device *otherdev = hw->dev[sky2->port^1];
1216
1217 /*
1218 * On dual port PCI-X card, there is an problem where status
1219 * can be received out of order due to split transactions
1220 */
1221 if (otherdev && netif_running(otherdev) &&
1222 (cap = pci_find_capability(hw->pdev, PCI_CAP_ID_PCIX))) {
1223 struct sky2_port *osky2 = netdev_priv(otherdev);
1224 u16 cmd;
1225
1226 cmd = sky2_pci_read16(hw, cap + PCI_X_CMD);
1227 cmd &= ~PCI_X_CMD_MAX_SPLIT;
1228 sky2_pci_write16(hw, cap + PCI_X_CMD, cmd);
1229
1230 sky2->rx_csum = 0;
1231 osky2->rx_csum = 0;
1232 }
1233
1234 if (netif_msg_ifup(sky2))
1235 printk(KERN_INFO PFX "%s: enabling interface\n", dev->name);
1236
1237 /* must be power of 2 */
1238 sky2->tx_le = pci_alloc_consistent(hw->pdev,
1239 TX_RING_SIZE *
1240 sizeof(struct sky2_tx_le),
1241 &sky2->tx_le_map);
1242 if (!sky2->tx_le)
1243 goto err_out;
1244
1245 sky2->tx_ring = kcalloc(TX_RING_SIZE, sizeof(struct tx_ring_info),
1246 GFP_KERNEL);
1247 if (!sky2->tx_ring)
1248 goto err_out;
1249 sky2->tx_prod = sky2->tx_cons = 0;
1250
1251 sky2->rx_le = pci_alloc_consistent(hw->pdev, RX_LE_BYTES,
1252 &sky2->rx_le_map);
1253 if (!sky2->rx_le)
1254 goto err_out;
1255 memset(sky2->rx_le, 0, RX_LE_BYTES);
1256
1257 sky2->rx_ring = kcalloc(sky2->rx_pending, sizeof(struct rx_ring_info),
1258 GFP_KERNEL);
1259 if (!sky2->rx_ring)
1260 goto err_out;
1261
1262 sky2_phy_power(hw, port, 1);
1263
1264 sky2_mac_init(hw, port);
1265
1266 /* Register is number of 4K blocks on internal RAM buffer. */
1267 ramsize = sky2_read8(hw, B2_E_0) * 4;
1268 printk(KERN_INFO PFX "%s: ram buffer %dK\n", dev->name, ramsize);
1269
1270 if (ramsize > 0) {
1271 u32 rxspace;
1272
1273 if (ramsize < 16)
1274 rxspace = ramsize / 2;
1275 else
1276 rxspace = 8 + (2*(ramsize - 16))/3;
1277
1278 sky2_ramset(hw, rxqaddr[port], 0, rxspace);
1279 sky2_ramset(hw, txqaddr[port], rxspace, ramsize - rxspace);
1280
1281 /* Make sure SyncQ is disabled */
1282 sky2_write8(hw, RB_ADDR(port == 0 ? Q_XS1 : Q_XS2, RB_CTRL),
1283 RB_RST_SET);
1284 }
1285
1286 sky2_qset(hw, txqaddr[port]);
1287
1288 /* Set almost empty threshold */
1289 if (hw->chip_id == CHIP_ID_YUKON_EC_U
1290 && hw->chip_rev == CHIP_REV_YU_EC_U_A0)
1291 sky2_write16(hw, Q_ADDR(txqaddr[port], Q_AL), ECU_TXFF_LEV);
1292
1293 sky2_prefetch_init(hw, txqaddr[port], sky2->tx_le_map,
1294 TX_RING_SIZE - 1);
1295
1296 err = sky2_rx_start(sky2);
1297 if (err)
1298 goto err_out;
1299
1300 /* Enable interrupts from phy/mac for port */
1301 imask = sky2_read32(hw, B0_IMSK);
1302 imask |= portirq_msk[port];
1303 sky2_write32(hw, B0_IMSK, imask);
1304
1305 return 0;
1306
1307 err_out:
1308 if (sky2->rx_le) {
1309 pci_free_consistent(hw->pdev, RX_LE_BYTES,
1310 sky2->rx_le, sky2->rx_le_map);
1311 sky2->rx_le = NULL;
1312 }
1313 if (sky2->tx_le) {
1314 pci_free_consistent(hw->pdev,
1315 TX_RING_SIZE * sizeof(struct sky2_tx_le),
1316 sky2->tx_le, sky2->tx_le_map);
1317 sky2->tx_le = NULL;
1318 }
1319 kfree(sky2->tx_ring);
1320 kfree(sky2->rx_ring);
1321
1322 sky2->tx_ring = NULL;
1323 sky2->rx_ring = NULL;
1324 return err;
1325 }
1326
1327 /* Modular subtraction in ring */
1328 static inline int tx_dist(unsigned tail, unsigned head)
1329 {
1330 return (head - tail) & (TX_RING_SIZE - 1);
1331 }
1332
1333 /* Number of list elements available for next tx */
1334 static inline int tx_avail(const struct sky2_port *sky2)
1335 {
1336 return sky2->tx_pending - tx_dist(sky2->tx_cons, sky2->tx_prod);
1337 }
1338
1339 /* Estimate of number of transmit list elements required */
1340 static unsigned tx_le_req(const struct sk_buff *skb)
1341 {
1342 unsigned count;
1343
1344 count = sizeof(dma_addr_t) / sizeof(u32);
1345 count += skb_shinfo(skb)->nr_frags * count;
1346
1347 if (skb_is_gso(skb))
1348 ++count;
1349
1350 if (skb->ip_summed == CHECKSUM_PARTIAL)
1351 ++count;
1352
1353 return count;
1354 }
1355
1356 /*
1357 * Put one packet in ring for transmit.
1358 * A single packet can generate multiple list elements, and
1359 * the number of ring elements will probably be less than the number
1360 * of list elements used.
1361 */
1362 static int sky2_xmit_frame(struct sk_buff *skb, struct net_device *dev)
1363 {
1364 struct sky2_port *sky2 = netdev_priv(dev);
1365 struct sky2_hw *hw = sky2->hw;
1366 struct sky2_tx_le *le = NULL;
1367 struct tx_ring_info *re;
1368 unsigned i, len;
1369 dma_addr_t mapping;
1370 u32 addr64;
1371 u16 mss;
1372 u8 ctrl;
1373
1374 if (unlikely(tx_avail(sky2) < tx_le_req(skb)))
1375 return NETDEV_TX_BUSY;
1376
1377 if (unlikely(netif_msg_tx_queued(sky2)))
1378 printk(KERN_DEBUG "%s: tx queued, slot %u, len %d\n",
1379 dev->name, sky2->tx_prod, skb->len);
1380
1381 len = skb_headlen(skb);
1382 mapping = pci_map_single(hw->pdev, skb->data, len, PCI_DMA_TODEVICE);
1383 addr64 = high32(mapping);
1384
1385 /* Send high bits if changed or crosses boundary */
1386 if (addr64 != sky2->tx_addr64 || high32(mapping + len) != sky2->tx_addr64) {
1387 le = get_tx_le(sky2);
1388 le->addr = cpu_to_le32(addr64);
1389 le->opcode = OP_ADDR64 | HW_OWNER;
1390 sky2->tx_addr64 = high32(mapping + len);
1391 }
1392
1393 /* Check for TCP Segmentation Offload */
1394 mss = skb_shinfo(skb)->gso_size;
1395 if (mss != 0) {
1396 mss += tcp_optlen(skb); /* TCP options */
1397 mss += ip_hdrlen(skb) + sizeof(struct tcphdr);
1398 mss += ETH_HLEN;
1399
1400 if (mss != sky2->tx_last_mss) {
1401 le = get_tx_le(sky2);
1402 le->addr = cpu_to_le32(mss);
1403 le->opcode = OP_LRGLEN | HW_OWNER;
1404 sky2->tx_last_mss = mss;
1405 }
1406 }
1407
1408 ctrl = 0;
1409 #ifdef SKY2_VLAN_TAG_USED
1410 /* Add VLAN tag, can piggyback on LRGLEN or ADDR64 */
1411 if (sky2->vlgrp && vlan_tx_tag_present(skb)) {
1412 if (!le) {
1413 le = get_tx_le(sky2);
1414 le->addr = 0;
1415 le->opcode = OP_VLAN|HW_OWNER;
1416 } else
1417 le->opcode |= OP_VLAN;
1418 le->length = cpu_to_be16(vlan_tx_tag_get(skb));
1419 ctrl |= INS_VLAN;
1420 }
1421 #endif
1422
1423 /* Handle TCP checksum offload */
1424 if (skb->ip_summed == CHECKSUM_PARTIAL) {
1425 const unsigned offset = skb_transport_offset(skb);
1426 u32 tcpsum;
1427
1428 tcpsum = offset << 16; /* sum start */
1429 tcpsum |= offset + skb->csum_offset; /* sum write */
1430
1431 ctrl |= CALSUM | WR_SUM | INIT_SUM | LOCK_SUM;
1432 if (ip_hdr(skb)->protocol == IPPROTO_UDP)
1433 ctrl |= UDPTCP;
1434
1435 if (tcpsum != sky2->tx_tcpsum) {
1436 sky2->tx_tcpsum = tcpsum;
1437
1438 le = get_tx_le(sky2);
1439 le->addr = cpu_to_le32(tcpsum);
1440 le->length = 0; /* initial checksum value */
1441 le->ctrl = 1; /* one packet */
1442 le->opcode = OP_TCPLISW | HW_OWNER;
1443 }
1444 }
1445
1446 le = get_tx_le(sky2);
1447 le->addr = cpu_to_le32((u32) mapping);
1448 le->length = cpu_to_le16(len);
1449 le->ctrl = ctrl;
1450 le->opcode = mss ? (OP_LARGESEND | HW_OWNER) : (OP_PACKET | HW_OWNER);
1451
1452 re = tx_le_re(sky2, le);
1453 re->skb = skb;
1454 pci_unmap_addr_set(re, mapaddr, mapping);
1455 pci_unmap_len_set(re, maplen, len);
1456
1457 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
1458 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
1459
1460 mapping = pci_map_page(hw->pdev, frag->page, frag->page_offset,
1461 frag->size, PCI_DMA_TODEVICE);
1462 addr64 = high32(mapping);
1463 if (addr64 != sky2->tx_addr64) {
1464 le = get_tx_le(sky2);
1465 le->addr = cpu_to_le32(addr64);
1466 le->ctrl = 0;
1467 le->opcode = OP_ADDR64 | HW_OWNER;
1468 sky2->tx_addr64 = addr64;
1469 }
1470
1471 le = get_tx_le(sky2);
1472 le->addr = cpu_to_le32((u32) mapping);
1473 le->length = cpu_to_le16(frag->size);
1474 le->ctrl = ctrl;
1475 le->opcode = OP_BUFFER | HW_OWNER;
1476
1477 re = tx_le_re(sky2, le);
1478 re->skb = skb;
1479 pci_unmap_addr_set(re, mapaddr, mapping);
1480 pci_unmap_len_set(re, maplen, frag->size);
1481 }
1482
1483 le->ctrl |= EOP;
1484
1485 if (tx_avail(sky2) <= MAX_SKB_TX_LE)
1486 netif_stop_queue(dev);
1487
1488 sky2_put_idx(hw, txqaddr[sky2->port], sky2->tx_prod);
1489
1490 dev->trans_start = jiffies;
1491 return NETDEV_TX_OK;
1492 }
1493
1494 /*
1495 * Free ring elements from starting at tx_cons until "done"
1496 *
1497 * NB: the hardware will tell us about partial completion of multi-part
1498 * buffers so make sure not to free skb to early.
1499 */
1500 static void sky2_tx_complete(struct sky2_port *sky2, u16 done)
1501 {
1502 struct net_device *dev = sky2->netdev;
1503 struct pci_dev *pdev = sky2->hw->pdev;
1504 unsigned idx;
1505
1506 BUG_ON(done >= TX_RING_SIZE);
1507
1508 for (idx = sky2->tx_cons; idx != done;
1509 idx = RING_NEXT(idx, TX_RING_SIZE)) {
1510 struct sky2_tx_le *le = sky2->tx_le + idx;
1511 struct tx_ring_info *re = sky2->tx_ring + idx;
1512
1513 switch(le->opcode & ~HW_OWNER) {
1514 case OP_LARGESEND:
1515 case OP_PACKET:
1516 pci_unmap_single(pdev,
1517 pci_unmap_addr(re, mapaddr),
1518 pci_unmap_len(re, maplen),
1519 PCI_DMA_TODEVICE);
1520 break;
1521 case OP_BUFFER:
1522 pci_unmap_page(pdev, pci_unmap_addr(re, mapaddr),
1523 pci_unmap_len(re, maplen),
1524 PCI_DMA_TODEVICE);
1525 break;
1526 }
1527
1528 if (le->ctrl & EOP) {
1529 if (unlikely(netif_msg_tx_done(sky2)))
1530 printk(KERN_DEBUG "%s: tx done %u\n",
1531 dev->name, idx);
1532 sky2->net_stats.tx_packets++;
1533 sky2->net_stats.tx_bytes += re->skb->len;
1534
1535 dev_kfree_skb_any(re->skb);
1536 }
1537
1538 le->opcode = 0; /* paranoia */
1539 }
1540
1541 sky2->tx_cons = idx;
1542 smp_mb();
1543
1544 if (tx_avail(sky2) > MAX_SKB_TX_LE + 4)
1545 netif_wake_queue(dev);
1546 }
1547
1548 /* Cleanup all untransmitted buffers, assume transmitter not running */
1549 static void sky2_tx_clean(struct net_device *dev)
1550 {
1551 struct sky2_port *sky2 = netdev_priv(dev);
1552
1553 netif_tx_lock_bh(dev);
1554 sky2_tx_complete(sky2, sky2->tx_prod);
1555 netif_tx_unlock_bh(dev);
1556 }
1557
1558 /* Network shutdown */
1559 static int sky2_down(struct net_device *dev)
1560 {
1561 struct sky2_port *sky2 = netdev_priv(dev);
1562 struct sky2_hw *hw = sky2->hw;
1563 unsigned port = sky2->port;
1564 u16 ctrl;
1565 u32 imask;
1566
1567 /* Never really got started! */
1568 if (!sky2->tx_le)
1569 return 0;
1570
1571 if (netif_msg_ifdown(sky2))
1572 printk(KERN_INFO PFX "%s: disabling interface\n", dev->name);
1573
1574 /* Stop more packets from being queued */
1575 netif_stop_queue(dev);
1576 netif_carrier_off(dev);
1577
1578 /* Disable port IRQ */
1579 imask = sky2_read32(hw, B0_IMSK);
1580 imask &= ~portirq_msk[port];
1581 sky2_write32(hw, B0_IMSK, imask);
1582
1583 sky2_gmac_reset(hw, port);
1584
1585 /* Stop transmitter */
1586 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_STOP);
1587 sky2_read32(hw, Q_ADDR(txqaddr[port], Q_CSR));
1588
1589 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL),
1590 RB_RST_SET | RB_DIS_OP_MD);
1591
1592 ctrl = gma_read16(hw, port, GM_GP_CTRL);
1593 ctrl &= ~(GM_GPCR_TX_ENA | GM_GPCR_RX_ENA);
1594 gma_write16(hw, port, GM_GP_CTRL, ctrl);
1595
1596 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
1597
1598 /* Workaround shared GMAC reset */
1599 if (!(hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0
1600 && port == 0 && hw->dev[1] && netif_running(hw->dev[1])))
1601 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET);
1602
1603 /* Disable Force Sync bit and Enable Alloc bit */
1604 sky2_write8(hw, SK_REG(port, TXA_CTRL),
1605 TXA_DIS_FSYNC | TXA_DIS_ALLOC | TXA_STOP_RC);
1606
1607 /* Stop Interval Timer and Limit Counter of Tx Arbiter */
1608 sky2_write32(hw, SK_REG(port, TXA_ITI_INI), 0L);
1609 sky2_write32(hw, SK_REG(port, TXA_LIM_INI), 0L);
1610
1611 /* Reset the PCI FIFO of the async Tx queue */
1612 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR),
1613 BMU_RST_SET | BMU_FIFO_RST);
1614
1615 /* Reset the Tx prefetch units */
1616 sky2_write32(hw, Y2_QADDR(txqaddr[port], PREF_UNIT_CTRL),
1617 PREF_UNIT_RST_SET);
1618
1619 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL), RB_RST_SET);
1620
1621 sky2_rx_stop(sky2);
1622
1623 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
1624 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_SET);
1625
1626 sky2_phy_power(hw, port, 0);
1627
1628 /* turn off LED's */
1629 sky2_write16(hw, B0_Y2LED, LED_STAT_OFF);
1630
1631 synchronize_irq(hw->pdev->irq);
1632
1633 sky2_tx_clean(dev);
1634 sky2_rx_clean(sky2);
1635
1636 pci_free_consistent(hw->pdev, RX_LE_BYTES,
1637 sky2->rx_le, sky2->rx_le_map);
1638 kfree(sky2->rx_ring);
1639
1640 pci_free_consistent(hw->pdev,
1641 TX_RING_SIZE * sizeof(struct sky2_tx_le),
1642 sky2->tx_le, sky2->tx_le_map);
1643 kfree(sky2->tx_ring);
1644
1645 sky2->tx_le = NULL;
1646 sky2->rx_le = NULL;
1647
1648 sky2->rx_ring = NULL;
1649 sky2->tx_ring = NULL;
1650
1651 return 0;
1652 }
1653
1654 static u16 sky2_phy_speed(const struct sky2_hw *hw, u16 aux)
1655 {
1656 if (!sky2_is_copper(hw))
1657 return SPEED_1000;
1658
1659 if (hw->chip_id == CHIP_ID_YUKON_FE)
1660 return (aux & PHY_M_PS_SPEED_100) ? SPEED_100 : SPEED_10;
1661
1662 switch (aux & PHY_M_PS_SPEED_MSK) {
1663 case PHY_M_PS_SPEED_1000:
1664 return SPEED_1000;
1665 case PHY_M_PS_SPEED_100:
1666 return SPEED_100;
1667 default:
1668 return SPEED_10;
1669 }
1670 }
1671
1672 static void sky2_link_up(struct sky2_port *sky2)
1673 {
1674 struct sky2_hw *hw = sky2->hw;
1675 unsigned port = sky2->port;
1676 u16 reg;
1677 static const char *fc_name[] = {
1678 [FC_NONE] = "none",
1679 [FC_TX] = "tx",
1680 [FC_RX] = "rx",
1681 [FC_BOTH] = "both",
1682 };
1683
1684 /* enable Rx/Tx */
1685 reg = gma_read16(hw, port, GM_GP_CTRL);
1686 reg |= GM_GPCR_RX_ENA | GM_GPCR_TX_ENA;
1687 gma_write16(hw, port, GM_GP_CTRL, reg);
1688
1689 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
1690
1691 netif_carrier_on(sky2->netdev);
1692 netif_wake_queue(sky2->netdev);
1693
1694 /* Turn on link LED */
1695 sky2_write8(hw, SK_REG(port, LNK_LED_REG),
1696 LINKLED_ON | LINKLED_BLINK_OFF | LINKLED_LINKSYNC_OFF);
1697
1698 if (hw->chip_id == CHIP_ID_YUKON_XL
1699 || hw->chip_id == CHIP_ID_YUKON_EC_U
1700 || hw->chip_id == CHIP_ID_YUKON_EX) {
1701 u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
1702 u16 led = PHY_M_LEDC_LOS_CTRL(1); /* link active */
1703
1704 switch(sky2->speed) {
1705 case SPEED_10:
1706 led |= PHY_M_LEDC_INIT_CTRL(7);
1707 break;
1708
1709 case SPEED_100:
1710 led |= PHY_M_LEDC_STA1_CTRL(7);
1711 break;
1712
1713 case SPEED_1000:
1714 led |= PHY_M_LEDC_STA0_CTRL(7);
1715 break;
1716 }
1717
1718 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
1719 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, led);
1720 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
1721 }
1722
1723 if (netif_msg_link(sky2))
1724 printk(KERN_INFO PFX
1725 "%s: Link is up at %d Mbps, %s duplex, flow control %s\n",
1726 sky2->netdev->name, sky2->speed,
1727 sky2->duplex == DUPLEX_FULL ? "full" : "half",
1728 fc_name[sky2->flow_status]);
1729 }
1730
1731 static void sky2_link_down(struct sky2_port *sky2)
1732 {
1733 struct sky2_hw *hw = sky2->hw;
1734 unsigned port = sky2->port;
1735 u16 reg;
1736
1737 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);
1738
1739 reg = gma_read16(hw, port, GM_GP_CTRL);
1740 reg &= ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA);
1741 gma_write16(hw, port, GM_GP_CTRL, reg);
1742
1743 netif_carrier_off(sky2->netdev);
1744 netif_stop_queue(sky2->netdev);
1745
1746 /* Turn on link LED */
1747 sky2_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_OFF);
1748
1749 if (netif_msg_link(sky2))
1750 printk(KERN_INFO PFX "%s: Link is down.\n", sky2->netdev->name);
1751
1752 sky2_phy_init(hw, port);
1753 }
1754
1755 static enum flow_control sky2_flow(int rx, int tx)
1756 {
1757 if (rx)
1758 return tx ? FC_BOTH : FC_RX;
1759 else
1760 return tx ? FC_TX : FC_NONE;
1761 }
1762
1763 static int sky2_autoneg_done(struct sky2_port *sky2, u16 aux)
1764 {
1765 struct sky2_hw *hw = sky2->hw;
1766 unsigned port = sky2->port;
1767 u16 advert, lpa;
1768
1769 advert = gm_phy_read(hw, port, PHY_MARV_AUNE_ADV);
1770 lpa = gm_phy_read(hw, port, PHY_MARV_AUNE_LP);
1771 if (lpa & PHY_M_AN_RF) {
1772 printk(KERN_ERR PFX "%s: remote fault", sky2->netdev->name);
1773 return -1;
1774 }
1775
1776 if (!(aux & PHY_M_PS_SPDUP_RES)) {
1777 printk(KERN_ERR PFX "%s: speed/duplex mismatch",
1778 sky2->netdev->name);
1779 return -1;
1780 }
1781
1782 sky2->speed = sky2_phy_speed(hw, aux);
1783 sky2->duplex = (aux & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
1784
1785 /* Since the pause result bits seem to in different positions on
1786 * different chips. look at registers.
1787 */
1788 if (!sky2_is_copper(hw)) {
1789 /* Shift for bits in fiber PHY */
1790 advert &= ~(ADVERTISE_PAUSE_CAP|ADVERTISE_PAUSE_ASYM);
1791 lpa &= ~(LPA_PAUSE_CAP|LPA_PAUSE_ASYM);
1792
1793 if (advert & ADVERTISE_1000XPAUSE)
1794 advert |= ADVERTISE_PAUSE_CAP;
1795 if (advert & ADVERTISE_1000XPSE_ASYM)
1796 advert |= ADVERTISE_PAUSE_ASYM;
1797 if (lpa & LPA_1000XPAUSE)
1798 lpa |= LPA_PAUSE_CAP;
1799 if (lpa & LPA_1000XPAUSE_ASYM)
1800 lpa |= LPA_PAUSE_ASYM;
1801 }
1802
1803 sky2->flow_status = FC_NONE;
1804 if (advert & ADVERTISE_PAUSE_CAP) {
1805 if (lpa & LPA_PAUSE_CAP)
1806 sky2->flow_status = FC_BOTH;
1807 else if (advert & ADVERTISE_PAUSE_ASYM)
1808 sky2->flow_status = FC_RX;
1809 } else if (advert & ADVERTISE_PAUSE_ASYM) {
1810 if ((lpa & LPA_PAUSE_CAP) && (lpa & LPA_PAUSE_ASYM))
1811 sky2->flow_status = FC_TX;
1812 }
1813
1814 if (sky2->duplex == DUPLEX_HALF && sky2->speed < SPEED_1000
1815 && !(hw->chip_id == CHIP_ID_YUKON_EC_U || hw->chip_id == CHIP_ID_YUKON_EX))
1816 sky2->flow_status = FC_NONE;
1817
1818 if (sky2->flow_status & FC_TX)
1819 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
1820 else
1821 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
1822
1823 return 0;
1824 }
1825
1826 /* Interrupt from PHY */
1827 static void sky2_phy_intr(struct sky2_hw *hw, unsigned port)
1828 {
1829 struct net_device *dev = hw->dev[port];
1830 struct sky2_port *sky2 = netdev_priv(dev);
1831 u16 istatus, phystat;
1832
1833 if (!netif_running(dev))
1834 return;
1835
1836 spin_lock(&sky2->phy_lock);
1837 istatus = gm_phy_read(hw, port, PHY_MARV_INT_STAT);
1838 phystat = gm_phy_read(hw, port, PHY_MARV_PHY_STAT);
1839
1840 if (netif_msg_intr(sky2))
1841 printk(KERN_INFO PFX "%s: phy interrupt status 0x%x 0x%x\n",
1842 sky2->netdev->name, istatus, phystat);
1843
1844 if (sky2->autoneg == AUTONEG_ENABLE && (istatus & PHY_M_IS_AN_COMPL)) {
1845 if (sky2_autoneg_done(sky2, phystat) == 0)
1846 sky2_link_up(sky2);
1847 goto out;
1848 }
1849
1850 if (istatus & PHY_M_IS_LSP_CHANGE)
1851 sky2->speed = sky2_phy_speed(hw, phystat);
1852
1853 if (istatus & PHY_M_IS_DUP_CHANGE)
1854 sky2->duplex =
1855 (phystat & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
1856
1857 if (istatus & PHY_M_IS_LST_CHANGE) {
1858 if (phystat & PHY_M_PS_LINK_UP)
1859 sky2_link_up(sky2);
1860 else
1861 sky2_link_down(sky2);
1862 }
1863 out:
1864 spin_unlock(&sky2->phy_lock);
1865 }
1866
1867 /* Transmit timeout is only called if we are running, carrier is up
1868 * and tx queue is full (stopped).
1869 */
1870 static void sky2_tx_timeout(struct net_device *dev)
1871 {
1872 struct sky2_port *sky2 = netdev_priv(dev);
1873 struct sky2_hw *hw = sky2->hw;
1874
1875 if (netif_msg_timer(sky2))
1876 printk(KERN_ERR PFX "%s: tx timeout\n", dev->name);
1877
1878 printk(KERN_DEBUG PFX "%s: transmit ring %u .. %u report=%u done=%u\n",
1879 dev->name, sky2->tx_cons, sky2->tx_prod,
1880 sky2_read16(hw, sky2->port == 0 ? STAT_TXA1_RIDX : STAT_TXA2_RIDX),
1881 sky2_read16(hw, Q_ADDR(txqaddr[sky2->port], Q_DONE)));
1882
1883 /* can't restart safely under softirq */
1884 schedule_work(&hw->restart_work);
1885 }
1886
1887 static int sky2_change_mtu(struct net_device *dev, int new_mtu)
1888 {
1889 struct sky2_port *sky2 = netdev_priv(dev);
1890 struct sky2_hw *hw = sky2->hw;
1891 unsigned port = sky2->port;
1892 int err;
1893 u16 ctl, mode;
1894 u32 imask;
1895
1896 if (new_mtu < ETH_ZLEN || new_mtu > ETH_JUMBO_MTU)
1897 return -EINVAL;
1898
1899 if (new_mtu > ETH_DATA_LEN && hw->chip_id == CHIP_ID_YUKON_FE)
1900 return -EINVAL;
1901
1902 if (!netif_running(dev)) {
1903 dev->mtu = new_mtu;
1904 return 0;
1905 }
1906
1907 imask = sky2_read32(hw, B0_IMSK);
1908 sky2_write32(hw, B0_IMSK, 0);
1909
1910 dev->trans_start = jiffies; /* prevent tx timeout */
1911 netif_stop_queue(dev);
1912 netif_poll_disable(hw->dev[0]);
1913
1914 synchronize_irq(hw->pdev->irq);
1915
1916 if (hw->chip_id == CHIP_ID_YUKON_EC_U || hw->chip_id == CHIP_ID_YUKON_EX) {
1917 if (new_mtu > ETH_DATA_LEN) {
1918 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
1919 TX_JUMBO_ENA | TX_STFW_DIS);
1920 dev->features &= NETIF_F_TSO | NETIF_F_SG | NETIF_F_IP_CSUM;
1921 } else
1922 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
1923 TX_JUMBO_DIS | TX_STFW_ENA);
1924 }
1925
1926 ctl = gma_read16(hw, port, GM_GP_CTRL);
1927 gma_write16(hw, port, GM_GP_CTRL, ctl & ~GM_GPCR_RX_ENA);
1928 sky2_rx_stop(sky2);
1929 sky2_rx_clean(sky2);
1930
1931 dev->mtu = new_mtu;
1932
1933 mode = DATA_BLIND_VAL(DATA_BLIND_DEF) |
1934 GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
1935
1936 if (dev->mtu > ETH_DATA_LEN)
1937 mode |= GM_SMOD_JUMBO_ENA;
1938
1939 gma_write16(hw, port, GM_SERIAL_MODE, mode);
1940
1941 sky2_write8(hw, RB_ADDR(rxqaddr[port], RB_CTRL), RB_ENA_OP_MD);
1942
1943 err = sky2_rx_start(sky2);
1944 sky2_write32(hw, B0_IMSK, imask);
1945
1946 if (err)
1947 dev_close(dev);
1948 else {
1949 gma_write16(hw, port, GM_GP_CTRL, ctl);
1950
1951 netif_poll_enable(hw->dev[0]);
1952 netif_wake_queue(dev);
1953 }
1954
1955 return err;
1956 }
1957
1958 /* For small just reuse existing skb for next receive */
1959 static struct sk_buff *receive_copy(struct sky2_port *sky2,
1960 const struct rx_ring_info *re,
1961 unsigned length)
1962 {
1963 struct sk_buff *skb;
1964
1965 skb = netdev_alloc_skb(sky2->netdev, length + 2);
1966 if (likely(skb)) {
1967 skb_reserve(skb, 2);
1968 pci_dma_sync_single_for_cpu(sky2->hw->pdev, re->data_addr,
1969 length, PCI_DMA_FROMDEVICE);
1970 skb_copy_from_linear_data(re->skb, skb->data, length);
1971 skb->ip_summed = re->skb->ip_summed;
1972 skb->csum = re->skb->csum;
1973 pci_dma_sync_single_for_device(sky2->hw->pdev, re->data_addr,
1974 length, PCI_DMA_FROMDEVICE);
1975 re->skb->ip_summed = CHECKSUM_NONE;
1976 skb_put(skb, length);
1977 }
1978 return skb;
1979 }
1980
1981 /* Adjust length of skb with fragments to match received data */
1982 static void skb_put_frags(struct sk_buff *skb, unsigned int hdr_space,
1983 unsigned int length)
1984 {
1985 int i, num_frags;
1986 unsigned int size;
1987
1988 /* put header into skb */
1989 size = min(length, hdr_space);
1990 skb->tail += size;
1991 skb->len += size;
1992 length -= size;
1993
1994 num_frags = skb_shinfo(skb)->nr_frags;
1995 for (i = 0; i < num_frags; i++) {
1996 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
1997
1998 if (length == 0) {
1999 /* don't need this page */
2000 __free_page(frag->page);
2001 --skb_shinfo(skb)->nr_frags;
2002 } else {
2003 size = min(length, (unsigned) PAGE_SIZE);
2004
2005 frag->size = size;
2006 skb->data_len += size;
2007 skb->truesize += size;
2008 skb->len += size;
2009 length -= size;
2010 }
2011 }
2012 }
2013
2014 /* Normal packet - take skb from ring element and put in a new one */
2015 static struct sk_buff *receive_new(struct sky2_port *sky2,
2016 struct rx_ring_info *re,
2017 unsigned int length)
2018 {
2019 struct sk_buff *skb, *nskb;
2020 unsigned hdr_space = sky2->rx_data_size;
2021
2022 pr_debug(PFX "receive new length=%d\n", length);
2023
2024 /* Don't be tricky about reusing pages (yet) */
2025 nskb = sky2_rx_alloc(sky2);
2026 if (unlikely(!nskb))
2027 return NULL;
2028
2029 skb = re->skb;
2030 sky2_rx_unmap_skb(sky2->hw->pdev, re);
2031
2032 prefetch(skb->data);
2033 re->skb = nskb;
2034 sky2_rx_map_skb(sky2->hw->pdev, re, hdr_space);
2035
2036 if (skb_shinfo(skb)->nr_frags)
2037 skb_put_frags(skb, hdr_space, length);
2038 else
2039 skb_put(skb, length);
2040 return skb;
2041 }
2042
2043 /*
2044 * Receive one packet.
2045 * For larger packets, get new buffer.
2046 */
2047 static struct sk_buff *sky2_receive(struct net_device *dev,
2048 u16 length, u32 status)
2049 {
2050 struct sky2_port *sky2 = netdev_priv(dev);
2051 struct rx_ring_info *re = sky2->rx_ring + sky2->rx_next;
2052 struct sk_buff *skb = NULL;
2053
2054 if (unlikely(netif_msg_rx_status(sky2)))
2055 printk(KERN_DEBUG PFX "%s: rx slot %u status 0x%x len %d\n",
2056 dev->name, sky2->rx_next, status, length);
2057
2058 sky2->rx_next = (sky2->rx_next + 1) % sky2->rx_pending;
2059 prefetch(sky2->rx_ring + sky2->rx_next);
2060
2061 if (status & GMR_FS_ANY_ERR)
2062 goto error;
2063
2064 if (!(status & GMR_FS_RX_OK))
2065 goto resubmit;
2066
2067 if (length < copybreak)
2068 skb = receive_copy(sky2, re, length);
2069 else
2070 skb = receive_new(sky2, re, length);
2071 resubmit:
2072 sky2_rx_submit(sky2, re);
2073
2074 return skb;
2075
2076 error:
2077 ++sky2->net_stats.rx_errors;
2078 if (status & GMR_FS_RX_FF_OV) {
2079 sky2->net_stats.rx_over_errors++;
2080 goto resubmit;
2081 }
2082
2083 if (netif_msg_rx_err(sky2) && net_ratelimit())
2084 printk(KERN_INFO PFX "%s: rx error, status 0x%x length %d\n",
2085 dev->name, status, length);
2086
2087 if (status & (GMR_FS_LONG_ERR | GMR_FS_UN_SIZE))
2088 sky2->net_stats.rx_length_errors++;
2089 if (status & GMR_FS_FRAGMENT)
2090 sky2->net_stats.rx_frame_errors++;
2091 if (status & GMR_FS_CRC_ERR)
2092 sky2->net_stats.rx_crc_errors++;
2093
2094 goto resubmit;
2095 }
2096
2097 /* Transmit complete */
2098 static inline void sky2_tx_done(struct net_device *dev, u16 last)
2099 {
2100 struct sky2_port *sky2 = netdev_priv(dev);
2101
2102 if (netif_running(dev)) {
2103 netif_tx_lock(dev);
2104 sky2_tx_complete(sky2, last);
2105 netif_tx_unlock(dev);
2106 }
2107 }
2108
2109 /* Process status response ring */
2110 static int sky2_status_intr(struct sky2_hw *hw, int to_do)
2111 {
2112 struct sky2_port *sky2;
2113 int work_done = 0;
2114 unsigned buf_write[2] = { 0, 0 };
2115 u16 hwidx = sky2_read16(hw, STAT_PUT_IDX);
2116
2117 rmb();
2118
2119 while (hw->st_idx != hwidx) {
2120 struct sky2_status_le *le = hw->st_le + hw->st_idx;
2121 struct net_device *dev;
2122 struct sk_buff *skb;
2123 u32 status;
2124 u16 length;
2125
2126 hw->st_idx = RING_NEXT(hw->st_idx, STATUS_RING_SIZE);
2127
2128 BUG_ON(le->link >= 2);
2129 dev = hw->dev[le->link];
2130
2131 sky2 = netdev_priv(dev);
2132 length = le16_to_cpu(le->length);
2133 status = le32_to_cpu(le->status);
2134
2135 switch (le->opcode & ~HW_OWNER) {
2136 case OP_RXSTAT:
2137 skb = sky2_receive(dev, length, status);
2138 if (unlikely(!skb)) {
2139 sky2->net_stats.rx_dropped++;
2140 goto force_update;
2141 }
2142
2143 skb->protocol = eth_type_trans(skb, dev);
2144 sky2->net_stats.rx_packets++;
2145 sky2->net_stats.rx_bytes += skb->len;
2146 dev->last_rx = jiffies;
2147
2148 #ifdef SKY2_VLAN_TAG_USED
2149 if (sky2->vlgrp && (status & GMR_FS_VLAN)) {
2150 vlan_hwaccel_receive_skb(skb,
2151 sky2->vlgrp,
2152 be16_to_cpu(sky2->rx_tag));
2153 } else
2154 #endif
2155 netif_receive_skb(skb);
2156
2157 /* Update receiver after 16 frames */
2158 if (++buf_write[le->link] == RX_BUF_WRITE) {
2159 force_update:
2160 sky2_put_idx(hw, rxqaddr[le->link], sky2->rx_put);
2161 buf_write[le->link] = 0;
2162 }
2163
2164 /* Stop after net poll weight */
2165 if (++work_done >= to_do)
2166 goto exit_loop;
2167 break;
2168
2169 #ifdef SKY2_VLAN_TAG_USED
2170 case OP_RXVLAN:
2171 sky2->rx_tag = length;
2172 break;
2173
2174 case OP_RXCHKSVLAN:
2175 sky2->rx_tag = length;
2176 /* fall through */
2177 #endif
2178 case OP_RXCHKS:
2179 if (!sky2->rx_csum)
2180 break;
2181
2182 /* Both checksum counters are programmed to start at
2183 * the same offset, so unless there is a problem they
2184 * should match. This failure is an early indication that
2185 * hardware receive checksumming won't work.
2186 */
2187 if (likely(status >> 16 == (status & 0xffff))) {
2188 skb = sky2->rx_ring[sky2->rx_next].skb;
2189 skb->ip_summed = CHECKSUM_COMPLETE;
2190 skb->csum = status & 0xffff;
2191 } else {
2192 printk(KERN_NOTICE PFX "%s: hardware receive "
2193 "checksum problem (status = %#x)\n",
2194 dev->name, status);
2195 sky2->rx_csum = 0;
2196 sky2_write32(sky2->hw,
2197 Q_ADDR(rxqaddr[le->link], Q_CSR),
2198 BMU_DIS_RX_CHKSUM);
2199 }
2200 break;
2201
2202 case OP_TXINDEXLE:
2203 /* TX index reports status for both ports */
2204 BUILD_BUG_ON(TX_RING_SIZE > 0x1000);
2205 sky2_tx_done(hw->dev[0], status & 0xfff);
2206 if (hw->dev[1])
2207 sky2_tx_done(hw->dev[1],
2208 ((status >> 24) & 0xff)
2209 | (u16)(length & 0xf) << 8);
2210 break;
2211
2212 default:
2213 if (net_ratelimit())
2214 printk(KERN_WARNING PFX
2215 "unknown status opcode 0x%x\n", le->opcode);
2216 goto exit_loop;
2217 }
2218 }
2219
2220 /* Fully processed status ring so clear irq */
2221 sky2_write32(hw, STAT_CTRL, SC_STAT_CLR_IRQ);
2222 mmiowb();
2223
2224 exit_loop:
2225 if (buf_write[0]) {
2226 sky2 = netdev_priv(hw->dev[0]);
2227 sky2_put_idx(hw, Q_R1, sky2->rx_put);
2228 }
2229
2230 if (buf_write[1]) {
2231 sky2 = netdev_priv(hw->dev[1]);
2232 sky2_put_idx(hw, Q_R2, sky2->rx_put);
2233 }
2234
2235 return work_done;
2236 }
2237
2238 static void sky2_hw_error(struct sky2_hw *hw, unsigned port, u32 status)
2239 {
2240 struct net_device *dev = hw->dev[port];
2241
2242 if (net_ratelimit())
2243 printk(KERN_INFO PFX "%s: hw error interrupt status 0x%x\n",
2244 dev->name, status);
2245
2246 if (status & Y2_IS_PAR_RD1) {
2247 if (net_ratelimit())
2248 printk(KERN_ERR PFX "%s: ram data read parity error\n",
2249 dev->name);
2250 /* Clear IRQ */
2251 sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_RD_PERR);
2252 }
2253
2254 if (status & Y2_IS_PAR_WR1) {
2255 if (net_ratelimit())
2256 printk(KERN_ERR PFX "%s: ram data write parity error\n",
2257 dev->name);
2258
2259 sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_WR_PERR);
2260 }
2261
2262 if (status & Y2_IS_PAR_MAC1) {
2263 if (net_ratelimit())
2264 printk(KERN_ERR PFX "%s: MAC parity error\n", dev->name);
2265 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_PE);
2266 }
2267
2268 if (status & Y2_IS_PAR_RX1) {
2269 if (net_ratelimit())
2270 printk(KERN_ERR PFX "%s: RX parity error\n", dev->name);
2271 sky2_write32(hw, Q_ADDR(rxqaddr[port], Q_CSR), BMU_CLR_IRQ_PAR);
2272 }
2273
2274 if (status & Y2_IS_TCP_TXA1) {
2275 if (net_ratelimit())
2276 printk(KERN_ERR PFX "%s: TCP segmentation error\n",
2277 dev->name);
2278 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_CLR_IRQ_TCP);
2279 }
2280 }
2281
2282 static void sky2_hw_intr(struct sky2_hw *hw)
2283 {
2284 u32 status = sky2_read32(hw, B0_HWE_ISRC);
2285
2286 if (status & Y2_IS_TIST_OV)
2287 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
2288
2289 if (status & (Y2_IS_MST_ERR | Y2_IS_IRQ_STAT)) {
2290 u16 pci_err;
2291
2292 pci_err = sky2_pci_read16(hw, PCI_STATUS);
2293 if (net_ratelimit())
2294 dev_err(&hw->pdev->dev, "PCI hardware error (0x%x)\n",
2295 pci_err);
2296
2297 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
2298 sky2_pci_write16(hw, PCI_STATUS,
2299 pci_err | PCI_STATUS_ERROR_BITS);
2300 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2301 }
2302
2303 if (status & Y2_IS_PCI_EXP) {
2304 /* PCI-Express uncorrectable Error occurred */
2305 u32 pex_err;
2306
2307 pex_err = sky2_pci_read32(hw, PEX_UNC_ERR_STAT);
2308
2309 if (net_ratelimit())
2310 dev_err(&hw->pdev->dev, "PCI Express error (0x%x)\n",
2311 pex_err);
2312
2313 /* clear the interrupt */
2314 sky2_write32(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
2315 sky2_pci_write32(hw, PEX_UNC_ERR_STAT,
2316 0xffffffffUL);
2317 sky2_write32(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2318
2319 if (pex_err & PEX_FATAL_ERRORS) {
2320 u32 hwmsk = sky2_read32(hw, B0_HWE_IMSK);
2321 hwmsk &= ~Y2_IS_PCI_EXP;
2322 sky2_write32(hw, B0_HWE_IMSK, hwmsk);
2323 }
2324 }
2325
2326 if (status & Y2_HWE_L1_MASK)
2327 sky2_hw_error(hw, 0, status);
2328 status >>= 8;
2329 if (status & Y2_HWE_L1_MASK)
2330 sky2_hw_error(hw, 1, status);
2331 }
2332
2333 static void sky2_mac_intr(struct sky2_hw *hw, unsigned port)
2334 {
2335 struct net_device *dev = hw->dev[port];
2336 struct sky2_port *sky2 = netdev_priv(dev);
2337 u8 status = sky2_read8(hw, SK_REG(port, GMAC_IRQ_SRC));
2338
2339 if (netif_msg_intr(sky2))
2340 printk(KERN_INFO PFX "%s: mac interrupt status 0x%x\n",
2341 dev->name, status);
2342
2343 if (status & GM_IS_RX_CO_OV)
2344 gma_read16(hw, port, GM_RX_IRQ_SRC);
2345
2346 if (status & GM_IS_TX_CO_OV)
2347 gma_read16(hw, port, GM_TX_IRQ_SRC);
2348
2349 if (status & GM_IS_RX_FF_OR) {
2350 ++sky2->net_stats.rx_fifo_errors;
2351 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_CLI_RX_FO);
2352 }
2353
2354 if (status & GM_IS_TX_FF_UR) {
2355 ++sky2->net_stats.tx_fifo_errors;
2356 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_FU);
2357 }
2358 }
2359
2360 /* This should never happen it is a bug. */
2361 static void sky2_le_error(struct sky2_hw *hw, unsigned port,
2362 u16 q, unsigned ring_size)
2363 {
2364 struct net_device *dev = hw->dev[port];
2365 struct sky2_port *sky2 = netdev_priv(dev);
2366 unsigned idx;
2367 const u64 *le = (q == Q_R1 || q == Q_R2)
2368 ? (u64 *) sky2->rx_le : (u64 *) sky2->tx_le;
2369
2370 idx = sky2_read16(hw, Y2_QADDR(q, PREF_UNIT_GET_IDX));
2371 printk(KERN_ERR PFX "%s: descriptor error q=%#x get=%u [%llx] put=%u\n",
2372 dev->name, (unsigned) q, idx, (unsigned long long) le[idx],
2373 (unsigned) sky2_read16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX)));
2374
2375 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_CLR_IRQ_CHK);
2376 }
2377
2378 /* If idle then force a fake soft NAPI poll once a second
2379 * to work around cases where sharing an edge triggered interrupt.
2380 */
2381 static inline void sky2_idle_start(struct sky2_hw *hw)
2382 {
2383 if (idle_timeout > 0)
2384 mod_timer(&hw->idle_timer,
2385 jiffies + msecs_to_jiffies(idle_timeout));
2386 }
2387
2388 static void sky2_idle(unsigned long arg)
2389 {
2390 struct sky2_hw *hw = (struct sky2_hw *) arg;
2391 struct net_device *dev = hw->dev[0];
2392
2393 if (__netif_rx_schedule_prep(dev))
2394 __netif_rx_schedule(dev);
2395
2396 mod_timer(&hw->idle_timer, jiffies + msecs_to_jiffies(idle_timeout));
2397 }
2398
2399 /* Hardware/software error handling */
2400 static void sky2_err_intr(struct sky2_hw *hw, u32 status)
2401 {
2402 if (net_ratelimit())
2403 dev_warn(&hw->pdev->dev, "error interrupt status=%#x\n", status);
2404
2405 if (status & Y2_IS_HW_ERR)
2406 sky2_hw_intr(hw);
2407
2408 if (status & Y2_IS_IRQ_MAC1)
2409 sky2_mac_intr(hw, 0);
2410
2411 if (status & Y2_IS_IRQ_MAC2)
2412 sky2_mac_intr(hw, 1);
2413
2414 if (status & Y2_IS_CHK_RX1)
2415 sky2_le_error(hw, 0, Q_R1, RX_LE_SIZE);
2416
2417 if (status & Y2_IS_CHK_RX2)
2418 sky2_le_error(hw, 1, Q_R2, RX_LE_SIZE);
2419
2420 if (status & Y2_IS_CHK_TXA1)
2421 sky2_le_error(hw, 0, Q_XA1, TX_RING_SIZE);
2422
2423 if (status & Y2_IS_CHK_TXA2)
2424 sky2_le_error(hw, 1, Q_XA2, TX_RING_SIZE);
2425 }
2426
2427 static int sky2_poll(struct net_device *dev0, int *budget)
2428 {
2429 struct sky2_hw *hw = ((struct sky2_port *) netdev_priv(dev0))->hw;
2430 int work_limit = min(dev0->quota, *budget);
2431 int work_done = 0;
2432 u32 status = sky2_read32(hw, B0_Y2_SP_EISR);
2433
2434 if (unlikely(status & Y2_IS_ERROR))
2435 sky2_err_intr(hw, status);
2436
2437 if (status & Y2_IS_IRQ_PHY1)
2438 sky2_phy_intr(hw, 0);
2439
2440 if (status & Y2_IS_IRQ_PHY2)
2441 sky2_phy_intr(hw, 1);
2442
2443 work_done = sky2_status_intr(hw, work_limit);
2444 if (work_done < work_limit) {
2445 netif_rx_complete(dev0);
2446
2447 /* end of interrupt, re-enables also acts as I/O synchronization */
2448 sky2_read32(hw, B0_Y2_SP_LISR);
2449 return 0;
2450 } else {
2451 *budget -= work_done;
2452 dev0->quota -= work_done;
2453 return 1;
2454 }
2455 }
2456
2457 static irqreturn_t sky2_intr(int irq, void *dev_id)
2458 {
2459 struct sky2_hw *hw = dev_id;
2460 struct net_device *dev0 = hw->dev[0];
2461 u32 status;
2462
2463 /* Reading this mask interrupts as side effect */
2464 status = sky2_read32(hw, B0_Y2_SP_ISRC2);
2465 if (status == 0 || status == ~0)
2466 return IRQ_NONE;
2467
2468 prefetch(&hw->st_le[hw->st_idx]);
2469 if (likely(__netif_rx_schedule_prep(dev0)))
2470 __netif_rx_schedule(dev0);
2471
2472 return IRQ_HANDLED;
2473 }
2474
2475 #ifdef CONFIG_NET_POLL_CONTROLLER
2476 static void sky2_netpoll(struct net_device *dev)
2477 {
2478 struct sky2_port *sky2 = netdev_priv(dev);
2479 struct net_device *dev0 = sky2->hw->dev[0];
2480
2481 if (netif_running(dev) && __netif_rx_schedule_prep(dev0))
2482 __netif_rx_schedule(dev0);
2483 }
2484 #endif
2485
2486 /* Chip internal frequency for clock calculations */
2487 static inline u32 sky2_mhz(const struct sky2_hw *hw)
2488 {
2489 switch (hw->chip_id) {
2490 case CHIP_ID_YUKON_EC:
2491 case CHIP_ID_YUKON_EC_U:
2492 case CHIP_ID_YUKON_EX:
2493 return 125; /* 125 Mhz */
2494 case CHIP_ID_YUKON_FE:
2495 return 100; /* 100 Mhz */
2496 default: /* YUKON_XL */
2497 return 156; /* 156 Mhz */
2498 }
2499 }
2500
2501 static inline u32 sky2_us2clk(const struct sky2_hw *hw, u32 us)
2502 {
2503 return sky2_mhz(hw) * us;
2504 }
2505
2506 static inline u32 sky2_clk2us(const struct sky2_hw *hw, u32 clk)
2507 {
2508 return clk / sky2_mhz(hw);
2509 }
2510
2511
2512 static int __devinit sky2_init(struct sky2_hw *hw)
2513 {
2514 u8 t8;
2515
2516 sky2_write8(hw, B0_CTST, CS_RST_CLR);
2517
2518 hw->chip_id = sky2_read8(hw, B2_CHIP_ID);
2519 if (hw->chip_id < CHIP_ID_YUKON_XL || hw->chip_id > CHIP_ID_YUKON_FE) {
2520 dev_err(&hw->pdev->dev, "unsupported chip type 0x%x\n",
2521 hw->chip_id);
2522 return -EOPNOTSUPP;
2523 }
2524
2525 if (hw->chip_id == CHIP_ID_YUKON_EX)
2526 dev_warn(&hw->pdev->dev, "this driver not yet tested on this chip type\n"
2527 "Please report success or failure to <netdev@vger.kernel.org>\n");
2528
2529 /* Make sure and enable all clocks */
2530 if (hw->chip_id == CHIP_ID_YUKON_EX || hw->chip_id == CHIP_ID_YUKON_EC_U)
2531 sky2_pci_write32(hw, PCI_DEV_REG3, 0);
2532
2533 hw->chip_rev = (sky2_read8(hw, B2_MAC_CFG) & CFG_CHIP_R_MSK) >> 4;
2534
2535 /* This rev is really old, and requires untested workarounds */
2536 if (hw->chip_id == CHIP_ID_YUKON_EC && hw->chip_rev == CHIP_REV_YU_EC_A1) {
2537 dev_err(&hw->pdev->dev, "unsupported revision Yukon-%s (0x%x) rev %d\n",
2538 yukon2_name[hw->chip_id - CHIP_ID_YUKON_XL],
2539 hw->chip_id, hw->chip_rev);
2540 return -EOPNOTSUPP;
2541 }
2542
2543 hw->pmd_type = sky2_read8(hw, B2_PMD_TYP);
2544 hw->ports = 1;
2545 t8 = sky2_read8(hw, B2_Y2_HW_RES);
2546 if ((t8 & CFG_DUAL_MAC_MSK) == CFG_DUAL_MAC_MSK) {
2547 if (!(sky2_read8(hw, B2_Y2_CLK_GATE) & Y2_STATUS_LNK2_INAC))
2548 ++hw->ports;
2549 }
2550
2551 return 0;
2552 }
2553
2554 static void sky2_reset(struct sky2_hw *hw)
2555 {
2556 u16 status;
2557 int i;
2558
2559 /* disable ASF */
2560 if (hw->chip_id == CHIP_ID_YUKON_EX) {
2561 status = sky2_read16(hw, HCU_CCSR);
2562 status &= ~(HCU_CCSR_AHB_RST | HCU_CCSR_CPU_RST_MODE |
2563 HCU_CCSR_UC_STATE_MSK);
2564 sky2_write16(hw, HCU_CCSR, status);
2565 } else
2566 sky2_write8(hw, B28_Y2_ASF_STAT_CMD, Y2_ASF_RESET);
2567 sky2_write16(hw, B0_CTST, Y2_ASF_DISABLE);
2568
2569 /* do a SW reset */
2570 sky2_write8(hw, B0_CTST, CS_RST_SET);
2571 sky2_write8(hw, B0_CTST, CS_RST_CLR);
2572
2573 /* clear PCI errors, if any */
2574 status = sky2_pci_read16(hw, PCI_STATUS);
2575
2576 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
2577 sky2_pci_write16(hw, PCI_STATUS, status | PCI_STATUS_ERROR_BITS);
2578
2579
2580 sky2_write8(hw, B0_CTST, CS_MRST_CLR);
2581
2582 /* clear any PEX errors */
2583 if (pci_find_capability(hw->pdev, PCI_CAP_ID_EXP))
2584 sky2_pci_write32(hw, PEX_UNC_ERR_STAT, 0xffffffffUL);
2585
2586
2587 sky2_power_on(hw);
2588
2589 for (i = 0; i < hw->ports; i++) {
2590 sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_SET);
2591 sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_CLR);
2592 }
2593
2594 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2595
2596 /* Clear I2C IRQ noise */
2597 sky2_write32(hw, B2_I2C_IRQ, 1);
2598
2599 /* turn off hardware timer (unused) */
2600 sky2_write8(hw, B2_TI_CTRL, TIM_STOP);
2601 sky2_write8(hw, B2_TI_CTRL, TIM_CLR_IRQ);
2602
2603 sky2_write8(hw, B0_Y2LED, LED_STAT_ON);
2604
2605 /* Turn off descriptor polling */
2606 sky2_write32(hw, B28_DPT_CTRL, DPT_STOP);
2607
2608 /* Turn off receive timestamp */
2609 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_STOP);
2610 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
2611
2612 /* enable the Tx Arbiters */
2613 for (i = 0; i < hw->ports; i++)
2614 sky2_write8(hw, SK_REG(i, TXA_CTRL), TXA_ENA_ARB);
2615
2616 /* Initialize ram interface */
2617 for (i = 0; i < hw->ports; i++) {
2618 sky2_write8(hw, RAM_BUFFER(i, B3_RI_CTRL), RI_RST_CLR);
2619
2620 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R1), SK_RI_TO_53);
2621 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA1), SK_RI_TO_53);
2622 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS1), SK_RI_TO_53);
2623 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R1), SK_RI_TO_53);
2624 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA1), SK_RI_TO_53);
2625 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS1), SK_RI_TO_53);
2626 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R2), SK_RI_TO_53);
2627 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA2), SK_RI_TO_53);
2628 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS2), SK_RI_TO_53);
2629 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R2), SK_RI_TO_53);
2630 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA2), SK_RI_TO_53);
2631 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS2), SK_RI_TO_53);
2632 }
2633
2634 sky2_write32(hw, B0_HWE_IMSK, Y2_HWE_ALL_MASK);
2635
2636 for (i = 0; i < hw->ports; i++)
2637 sky2_gmac_reset(hw, i);
2638
2639 memset(hw->st_le, 0, STATUS_LE_BYTES);
2640 hw->st_idx = 0;
2641
2642 sky2_write32(hw, STAT_CTRL, SC_STAT_RST_SET);
2643 sky2_write32(hw, STAT_CTRL, SC_STAT_RST_CLR);
2644
2645 sky2_write32(hw, STAT_LIST_ADDR_LO, hw->st_dma);
2646 sky2_write32(hw, STAT_LIST_ADDR_HI, (u64) hw->st_dma >> 32);
2647
2648 /* Set the list last index */
2649 sky2_write16(hw, STAT_LAST_IDX, STATUS_RING_SIZE - 1);
2650
2651 sky2_write16(hw, STAT_TX_IDX_TH, 10);
2652 sky2_write8(hw, STAT_FIFO_WM, 16);
2653
2654 /* set Status-FIFO ISR watermark */
2655 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0)
2656 sky2_write8(hw, STAT_FIFO_ISR_WM, 4);
2657 else
2658 sky2_write8(hw, STAT_FIFO_ISR_WM, 16);
2659
2660 sky2_write32(hw, STAT_TX_TIMER_INI, sky2_us2clk(hw, 1000));
2661 sky2_write32(hw, STAT_ISR_TIMER_INI, sky2_us2clk(hw, 20));
2662 sky2_write32(hw, STAT_LEV_TIMER_INI, sky2_us2clk(hw, 100));
2663
2664 /* enable status unit */
2665 sky2_write32(hw, STAT_CTRL, SC_STAT_OP_ON);
2666
2667 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
2668 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);
2669 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START);
2670 }
2671
2672 static void sky2_restart(struct work_struct *work)
2673 {
2674 struct sky2_hw *hw = container_of(work, struct sky2_hw, restart_work);
2675 struct net_device *dev;
2676 int i, err;
2677
2678 dev_dbg(&hw->pdev->dev, "restarting\n");
2679
2680 del_timer_sync(&hw->idle_timer);
2681
2682 rtnl_lock();
2683 sky2_write32(hw, B0_IMSK, 0);
2684 sky2_read32(hw, B0_IMSK);
2685
2686 netif_poll_disable(hw->dev[0]);
2687
2688 for (i = 0; i < hw->ports; i++) {
2689 dev = hw->dev[i];
2690 if (netif_running(dev))
2691 sky2_down(dev);
2692 }
2693
2694 sky2_reset(hw);
2695 sky2_write32(hw, B0_IMSK, Y2_IS_BASE);
2696 netif_poll_enable(hw->dev[0]);
2697
2698 for (i = 0; i < hw->ports; i++) {
2699 dev = hw->dev[i];
2700 if (netif_running(dev)) {
2701 err = sky2_up(dev);
2702 if (err) {
2703 printk(KERN_INFO PFX "%s: could not restart %d\n",
2704 dev->name, err);
2705 dev_close(dev);
2706 }
2707 }
2708 }
2709
2710 sky2_idle_start(hw);
2711
2712 rtnl_unlock();
2713 }
2714
2715 static inline u8 sky2_wol_supported(const struct sky2_hw *hw)
2716 {
2717 return sky2_is_copper(hw) ? (WAKE_PHY | WAKE_MAGIC) : 0;
2718 }
2719
2720 static void sky2_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
2721 {
2722 const struct sky2_port *sky2 = netdev_priv(dev);
2723
2724 wol->supported = sky2_wol_supported(sky2->hw);
2725 wol->wolopts = sky2->wol;
2726 }
2727
2728 static int sky2_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
2729 {
2730 struct sky2_port *sky2 = netdev_priv(dev);
2731 struct sky2_hw *hw = sky2->hw;
2732
2733 if (wol->wolopts & ~sky2_wol_supported(sky2->hw))
2734 return -EOPNOTSUPP;
2735
2736 sky2->wol = wol->wolopts;
2737
2738 if (hw->chip_id == CHIP_ID_YUKON_EC_U)
2739 sky2_write32(hw, B0_CTST, sky2->wol
2740 ? Y2_HW_WOL_ON : Y2_HW_WOL_OFF);
2741
2742 if (!netif_running(dev))
2743 sky2_wol_init(sky2);
2744 return 0;
2745 }
2746
2747 static u32 sky2_supported_modes(const struct sky2_hw *hw)
2748 {
2749 if (sky2_is_copper(hw)) {
2750 u32 modes = SUPPORTED_10baseT_Half
2751 | SUPPORTED_10baseT_Full
2752 | SUPPORTED_100baseT_Half
2753 | SUPPORTED_100baseT_Full
2754 | SUPPORTED_Autoneg | SUPPORTED_TP;
2755
2756 if (hw->chip_id != CHIP_ID_YUKON_FE)
2757 modes |= SUPPORTED_1000baseT_Half
2758 | SUPPORTED_1000baseT_Full;
2759 return modes;
2760 } else
2761 return SUPPORTED_1000baseT_Half
2762 | SUPPORTED_1000baseT_Full
2763 | SUPPORTED_Autoneg
2764 | SUPPORTED_FIBRE;
2765 }
2766
2767 static int sky2_get_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
2768 {
2769 struct sky2_port *sky2 = netdev_priv(dev);
2770 struct sky2_hw *hw = sky2->hw;
2771
2772 ecmd->transceiver = XCVR_INTERNAL;
2773 ecmd->supported = sky2_supported_modes(hw);
2774 ecmd->phy_address = PHY_ADDR_MARV;
2775 if (sky2_is_copper(hw)) {
2776 ecmd->supported = SUPPORTED_10baseT_Half
2777 | SUPPORTED_10baseT_Full
2778 | SUPPORTED_100baseT_Half
2779 | SUPPORTED_100baseT_Full
2780 | SUPPORTED_1000baseT_Half
2781 | SUPPORTED_1000baseT_Full
2782 | SUPPORTED_Autoneg | SUPPORTED_TP;
2783 ecmd->port = PORT_TP;
2784 ecmd->speed = sky2->speed;
2785 } else {
2786 ecmd->speed = SPEED_1000;
2787 ecmd->port = PORT_FIBRE;
2788 }
2789
2790 ecmd->advertising = sky2->advertising;
2791 ecmd->autoneg = sky2->autoneg;
2792 ecmd->duplex = sky2->duplex;
2793 return 0;
2794 }
2795
2796 static int sky2_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
2797 {
2798 struct sky2_port *sky2 = netdev_priv(dev);
2799 const struct sky2_hw *hw = sky2->hw;
2800 u32 supported = sky2_supported_modes(hw);
2801
2802 if (ecmd->autoneg == AUTONEG_ENABLE) {
2803 ecmd->advertising = supported;
2804 sky2->duplex = -1;
2805 sky2->speed = -1;
2806 } else {
2807 u32 setting;
2808
2809 switch (ecmd->speed) {
2810 case SPEED_1000:
2811 if (ecmd->duplex == DUPLEX_FULL)
2812 setting = SUPPORTED_1000baseT_Full;
2813 else if (ecmd->duplex == DUPLEX_HALF)
2814 setting = SUPPORTED_1000baseT_Half;
2815 else
2816 return -EINVAL;
2817 break;
2818 case SPEED_100:
2819 if (ecmd->duplex == DUPLEX_FULL)
2820 setting = SUPPORTED_100baseT_Full;
2821 else if (ecmd->duplex == DUPLEX_HALF)
2822 setting = SUPPORTED_100baseT_Half;
2823 else
2824 return -EINVAL;
2825 break;
2826
2827 case SPEED_10:
2828 if (ecmd->duplex == DUPLEX_FULL)
2829 setting = SUPPORTED_10baseT_Full;
2830 else if (ecmd->duplex == DUPLEX_HALF)
2831 setting = SUPPORTED_10baseT_Half;
2832 else
2833 return -EINVAL;
2834 break;
2835 default:
2836 return -EINVAL;
2837 }
2838
2839 if ((setting & supported) == 0)
2840 return -EINVAL;
2841
2842 sky2->speed = ecmd->speed;
2843 sky2->duplex = ecmd->duplex;
2844 }
2845
2846 sky2->autoneg = ecmd->autoneg;
2847 sky2->advertising = ecmd->advertising;
2848
2849 if (netif_running(dev))
2850 sky2_phy_reinit(sky2);
2851
2852 return 0;
2853 }
2854
2855 static void sky2_get_drvinfo(struct net_device *dev,
2856 struct ethtool_drvinfo *info)
2857 {
2858 struct sky2_port *sky2 = netdev_priv(dev);
2859
2860 strcpy(info->driver, DRV_NAME);
2861 strcpy(info->version, DRV_VERSION);
2862 strcpy(info->fw_version, "N/A");
2863 strcpy(info->bus_info, pci_name(sky2->hw->pdev));
2864 }
2865
2866 static const struct sky2_stat {
2867 char name[ETH_GSTRING_LEN];
2868 u16 offset;
2869 } sky2_stats[] = {
2870 { "tx_bytes", GM_TXO_OK_HI },
2871 { "rx_bytes", GM_RXO_OK_HI },
2872 { "tx_broadcast", GM_TXF_BC_OK },
2873 { "rx_broadcast", GM_RXF_BC_OK },
2874 { "tx_multicast", GM_TXF_MC_OK },
2875 { "rx_multicast", GM_RXF_MC_OK },
2876 { "tx_unicast", GM_TXF_UC_OK },
2877 { "rx_unicast", GM_RXF_UC_OK },
2878 { "tx_mac_pause", GM_TXF_MPAUSE },
2879 { "rx_mac_pause", GM_RXF_MPAUSE },
2880 { "collisions", GM_TXF_COL },
2881 { "late_collision",GM_TXF_LAT_COL },
2882 { "aborted", GM_TXF_ABO_COL },
2883 { "single_collisions", GM_TXF_SNG_COL },
2884 { "multi_collisions", GM_TXF_MUL_COL },
2885
2886 { "rx_short", GM_RXF_SHT },
2887 { "rx_runt", GM_RXE_FRAG },
2888 { "rx_64_byte_packets", GM_RXF_64B },
2889 { "rx_65_to_127_byte_packets", GM_RXF_127B },
2890 { "rx_128_to_255_byte_packets", GM_RXF_255B },
2891 { "rx_256_to_511_byte_packets", GM_RXF_511B },
2892 { "rx_512_to_1023_byte_packets", GM_RXF_1023B },
2893 { "rx_1024_to_1518_byte_packets", GM_RXF_1518B },
2894 { "rx_1518_to_max_byte_packets", GM_RXF_MAX_SZ },
2895 { "rx_too_long", GM_RXF_LNG_ERR },
2896 { "rx_fifo_overflow", GM_RXE_FIFO_OV },
2897 { "rx_jabber", GM_RXF_JAB_PKT },
2898 { "rx_fcs_error", GM_RXF_FCS_ERR },
2899
2900 { "tx_64_byte_packets", GM_TXF_64B },
2901 { "tx_65_to_127_byte_packets", GM_TXF_127B },
2902 { "tx_128_to_255_byte_packets", GM_TXF_255B },
2903 { "tx_256_to_511_byte_packets", GM_TXF_511B },
2904 { "tx_512_to_1023_byte_packets", GM_TXF_1023B },
2905 { "tx_1024_to_1518_byte_packets", GM_TXF_1518B },
2906 { "tx_1519_to_max_byte_packets", GM_TXF_MAX_SZ },
2907 { "tx_fifo_underrun", GM_TXE_FIFO_UR },
2908 };
2909
2910 static u32 sky2_get_rx_csum(struct net_device *dev)
2911 {
2912 struct sky2_port *sky2 = netdev_priv(dev);
2913
2914 return sky2->rx_csum;
2915 }
2916
2917 static int sky2_set_rx_csum(struct net_device *dev, u32 data)
2918 {
2919 struct sky2_port *sky2 = netdev_priv(dev);
2920
2921 sky2->rx_csum = data;
2922
2923 sky2_write32(sky2->hw, Q_ADDR(rxqaddr[sky2->port], Q_CSR),
2924 data ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);
2925
2926 return 0;
2927 }
2928
2929 static u32 sky2_get_msglevel(struct net_device *netdev)
2930 {
2931 struct sky2_port *sky2 = netdev_priv(netdev);
2932 return sky2->msg_enable;
2933 }
2934
2935 static int sky2_nway_reset(struct net_device *dev)
2936 {
2937 struct sky2_port *sky2 = netdev_priv(dev);
2938
2939 if (!netif_running(dev) || sky2->autoneg != AUTONEG_ENABLE)
2940 return -EINVAL;
2941
2942 sky2_phy_reinit(sky2);
2943
2944 return 0;
2945 }
2946
2947 static void sky2_phy_stats(struct sky2_port *sky2, u64 * data, unsigned count)
2948 {
2949 struct sky2_hw *hw = sky2->hw;
2950 unsigned port = sky2->port;
2951 int i;
2952
2953 data[0] = (u64) gma_read32(hw, port, GM_TXO_OK_HI) << 32
2954 | (u64) gma_read32(hw, port, GM_TXO_OK_LO);
2955 data[1] = (u64) gma_read32(hw, port, GM_RXO_OK_HI) << 32
2956 | (u64) gma_read32(hw, port, GM_RXO_OK_LO);
2957
2958 for (i = 2; i < count; i++)
2959 data[i] = (u64) gma_read32(hw, port, sky2_stats[i].offset);
2960 }
2961
2962 static void sky2_set_msglevel(struct net_device *netdev, u32 value)
2963 {
2964 struct sky2_port *sky2 = netdev_priv(netdev);
2965 sky2->msg_enable = value;
2966 }
2967
2968 static int sky2_get_stats_count(struct net_device *dev)
2969 {
2970 return ARRAY_SIZE(sky2_stats);
2971 }
2972
2973 static void sky2_get_ethtool_stats(struct net_device *dev,
2974 struct ethtool_stats *stats, u64 * data)
2975 {
2976 struct sky2_port *sky2 = netdev_priv(dev);
2977
2978 sky2_phy_stats(sky2, data, ARRAY_SIZE(sky2_stats));
2979 }
2980
2981 static void sky2_get_strings(struct net_device *dev, u32 stringset, u8 * data)
2982 {
2983 int i;
2984
2985 switch (stringset) {
2986 case ETH_SS_STATS:
2987 for (i = 0; i < ARRAY_SIZE(sky2_stats); i++)
2988 memcpy(data + i * ETH_GSTRING_LEN,
2989 sky2_stats[i].name, ETH_GSTRING_LEN);
2990 break;
2991 }
2992 }
2993
2994 static struct net_device_stats *sky2_get_stats(struct net_device *dev)
2995 {
2996 struct sky2_port *sky2 = netdev_priv(dev);
2997 return &sky2->net_stats;
2998 }
2999
3000 static int sky2_set_mac_address(struct net_device *dev, void *p)
3001 {
3002 struct sky2_port *sky2 = netdev_priv(dev);
3003 struct sky2_hw *hw = sky2->hw;
3004 unsigned port = sky2->port;
3005 const struct sockaddr *addr = p;
3006
3007 if (!is_valid_ether_addr(addr->sa_data))
3008 return -EADDRNOTAVAIL;
3009
3010 memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN);
3011 memcpy_toio(hw->regs + B2_MAC_1 + port * 8,
3012 dev->dev_addr, ETH_ALEN);
3013 memcpy_toio(hw->regs + B2_MAC_2 + port * 8,
3014 dev->dev_addr, ETH_ALEN);
3015
3016 /* virtual address for data */
3017 gma_set_addr(hw, port, GM_SRC_ADDR_2L, dev->dev_addr);
3018
3019 /* physical address: used for pause frames */
3020 gma_set_addr(hw, port, GM_SRC_ADDR_1L, dev->dev_addr);
3021
3022 return 0;
3023 }
3024
3025 static void inline sky2_add_filter(u8 filter[8], const u8 *addr)
3026 {
3027 u32 bit;
3028
3029 bit = ether_crc(ETH_ALEN, addr) & 63;
3030 filter[bit >> 3] |= 1 << (bit & 7);
3031 }
3032
3033 static void sky2_set_multicast(struct net_device *dev)
3034 {
3035 struct sky2_port *sky2 = netdev_priv(dev);
3036 struct sky2_hw *hw = sky2->hw;
3037 unsigned port = sky2->port;
3038 struct dev_mc_list *list = dev->mc_list;
3039 u16 reg;
3040 u8 filter[8];
3041 int rx_pause;
3042 static const u8 pause_mc_addr[ETH_ALEN] = { 0x1, 0x80, 0xc2, 0x0, 0x0, 0x1 };
3043
3044 rx_pause = (sky2->flow_status == FC_RX || sky2->flow_status == FC_BOTH);
3045 memset(filter, 0, sizeof(filter));
3046
3047 reg = gma_read16(hw, port, GM_RX_CTRL);
3048 reg |= GM_RXCR_UCF_ENA;
3049
3050 if (dev->flags & IFF_PROMISC) /* promiscuous */
3051 reg &= ~(GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);
3052 else if (dev->flags & IFF_ALLMULTI)
3053 memset(filter, 0xff, sizeof(filter));
3054 else if (dev->mc_count == 0 && !rx_pause)
3055 reg &= ~GM_RXCR_MCF_ENA;
3056 else {
3057 int i;
3058 reg |= GM_RXCR_MCF_ENA;
3059
3060 if (rx_pause)
3061 sky2_add_filter(filter, pause_mc_addr);
3062
3063 for (i = 0; list && i < dev->mc_count; i++, list = list->next)
3064 sky2_add_filter(filter, list->dmi_addr);
3065 }
3066
3067 gma_write16(hw, port, GM_MC_ADDR_H1,
3068 (u16) filter[0] | ((u16) filter[1] << 8));
3069 gma_write16(hw, port, GM_MC_ADDR_H2,
3070 (u16) filter[2] | ((u16) filter[3] << 8));
3071 gma_write16(hw, port, GM_MC_ADDR_H3,
3072 (u16) filter[4] | ((u16) filter[5] << 8));
3073 gma_write16(hw, port, GM_MC_ADDR_H4,
3074 (u16) filter[6] | ((u16) filter[7] << 8));
3075
3076 gma_write16(hw, port, GM_RX_CTRL, reg);
3077 }
3078
3079 /* Can have one global because blinking is controlled by
3080 * ethtool and that is always under RTNL mutex
3081 */
3082 static void sky2_led(struct sky2_hw *hw, unsigned port, int on)
3083 {
3084 u16 pg;
3085
3086 switch (hw->chip_id) {
3087 case CHIP_ID_YUKON_XL:
3088 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
3089 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
3090 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
3091 on ? (PHY_M_LEDC_LOS_CTRL(1) |
3092 PHY_M_LEDC_INIT_CTRL(7) |
3093 PHY_M_LEDC_STA1_CTRL(7) |
3094 PHY_M_LEDC_STA0_CTRL(7))
3095 : 0);
3096
3097 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
3098 break;
3099
3100 default:
3101 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, 0);
3102 gm_phy_write(hw, port, PHY_MARV_LED_OVER,
3103 on ? PHY_M_LED_ALL : 0);
3104 }
3105 }
3106
3107 /* blink LED's for finding board */
3108 static int sky2_phys_id(struct net_device *dev, u32 data)
3109 {
3110 struct sky2_port *sky2 = netdev_priv(dev);
3111 struct sky2_hw *hw = sky2->hw;
3112 unsigned port = sky2->port;
3113 u16 ledctrl, ledover = 0;
3114 long ms;
3115 int interrupted;
3116 int onoff = 1;
3117
3118 if (!data || data > (u32) (MAX_SCHEDULE_TIMEOUT / HZ))
3119 ms = jiffies_to_msecs(MAX_SCHEDULE_TIMEOUT);
3120 else
3121 ms = data * 1000;
3122
3123 /* save initial values */
3124 spin_lock_bh(&sky2->phy_lock);
3125 if (hw->chip_id == CHIP_ID_YUKON_XL) {
3126 u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
3127 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
3128 ledctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
3129 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
3130 } else {
3131 ledctrl = gm_phy_read(hw, port, PHY_MARV_LED_CTRL);
3132 ledover = gm_phy_read(hw, port, PHY_MARV_LED_OVER);
3133 }
3134
3135 interrupted = 0;
3136 while (!interrupted && ms > 0) {
3137 sky2_led(hw, port, onoff);
3138 onoff = !onoff;
3139
3140 spin_unlock_bh(&sky2->phy_lock);
3141 interrupted = msleep_interruptible(250);
3142 spin_lock_bh(&sky2->phy_lock);
3143
3144 ms -= 250;
3145 }
3146
3147 /* resume regularly scheduled programming */
3148 if (hw->chip_id == CHIP_ID_YUKON_XL) {
3149 u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
3150 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
3151 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ledctrl);
3152 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
3153 } else {
3154 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl);
3155 gm_phy_write(hw, port, PHY_MARV_LED_OVER, ledover);
3156 }
3157 spin_unlock_bh(&sky2->phy_lock);
3158
3159 return 0;
3160 }
3161
3162 static void sky2_get_pauseparam(struct net_device *dev,
3163 struct ethtool_pauseparam *ecmd)
3164 {
3165 struct sky2_port *sky2 = netdev_priv(dev);
3166
3167 switch (sky2->flow_mode) {
3168 case FC_NONE:
3169 ecmd->tx_pause = ecmd->rx_pause = 0;
3170 break;
3171 case FC_TX:
3172 ecmd->tx_pause = 1, ecmd->rx_pause = 0;
3173 break;
3174 case FC_RX:
3175 ecmd->tx_pause = 0, ecmd->rx_pause = 1;
3176 break;
3177 case FC_BOTH:
3178 ecmd->tx_pause = ecmd->rx_pause = 1;
3179 }
3180
3181 ecmd->autoneg = sky2->autoneg;
3182 }
3183
3184 static int sky2_set_pauseparam(struct net_device *dev,
3185 struct ethtool_pauseparam *ecmd)
3186 {
3187 struct sky2_port *sky2 = netdev_priv(dev);
3188
3189 sky2->autoneg = ecmd->autoneg;
3190 sky2->flow_mode = sky2_flow(ecmd->rx_pause, ecmd->tx_pause);
3191
3192 if (netif_running(dev))
3193 sky2_phy_reinit(sky2);
3194
3195 return 0;
3196 }
3197
3198 static int sky2_get_coalesce(struct net_device *dev,
3199 struct ethtool_coalesce *ecmd)
3200 {
3201 struct sky2_port *sky2 = netdev_priv(dev);
3202 struct sky2_hw *hw = sky2->hw;
3203
3204 if (sky2_read8(hw, STAT_TX_TIMER_CTRL) == TIM_STOP)
3205 ecmd->tx_coalesce_usecs = 0;
3206 else {
3207 u32 clks = sky2_read32(hw, STAT_TX_TIMER_INI);
3208 ecmd->tx_coalesce_usecs = sky2_clk2us(hw, clks);
3209 }
3210 ecmd->tx_max_coalesced_frames = sky2_read16(hw, STAT_TX_IDX_TH);
3211
3212 if (sky2_read8(hw, STAT_LEV_TIMER_CTRL) == TIM_STOP)
3213 ecmd->rx_coalesce_usecs = 0;
3214 else {
3215 u32 clks = sky2_read32(hw, STAT_LEV_TIMER_INI);
3216 ecmd->rx_coalesce_usecs = sky2_clk2us(hw, clks);
3217 }
3218 ecmd->rx_max_coalesced_frames = sky2_read8(hw, STAT_FIFO_WM);
3219
3220 if (sky2_read8(hw, STAT_ISR_TIMER_CTRL) == TIM_STOP)
3221 ecmd->rx_coalesce_usecs_irq = 0;
3222 else {
3223 u32 clks = sky2_read32(hw, STAT_ISR_TIMER_INI);
3224 ecmd->rx_coalesce_usecs_irq = sky2_clk2us(hw, clks);
3225 }
3226
3227 ecmd->rx_max_coalesced_frames_irq = sky2_read8(hw, STAT_FIFO_ISR_WM);
3228
3229 return 0;
3230 }
3231
3232 /* Note: this affect both ports */
3233 static int sky2_set_coalesce(struct net_device *dev,
3234 struct ethtool_coalesce *ecmd)
3235 {
3236 struct sky2_port *sky2 = netdev_priv(dev);
3237 struct sky2_hw *hw = sky2->hw;
3238 const u32 tmax = sky2_clk2us(hw, 0x0ffffff);
3239
3240 if (ecmd->tx_coalesce_usecs > tmax ||
3241 ecmd->rx_coalesce_usecs > tmax ||
3242 ecmd->rx_coalesce_usecs_irq > tmax)
3243 return -EINVAL;
3244
3245 if (ecmd->tx_max_coalesced_frames >= TX_RING_SIZE-1)
3246 return -EINVAL;
3247 if (ecmd->rx_max_coalesced_frames > RX_MAX_PENDING)
3248 return -EINVAL;
3249 if (ecmd->rx_max_coalesced_frames_irq >RX_MAX_PENDING)
3250 return -EINVAL;
3251
3252 if (ecmd->tx_coalesce_usecs == 0)
3253 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_STOP);
3254 else {
3255 sky2_write32(hw, STAT_TX_TIMER_INI,
3256 sky2_us2clk(hw, ecmd->tx_coalesce_usecs));
3257 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
3258 }
3259 sky2_write16(hw, STAT_TX_IDX_TH, ecmd->tx_max_coalesced_frames);
3260
3261 if (ecmd->rx_coalesce_usecs == 0)
3262 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_STOP);
3263 else {
3264 sky2_write32(hw, STAT_LEV_TIMER_INI,
3265 sky2_us2clk(hw, ecmd->rx_coalesce_usecs));
3266 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);
3267 }
3268 sky2_write8(hw, STAT_FIFO_WM, ecmd->rx_max_coalesced_frames);
3269
3270 if (ecmd->rx_coalesce_usecs_irq == 0)
3271 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_STOP);
3272 else {
3273 sky2_write32(hw, STAT_ISR_TIMER_INI,
3274 sky2_us2clk(hw, ecmd->rx_coalesce_usecs_irq));
3275 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START);
3276 }
3277 sky2_write8(hw, STAT_FIFO_ISR_WM, ecmd->rx_max_coalesced_frames_irq);
3278 return 0;
3279 }
3280
3281 static void sky2_get_ringparam(struct net_device *dev,
3282 struct ethtool_ringparam *ering)
3283 {
3284 struct sky2_port *sky2 = netdev_priv(dev);
3285
3286 ering->rx_max_pending = RX_MAX_PENDING;
3287 ering->rx_mini_max_pending = 0;
3288 ering->rx_jumbo_max_pending = 0;
3289 ering->tx_max_pending = TX_RING_SIZE - 1;
3290
3291 ering->rx_pending = sky2->rx_pending;
3292 ering->rx_mini_pending = 0;
3293 ering->rx_jumbo_pending = 0;
3294 ering->tx_pending = sky2->tx_pending;
3295 }
3296
3297 static int sky2_set_ringparam(struct net_device *dev,
3298 struct ethtool_ringparam *ering)
3299 {
3300 struct sky2_port *sky2 = netdev_priv(dev);
3301 int err = 0;
3302
3303 if (ering->rx_pending > RX_MAX_PENDING ||
3304 ering->rx_pending < 8 ||
3305 ering->tx_pending < MAX_SKB_TX_LE ||
3306 ering->tx_pending > TX_RING_SIZE - 1)
3307 return -EINVAL;
3308
3309 if (netif_running(dev))
3310 sky2_down(dev);
3311
3312 sky2->rx_pending = ering->rx_pending;
3313 sky2->tx_pending = ering->tx_pending;
3314
3315 if (netif_running(dev)) {
3316 err = sky2_up(dev);
3317 if (err)
3318 dev_close(dev);
3319 else
3320 sky2_set_multicast(dev);
3321 }
3322
3323 return err;
3324 }
3325
3326 static int sky2_get_regs_len(struct net_device *dev)
3327 {
3328 return 0x4000;
3329 }
3330
3331 /*
3332 * Returns copy of control register region
3333 * Note: access to the RAM address register set will cause timeouts.
3334 */
3335 static void sky2_get_regs(struct net_device *dev, struct ethtool_regs *regs,
3336 void *p)
3337 {
3338 const struct sky2_port *sky2 = netdev_priv(dev);
3339 const void __iomem *io = sky2->hw->regs;
3340
3341 BUG_ON(regs->len < B3_RI_WTO_R1);
3342 regs->version = 1;
3343 memset(p, 0, regs->len);
3344
3345 memcpy_fromio(p, io, B3_RAM_ADDR);
3346
3347 memcpy_fromio(p + B3_RI_WTO_R1,
3348 io + B3_RI_WTO_R1,
3349 regs->len - B3_RI_WTO_R1);
3350 }
3351
3352 /* In order to do Jumbo packets on these chips, need to turn off the
3353 * transmit store/forward. Therefore checksum offload won't work.
3354 */
3355 static int no_tx_offload(struct net_device *dev)
3356 {
3357 const struct sky2_port *sky2 = netdev_priv(dev);
3358 const struct sky2_hw *hw = sky2->hw;
3359
3360 return dev->mtu > ETH_DATA_LEN &&
3361 (hw->chip_id == CHIP_ID_YUKON_EX
3362 || hw->chip_id == CHIP_ID_YUKON_EC_U);
3363 }
3364
3365 static int sky2_set_tx_csum(struct net_device *dev, u32 data)
3366 {
3367 if (data && no_tx_offload(dev))
3368 return -EINVAL;
3369
3370 return ethtool_op_set_tx_csum(dev, data);
3371 }
3372
3373
3374 static int sky2_set_tso(struct net_device *dev, u32 data)
3375 {
3376 if (data && no_tx_offload(dev))
3377 return -EINVAL;
3378
3379 return ethtool_op_set_tso(dev, data);
3380 }
3381
3382 static const struct ethtool_ops sky2_ethtool_ops = {
3383 .get_settings = sky2_get_settings,
3384 .set_settings = sky2_set_settings,
3385 .get_drvinfo = sky2_get_drvinfo,
3386 .get_wol = sky2_get_wol,
3387 .set_wol = sky2_set_wol,
3388 .get_msglevel = sky2_get_msglevel,
3389 .set_msglevel = sky2_set_msglevel,
3390 .nway_reset = sky2_nway_reset,
3391 .get_regs_len = sky2_get_regs_len,
3392 .get_regs = sky2_get_regs,
3393 .get_link = ethtool_op_get_link,
3394 .get_sg = ethtool_op_get_sg,
3395 .set_sg = ethtool_op_set_sg,
3396 .get_tx_csum = ethtool_op_get_tx_csum,
3397 .set_tx_csum = sky2_set_tx_csum,
3398 .get_tso = ethtool_op_get_tso,
3399 .set_tso = sky2_set_tso,
3400 .get_rx_csum = sky2_get_rx_csum,
3401 .set_rx_csum = sky2_set_rx_csum,
3402 .get_strings = sky2_get_strings,
3403 .get_coalesce = sky2_get_coalesce,
3404 .set_coalesce = sky2_set_coalesce,
3405 .get_ringparam = sky2_get_ringparam,
3406 .set_ringparam = sky2_set_ringparam,
3407 .get_pauseparam = sky2_get_pauseparam,
3408 .set_pauseparam = sky2_set_pauseparam,
3409 .phys_id = sky2_phys_id,
3410 .get_stats_count = sky2_get_stats_count,
3411 .get_ethtool_stats = sky2_get_ethtool_stats,
3412 .get_perm_addr = ethtool_op_get_perm_addr,
3413 };
3414
3415 /* Initialize network device */
3416 static __devinit struct net_device *sky2_init_netdev(struct sky2_hw *hw,
3417 unsigned port,
3418 int highmem, int wol)
3419 {
3420 struct sky2_port *sky2;
3421 struct net_device *dev = alloc_etherdev(sizeof(*sky2));
3422
3423 if (!dev) {
3424 dev_err(&hw->pdev->dev, "etherdev alloc failed");
3425 return NULL;
3426 }
3427
3428 SET_MODULE_OWNER(dev);
3429 SET_NETDEV_DEV(dev, &hw->pdev->dev);
3430 dev->irq = hw->pdev->irq;
3431 dev->open = sky2_up;
3432 dev->stop = sky2_down;
3433 dev->do_ioctl = sky2_ioctl;
3434 dev->hard_start_xmit = sky2_xmit_frame;
3435 dev->get_stats = sky2_get_stats;
3436 dev->set_multicast_list = sky2_set_multicast;
3437 dev->set_mac_address = sky2_set_mac_address;
3438 dev->change_mtu = sky2_change_mtu;
3439 SET_ETHTOOL_OPS(dev, &sky2_ethtool_ops);
3440 dev->tx_timeout = sky2_tx_timeout;
3441 dev->watchdog_timeo = TX_WATCHDOG;
3442 if (port == 0)
3443 dev->poll = sky2_poll;
3444 dev->weight = NAPI_WEIGHT;
3445 #ifdef CONFIG_NET_POLL_CONTROLLER
3446 /* Network console (only works on port 0)
3447 * because netpoll makes assumptions about NAPI
3448 */
3449 if (port == 0)
3450 dev->poll_controller = sky2_netpoll;
3451 #endif
3452
3453 sky2 = netdev_priv(dev);
3454 sky2->netdev = dev;
3455 sky2->hw = hw;
3456 sky2->msg_enable = netif_msg_init(debug, default_msg);
3457
3458 /* Auto speed and flow control */
3459 sky2->autoneg = AUTONEG_ENABLE;
3460 sky2->flow_mode = FC_BOTH;
3461
3462 sky2->duplex = -1;
3463 sky2->speed = -1;
3464 sky2->advertising = sky2_supported_modes(hw);
3465 sky2->rx_csum = 1;
3466 sky2->wol = wol;
3467
3468 spin_lock_init(&sky2->phy_lock);
3469 sky2->tx_pending = TX_DEF_PENDING;
3470 sky2->rx_pending = RX_DEF_PENDING;
3471
3472 hw->dev[port] = dev;
3473
3474 sky2->port = port;
3475
3476 dev->features |= NETIF_F_TSO | NETIF_F_IP_CSUM | NETIF_F_SG;
3477 if (highmem)
3478 dev->features |= NETIF_F_HIGHDMA;
3479
3480 #ifdef SKY2_VLAN_TAG_USED
3481 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
3482 dev->vlan_rx_register = sky2_vlan_rx_register;
3483 #endif
3484
3485 /* read the mac address */
3486 memcpy_fromio(dev->dev_addr, hw->regs + B2_MAC_1 + port * 8, ETH_ALEN);
3487 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
3488
3489 /* device is off until link detection */
3490 netif_carrier_off(dev);
3491 netif_stop_queue(dev);
3492
3493 return dev;
3494 }
3495
3496 static void __devinit sky2_show_addr(struct net_device *dev)
3497 {
3498 const struct sky2_port *sky2 = netdev_priv(dev);
3499
3500 if (netif_msg_probe(sky2))
3501 printk(KERN_INFO PFX "%s: addr %02x:%02x:%02x:%02x:%02x:%02x\n",
3502 dev->name,
3503 dev->dev_addr[0], dev->dev_addr[1], dev->dev_addr[2],
3504 dev->dev_addr[3], dev->dev_addr[4], dev->dev_addr[5]);
3505 }
3506
3507 /* Handle software interrupt used during MSI test */
3508 static irqreturn_t __devinit sky2_test_intr(int irq, void *dev_id)
3509 {
3510 struct sky2_hw *hw = dev_id;
3511 u32 status = sky2_read32(hw, B0_Y2_SP_ISRC2);
3512
3513 if (status == 0)
3514 return IRQ_NONE;
3515
3516 if (status & Y2_IS_IRQ_SW) {
3517 hw->msi = 1;
3518 wake_up(&hw->msi_wait);
3519 sky2_write8(hw, B0_CTST, CS_CL_SW_IRQ);
3520 }
3521 sky2_write32(hw, B0_Y2_SP_ICR, 2);
3522
3523 return IRQ_HANDLED;
3524 }
3525
3526 /* Test interrupt path by forcing a a software IRQ */
3527 static int __devinit sky2_test_msi(struct sky2_hw *hw)
3528 {
3529 struct pci_dev *pdev = hw->pdev;
3530 int err;
3531
3532 init_waitqueue_head (&hw->msi_wait);
3533
3534 sky2_write32(hw, B0_IMSK, Y2_IS_IRQ_SW);
3535
3536 err = request_irq(pdev->irq, sky2_test_intr, 0, DRV_NAME, hw);
3537 if (err) {
3538 dev_err(&pdev->dev, "cannot assign irq %d\n", pdev->irq);
3539 return err;
3540 }
3541
3542 sky2_write8(hw, B0_CTST, CS_ST_SW_IRQ);
3543 sky2_read8(hw, B0_CTST);
3544
3545 wait_event_timeout(hw->msi_wait, hw->msi, HZ/10);
3546
3547 if (!hw->msi) {
3548 /* MSI test failed, go back to INTx mode */
3549 dev_info(&pdev->dev, "No interrupt generated using MSI, "
3550 "switching to INTx mode.\n");
3551
3552 err = -EOPNOTSUPP;
3553 sky2_write8(hw, B0_CTST, CS_CL_SW_IRQ);
3554 }
3555
3556 sky2_write32(hw, B0_IMSK, 0);
3557 sky2_read32(hw, B0_IMSK);
3558
3559 free_irq(pdev->irq, hw);
3560
3561 return err;
3562 }
3563
3564 static int __devinit pci_wake_enabled(struct pci_dev *dev)
3565 {
3566 int pm = pci_find_capability(dev, PCI_CAP_ID_PM);
3567 u16 value;
3568
3569 if (!pm)
3570 return 0;
3571 if (pci_read_config_word(dev, pm + PCI_PM_CTRL, &value))
3572 return 0;
3573 return value & PCI_PM_CTRL_PME_ENABLE;
3574 }
3575
3576 static int __devinit sky2_probe(struct pci_dev *pdev,
3577 const struct pci_device_id *ent)
3578 {
3579 struct net_device *dev;
3580 struct sky2_hw *hw;
3581 int err, using_dac = 0, wol_default;
3582
3583 err = pci_enable_device(pdev);
3584 if (err) {
3585 dev_err(&pdev->dev, "cannot enable PCI device\n");
3586 goto err_out;
3587 }
3588
3589 err = pci_request_regions(pdev, DRV_NAME);
3590 if (err) {
3591 dev_err(&pdev->dev, "cannot obtain PCI resources\n");
3592 goto err_out_disable;
3593 }
3594
3595 pci_set_master(pdev);
3596
3597 if (sizeof(dma_addr_t) > sizeof(u32) &&
3598 !(err = pci_set_dma_mask(pdev, DMA_64BIT_MASK))) {
3599 using_dac = 1;
3600 err = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
3601 if (err < 0) {
3602 dev_err(&pdev->dev, "unable to obtain 64 bit DMA "
3603 "for consistent allocations\n");
3604 goto err_out_free_regions;
3605 }
3606 } else {
3607 err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
3608 if (err) {
3609 dev_err(&pdev->dev, "no usable DMA configuration\n");
3610 goto err_out_free_regions;
3611 }
3612 }
3613
3614 wol_default = pci_wake_enabled(pdev) ? WAKE_MAGIC : 0;
3615
3616 err = -ENOMEM;
3617 hw = kzalloc(sizeof(*hw), GFP_KERNEL);
3618 if (!hw) {
3619 dev_err(&pdev->dev, "cannot allocate hardware struct\n");
3620 goto err_out_free_regions;
3621 }
3622
3623 hw->pdev = pdev;
3624
3625 hw->regs = ioremap_nocache(pci_resource_start(pdev, 0), 0x4000);
3626 if (!hw->regs) {
3627 dev_err(&pdev->dev, "cannot map device registers\n");
3628 goto err_out_free_hw;
3629 }
3630
3631 #ifdef __BIG_ENDIAN
3632 /* The sk98lin vendor driver uses hardware byte swapping but
3633 * this driver uses software swapping.
3634 */
3635 {
3636 u32 reg;
3637 reg = sky2_pci_read32(hw, PCI_DEV_REG2);
3638 reg &= ~PCI_REV_DESC;
3639 sky2_pci_write32(hw, PCI_DEV_REG2, reg);
3640 }
3641 #endif
3642
3643 /* ring for status responses */
3644 hw->st_le = pci_alloc_consistent(hw->pdev, STATUS_LE_BYTES,
3645 &hw->st_dma);
3646 if (!hw->st_le)
3647 goto err_out_iounmap;
3648
3649 err = sky2_init(hw);
3650 if (err)
3651 goto err_out_iounmap;
3652
3653 dev_info(&pdev->dev, "v%s addr 0x%llx irq %d Yukon-%s (0x%x) rev %d\n",
3654 DRV_VERSION, (unsigned long long)pci_resource_start(pdev, 0),
3655 pdev->irq, yukon2_name[hw->chip_id - CHIP_ID_YUKON_XL],
3656 hw->chip_id, hw->chip_rev);
3657
3658 sky2_reset(hw);
3659
3660 dev = sky2_init_netdev(hw, 0, using_dac, wol_default);
3661 if (!dev) {
3662 err = -ENOMEM;
3663 goto err_out_free_pci;
3664 }
3665
3666 if (!disable_msi && pci_enable_msi(pdev) == 0) {
3667 err = sky2_test_msi(hw);
3668 if (err == -EOPNOTSUPP)
3669 pci_disable_msi(pdev);
3670 else if (err)
3671 goto err_out_free_netdev;
3672 }
3673
3674 err = register_netdev(dev);
3675 if (err) {
3676 dev_err(&pdev->dev, "cannot register net device\n");
3677 goto err_out_free_netdev;
3678 }
3679
3680 err = request_irq(pdev->irq, sky2_intr, hw->msi ? 0 : IRQF_SHARED,
3681 dev->name, hw);
3682 if (err) {
3683 dev_err(&pdev->dev, "cannot assign irq %d\n", pdev->irq);
3684 goto err_out_unregister;
3685 }
3686 sky2_write32(hw, B0_IMSK, Y2_IS_BASE);
3687
3688 sky2_show_addr(dev);
3689
3690 if (hw->ports > 1) {
3691 struct net_device *dev1;
3692
3693 dev1 = sky2_init_netdev(hw, 1, using_dac, wol_default);
3694 if (!dev1)
3695 dev_warn(&pdev->dev, "allocation for second device failed\n");
3696 else if ((err = register_netdev(dev1))) {
3697 dev_warn(&pdev->dev,
3698 "register of second port failed (%d)\n", err);
3699 hw->dev[1] = NULL;
3700 free_netdev(dev1);
3701 } else
3702 sky2_show_addr(dev1);
3703 }
3704
3705 setup_timer(&hw->idle_timer, sky2_idle, (unsigned long) hw);
3706 INIT_WORK(&hw->restart_work, sky2_restart);
3707
3708 sky2_idle_start(hw);
3709
3710 pci_set_drvdata(pdev, hw);
3711
3712 return 0;
3713
3714 err_out_unregister:
3715 if (hw->msi)
3716 pci_disable_msi(pdev);
3717 unregister_netdev(dev);
3718 err_out_free_netdev:
3719 free_netdev(dev);
3720 err_out_free_pci:
3721 sky2_write8(hw, B0_CTST, CS_RST_SET);
3722 pci_free_consistent(hw->pdev, STATUS_LE_BYTES, hw->st_le, hw->st_dma);
3723 err_out_iounmap:
3724 iounmap(hw->regs);
3725 err_out_free_hw:
3726 kfree(hw);
3727 err_out_free_regions:
3728 pci_release_regions(pdev);
3729 err_out_disable:
3730 pci_disable_device(pdev);
3731 err_out:
3732 pci_set_drvdata(pdev, NULL);
3733 return err;
3734 }
3735
3736 static void __devexit sky2_remove(struct pci_dev *pdev)
3737 {
3738 struct sky2_hw *hw = pci_get_drvdata(pdev);
3739 struct net_device *dev0, *dev1;
3740
3741 if (!hw)
3742 return;
3743
3744 del_timer_sync(&hw->idle_timer);
3745
3746 flush_scheduled_work();
3747
3748 sky2_write32(hw, B0_IMSK, 0);
3749 synchronize_irq(hw->pdev->irq);
3750
3751 dev0 = hw->dev[0];
3752 dev1 = hw->dev[1];
3753 if (dev1)
3754 unregister_netdev(dev1);
3755 unregister_netdev(dev0);
3756
3757 sky2_power_aux(hw);
3758
3759 sky2_write16(hw, B0_Y2LED, LED_STAT_OFF);
3760 sky2_write8(hw, B0_CTST, CS_RST_SET);
3761 sky2_read8(hw, B0_CTST);
3762
3763 free_irq(pdev->irq, hw);
3764 if (hw->msi)
3765 pci_disable_msi(pdev);
3766 pci_free_consistent(pdev, STATUS_LE_BYTES, hw->st_le, hw->st_dma);
3767 pci_release_regions(pdev);
3768 pci_disable_device(pdev);
3769
3770 if (dev1)
3771 free_netdev(dev1);
3772 free_netdev(dev0);
3773 iounmap(hw->regs);
3774 kfree(hw);
3775
3776 pci_set_drvdata(pdev, NULL);
3777 }
3778
3779 #ifdef CONFIG_PM
3780 static int sky2_suspend(struct pci_dev *pdev, pm_message_t state)
3781 {
3782 struct sky2_hw *hw = pci_get_drvdata(pdev);
3783 int i, wol = 0;
3784
3785 if (!hw)
3786 return 0;
3787
3788 del_timer_sync(&hw->idle_timer);
3789 netif_poll_disable(hw->dev[0]);
3790
3791 for (i = 0; i < hw->ports; i++) {
3792 struct net_device *dev = hw->dev[i];
3793 struct sky2_port *sky2 = netdev_priv(dev);
3794
3795 if (netif_running(dev))
3796 sky2_down(dev);
3797
3798 if (sky2->wol)
3799 sky2_wol_init(sky2);
3800
3801 wol |= sky2->wol;
3802 }
3803
3804 sky2_write32(hw, B0_IMSK, 0);
3805 sky2_power_aux(hw);
3806
3807 pci_save_state(pdev);
3808 pci_enable_wake(pdev, pci_choose_state(pdev, state), wol);
3809 pci_set_power_state(pdev, pci_choose_state(pdev, state));
3810
3811 return 0;
3812 }
3813
3814 static int sky2_resume(struct pci_dev *pdev)
3815 {
3816 struct sky2_hw *hw = pci_get_drvdata(pdev);
3817 int i, err;
3818
3819 if (!hw)
3820 return 0;
3821
3822 err = pci_set_power_state(pdev, PCI_D0);
3823 if (err)
3824 goto out;
3825
3826 err = pci_restore_state(pdev);
3827 if (err)
3828 goto out;
3829
3830 pci_enable_wake(pdev, PCI_D0, 0);
3831
3832 /* Re-enable all clocks */
3833 if (hw->chip_id == CHIP_ID_YUKON_EX || hw->chip_id == CHIP_ID_YUKON_EC_U)
3834 sky2_pci_write32(hw, PCI_DEV_REG3, 0);
3835
3836 sky2_reset(hw);
3837
3838 sky2_write32(hw, B0_IMSK, Y2_IS_BASE);
3839
3840 for (i = 0; i < hw->ports; i++) {
3841 struct net_device *dev = hw->dev[i];
3842 if (netif_running(dev)) {
3843 err = sky2_up(dev);
3844 if (err) {
3845 printk(KERN_ERR PFX "%s: could not up: %d\n",
3846 dev->name, err);
3847 dev_close(dev);
3848 goto out;
3849 }
3850 }
3851 }
3852
3853 netif_poll_enable(hw->dev[0]);
3854 sky2_idle_start(hw);
3855 return 0;
3856 out:
3857 dev_err(&pdev->dev, "resume failed (%d)\n", err);
3858 pci_disable_device(pdev);
3859 return err;
3860 }
3861 #endif
3862
3863 static void sky2_shutdown(struct pci_dev *pdev)
3864 {
3865 struct sky2_hw *hw = pci_get_drvdata(pdev);
3866 int i, wol = 0;
3867
3868 if (!hw)
3869 return;
3870
3871 del_timer_sync(&hw->idle_timer);
3872 netif_poll_disable(hw->dev[0]);
3873
3874 for (i = 0; i < hw->ports; i++) {
3875 struct net_device *dev = hw->dev[i];
3876 struct sky2_port *sky2 = netdev_priv(dev);
3877
3878 if (sky2->wol) {
3879 wol = 1;
3880 sky2_wol_init(sky2);
3881 }
3882 }
3883
3884 if (wol)
3885 sky2_power_aux(hw);
3886
3887 pci_enable_wake(pdev, PCI_D3hot, wol);
3888 pci_enable_wake(pdev, PCI_D3cold, wol);
3889
3890 pci_disable_device(pdev);
3891 pci_set_power_state(pdev, PCI_D3hot);
3892
3893 }
3894
3895 static struct pci_driver sky2_driver = {
3896 .name = DRV_NAME,
3897 .id_table = sky2_id_table,
3898 .probe = sky2_probe,
3899 .remove = __devexit_p(sky2_remove),
3900 #ifdef CONFIG_PM
3901 .suspend = sky2_suspend,
3902 .resume = sky2_resume,
3903 #endif
3904 .shutdown = sky2_shutdown,
3905 };
3906
3907 static int __init sky2_init_module(void)
3908 {
3909 return pci_register_driver(&sky2_driver);
3910 }
3911
3912 static void __exit sky2_cleanup_module(void)
3913 {
3914 pci_unregister_driver(&sky2_driver);
3915 }
3916
3917 module_init(sky2_init_module);
3918 module_exit(sky2_cleanup_module);
3919
3920 MODULE_DESCRIPTION("Marvell Yukon 2 Gigabit Ethernet driver");
3921 MODULE_AUTHOR("Stephen Hemminger <shemminger@linux-foundation.org>");
3922 MODULE_LICENSE("GPL");
3923 MODULE_VERSION(DRV_VERSION);
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