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Pull bugzilla-9429 into release branch
[pv_ops_mirror.git] / drivers / net / ibm_newemac / mal.c
blob9a88f71db004ee0e328027e4bd5864271a4050a8
1 /*
2 * drivers/net/ibm_newemac/mal.c
3 *
4 * Memory Access Layer (MAL) support
5 *
6 * Copyright (c) 2004, 2005 Zultys Technologies.
7 * Eugene Surovegin <eugene.surovegin@zultys.com> or <ebs@ebshome.net>
8 *
9 * Based on original work by
10 * Benjamin Herrenschmidt <benh@kernel.crashing.org>,
11 * David Gibson <hermes@gibson.dropbear.id.au>,
12 *
13 * Armin Kuster <akuster@mvista.com>
14 * Copyright 2002 MontaVista Softare Inc.
15 *
16 * This program is free software; you can redistribute it and/or modify it
17 * under the terms of the GNU General Public License as published by the
18 * Free Software Foundation; either version 2 of the License, or (at your
19 * option) any later version.
20 *
21 */
22
23 #include <linux/delay.h>
24
25 #include "core.h"
26
27 static int mal_count;
28
29 int __devinit mal_register_commac(struct mal_instance *mal,
30 struct mal_commac *commac)
31 {
32 unsigned long flags;
33
34 spin_lock_irqsave(&mal->lock, flags);
35
36 MAL_DBG(mal, "reg(%08x, %08x)" NL,
37 commac->tx_chan_mask, commac->rx_chan_mask);
38
39 /* Don't let multiple commacs claim the same channel(s) */
40 if ((mal->tx_chan_mask & commac->tx_chan_mask) ||
41 (mal->rx_chan_mask & commac->rx_chan_mask)) {
42 spin_unlock_irqrestore(&mal->lock, flags);
43 printk(KERN_WARNING "mal%d: COMMAC channels conflict!\n",
44 mal->index);
45 return -EBUSY;
46 }
47
48 if (list_empty(&mal->list))
49 napi_enable(&mal->napi);
50 mal->tx_chan_mask |= commac->tx_chan_mask;
51 mal->rx_chan_mask |= commac->rx_chan_mask;
52 list_add(&commac->list, &mal->list);
53
54 spin_unlock_irqrestore(&mal->lock, flags);
55
56 return 0;
57 }
58
59 void __devexit mal_unregister_commac(struct mal_instance *mal,
60 struct mal_commac *commac)
61 {
62 unsigned long flags;
63
64 spin_lock_irqsave(&mal->lock, flags);
65
66 MAL_DBG(mal, "unreg(%08x, %08x)" NL,
67 commac->tx_chan_mask, commac->rx_chan_mask);
68
69 mal->tx_chan_mask &= ~commac->tx_chan_mask;
70 mal->rx_chan_mask &= ~commac->rx_chan_mask;
71 list_del_init(&commac->list);
72 if (list_empty(&mal->list))
73 napi_disable(&mal->napi);
74
75 spin_unlock_irqrestore(&mal->lock, flags);
76 }
77
78 int mal_set_rcbs(struct mal_instance *mal, int channel, unsigned long size)
79 {
80 BUG_ON(channel < 0 || channel >= mal->num_rx_chans ||
81 size > MAL_MAX_RX_SIZE);
82
83 MAL_DBG(mal, "set_rbcs(%d, %lu)" NL, channel, size);
84
85 if (size & 0xf) {
86 printk(KERN_WARNING
87 "mal%d: incorrect RX size %lu for the channel %d\n",
88 mal->index, size, channel);
89 return -EINVAL;
90 }
91
92 set_mal_dcrn(mal, MAL_RCBS(channel), size >> 4);
93 return 0;
94 }
95
96 int mal_tx_bd_offset(struct mal_instance *mal, int channel)
97 {
98 BUG_ON(channel < 0 || channel >= mal->num_tx_chans);
99
100 return channel * NUM_TX_BUFF;
101 }
102
103 int mal_rx_bd_offset(struct mal_instance *mal, int channel)
104 {
105 BUG_ON(channel < 0 || channel >= mal->num_rx_chans);
106 return mal->num_tx_chans * NUM_TX_BUFF + channel * NUM_RX_BUFF;
107 }
108
109 void mal_enable_tx_channel(struct mal_instance *mal, int channel)
110 {
111 unsigned long flags;
112
113 spin_lock_irqsave(&mal->lock, flags);
114
115 MAL_DBG(mal, "enable_tx(%d)" NL, channel);
116
117 set_mal_dcrn(mal, MAL_TXCASR,
118 get_mal_dcrn(mal, MAL_TXCASR) | MAL_CHAN_MASK(channel));
119
120 spin_unlock_irqrestore(&mal->lock, flags);
121 }
122
123 void mal_disable_tx_channel(struct mal_instance *mal, int channel)
124 {
125 set_mal_dcrn(mal, MAL_TXCARR, MAL_CHAN_MASK(channel));
126
127 MAL_DBG(mal, "disable_tx(%d)" NL, channel);
128 }
129
130 void mal_enable_rx_channel(struct mal_instance *mal, int channel)
131 {
132 unsigned long flags;
133
134 spin_lock_irqsave(&mal->lock, flags);
135
136 MAL_DBG(mal, "enable_rx(%d)" NL, channel);
137
138 set_mal_dcrn(mal, MAL_RXCASR,
139 get_mal_dcrn(mal, MAL_RXCASR) | MAL_CHAN_MASK(channel));
140
141 spin_unlock_irqrestore(&mal->lock, flags);
142 }
143
144 void mal_disable_rx_channel(struct mal_instance *mal, int channel)
145 {
146 set_mal_dcrn(mal, MAL_RXCARR, MAL_CHAN_MASK(channel));
147
148 MAL_DBG(mal, "disable_rx(%d)" NL, channel);
149 }
150
151 void mal_poll_add(struct mal_instance *mal, struct mal_commac *commac)
152 {
153 unsigned long flags;
154
155 spin_lock_irqsave(&mal->lock, flags);
156
157 MAL_DBG(mal, "poll_add(%p)" NL, commac);
158
159 /* starts disabled */
160 set_bit(MAL_COMMAC_POLL_DISABLED, &commac->flags);
161
162 list_add_tail(&commac->poll_list, &mal->poll_list);
163
164 spin_unlock_irqrestore(&mal->lock, flags);
165 }
166
167 void mal_poll_del(struct mal_instance *mal, struct mal_commac *commac)
168 {
169 unsigned long flags;
170
171 spin_lock_irqsave(&mal->lock, flags);
172
173 MAL_DBG(mal, "poll_del(%p)" NL, commac);
174
175 list_del(&commac->poll_list);
176
177 spin_unlock_irqrestore(&mal->lock, flags);
178 }
179
180 /* synchronized by mal_poll() */
181 static inline void mal_enable_eob_irq(struct mal_instance *mal)
182 {
183 MAL_DBG2(mal, "enable_irq" NL);
184
185 // XXX might want to cache MAL_CFG as the DCR read can be slooooow
186 set_mal_dcrn(mal, MAL_CFG, get_mal_dcrn(mal, MAL_CFG) | MAL_CFG_EOPIE);
187 }
188
189 /* synchronized by NAPI state */
190 static inline void mal_disable_eob_irq(struct mal_instance *mal)
191 {
192 // XXX might want to cache MAL_CFG as the DCR read can be slooooow
193 set_mal_dcrn(mal, MAL_CFG, get_mal_dcrn(mal, MAL_CFG) & ~MAL_CFG_EOPIE);
194
195 MAL_DBG2(mal, "disable_irq" NL);
196 }
197
198 static irqreturn_t mal_serr(int irq, void *dev_instance)
199 {
200 struct mal_instance *mal = dev_instance;
201
202 u32 esr = get_mal_dcrn(mal, MAL_ESR);
203
204 /* Clear the error status register */
205 set_mal_dcrn(mal, MAL_ESR, esr);
206
207 MAL_DBG(mal, "SERR %08x" NL, esr);
208
209 if (esr & MAL_ESR_EVB) {
210 if (esr & MAL_ESR_DE) {
211 /* We ignore Descriptor error,
212 * TXDE or RXDE interrupt will be generated anyway.
213 */
214 return IRQ_HANDLED;
215 }
216
217 if (esr & MAL_ESR_PEIN) {
218 /* PLB error, it's probably buggy hardware or
219 * incorrect physical address in BD (i.e. bug)
220 */
221 if (net_ratelimit())
222 printk(KERN_ERR
223 "mal%d: system error, "
224 "PLB (ESR = 0x%08x)\n",
225 mal->index, esr);
226 return IRQ_HANDLED;
227 }
228
229 /* OPB error, it's probably buggy hardware or incorrect
230 * EBC setup
231 */
232 if (net_ratelimit())
233 printk(KERN_ERR
234 "mal%d: system error, OPB (ESR = 0x%08x)\n",
235 mal->index, esr);
236 }
237 return IRQ_HANDLED;
238 }
239
240 static inline void mal_schedule_poll(struct mal_instance *mal)
241 {
242 if (likely(napi_schedule_prep(&mal->napi))) {
243 MAL_DBG2(mal, "schedule_poll" NL);
244 mal_disable_eob_irq(mal);
245 __napi_schedule(&mal->napi);
246 } else
247 MAL_DBG2(mal, "already in poll" NL);
248 }
249
250 static irqreturn_t mal_txeob(int irq, void *dev_instance)
251 {
252 struct mal_instance *mal = dev_instance;
253
254 u32 r = get_mal_dcrn(mal, MAL_TXEOBISR);
255
256 MAL_DBG2(mal, "txeob %08x" NL, r);
257
258 mal_schedule_poll(mal);
259 set_mal_dcrn(mal, MAL_TXEOBISR, r);
260
261 return IRQ_HANDLED;
262 }
263
264 static irqreturn_t mal_rxeob(int irq, void *dev_instance)
265 {
266 struct mal_instance *mal = dev_instance;
267
268 u32 r = get_mal_dcrn(mal, MAL_RXEOBISR);
269
270 MAL_DBG2(mal, "rxeob %08x" NL, r);
271
272 mal_schedule_poll(mal);
273 set_mal_dcrn(mal, MAL_RXEOBISR, r);
274
275 return IRQ_HANDLED;
276 }
277
278 static irqreturn_t mal_txde(int irq, void *dev_instance)
279 {
280 struct mal_instance *mal = dev_instance;
281
282 u32 deir = get_mal_dcrn(mal, MAL_TXDEIR);
283 set_mal_dcrn(mal, MAL_TXDEIR, deir);
284
285 MAL_DBG(mal, "txde %08x" NL, deir);
286
287 if (net_ratelimit())
288 printk(KERN_ERR
289 "mal%d: TX descriptor error (TXDEIR = 0x%08x)\n",
290 mal->index, deir);
291
292 return IRQ_HANDLED;
293 }
294
295 static irqreturn_t mal_rxde(int irq, void *dev_instance)
296 {
297 struct mal_instance *mal = dev_instance;
298 struct list_head *l;
299
300 u32 deir = get_mal_dcrn(mal, MAL_RXDEIR);
301
302 MAL_DBG(mal, "rxde %08x" NL, deir);
303
304 list_for_each(l, &mal->list) {
305 struct mal_commac *mc = list_entry(l, struct mal_commac, list);
306 if (deir & mc->rx_chan_mask) {
307 set_bit(MAL_COMMAC_RX_STOPPED, &mc->flags);
308 mc->ops->rxde(mc->dev);
309 }
310 }
311
312 mal_schedule_poll(mal);
313 set_mal_dcrn(mal, MAL_RXDEIR, deir);
314
315 return IRQ_HANDLED;
316 }
317
318 void mal_poll_disable(struct mal_instance *mal, struct mal_commac *commac)
319 {
320 /* Spinlock-type semantics: only one caller disable poll at a time */
321 while (test_and_set_bit(MAL_COMMAC_POLL_DISABLED, &commac->flags))
322 msleep(1);
323
324 /* Synchronize with the MAL NAPI poller */
325 napi_synchronize(&mal->napi);
326 }
327
328 void mal_poll_enable(struct mal_instance *mal, struct mal_commac *commac)
329 {
330 smp_wmb();
331 clear_bit(MAL_COMMAC_POLL_DISABLED, &commac->flags);
332
333 /* Feels better to trigger a poll here to catch up with events that
334 * may have happened on this channel while disabled. It will most
335 * probably be delayed until the next interrupt but that's mostly a
336 * non-issue in the context where this is called.
337 */
338 napi_schedule(&mal->napi);
339 }
340
341 static int mal_poll(struct napi_struct *napi, int budget)
342 {
343 struct mal_instance *mal = container_of(napi, struct mal_instance, napi);
344 struct list_head *l;
345 int received = 0;
346 unsigned long flags;
347
348 MAL_DBG2(mal, "poll(%d)" NL, budget);
349 again:
350 /* Process TX skbs */
351 list_for_each(l, &mal->poll_list) {
352 struct mal_commac *mc =
353 list_entry(l, struct mal_commac, poll_list);
354 mc->ops->poll_tx(mc->dev);
355 }
356
357 /* Process RX skbs.
358 *
359 * We _might_ need something more smart here to enforce polling
360 * fairness.
361 */
362 list_for_each(l, &mal->poll_list) {
363 struct mal_commac *mc =
364 list_entry(l, struct mal_commac, poll_list);
365 int n;
366 if (unlikely(test_bit(MAL_COMMAC_POLL_DISABLED, &mc->flags)))
367 continue;
368 n = mc->ops->poll_rx(mc->dev, budget);
369 if (n) {
370 received += n;
371 budget -= n;
372 if (budget <= 0)
373 goto more_work; // XXX What if this is the last one ?
374 }
375 }
376
377 /* We need to disable IRQs to protect from RXDE IRQ here */
378 spin_lock_irqsave(&mal->lock, flags);
379 __napi_complete(napi);
380 mal_enable_eob_irq(mal);
381 spin_unlock_irqrestore(&mal->lock, flags);
382
383 /* Check for "rotting" packet(s) */
384 list_for_each(l, &mal->poll_list) {
385 struct mal_commac *mc =
386 list_entry(l, struct mal_commac, poll_list);
387 if (unlikely(test_bit(MAL_COMMAC_POLL_DISABLED, &mc->flags)))
388 continue;
389 if (unlikely(mc->ops->peek_rx(mc->dev) ||
390 test_bit(MAL_COMMAC_RX_STOPPED, &mc->flags))) {
391 MAL_DBG2(mal, "rotting packet" NL);
392 if (napi_reschedule(napi))
393 mal_disable_eob_irq(mal);
394 else
395 MAL_DBG2(mal, "already in poll list" NL);
396
397 if (budget > 0)
398 goto again;
399 else
400 goto more_work;
401 }
402 mc->ops->poll_tx(mc->dev);
403 }
404
405 more_work:
406 MAL_DBG2(mal, "poll() %d <- %d" NL, budget, received);
407 return received;
408 }
409
410 static void mal_reset(struct mal_instance *mal)
411 {
412 int n = 10;
413
414 MAL_DBG(mal, "reset" NL);
415
416 set_mal_dcrn(mal, MAL_CFG, MAL_CFG_SR);
417
418 /* Wait for reset to complete (1 system clock) */
419 while ((get_mal_dcrn(mal, MAL_CFG) & MAL_CFG_SR) && n)
420 --n;
421
422 if (unlikely(!n))
423 printk(KERN_ERR "mal%d: reset timeout\n", mal->index);
424 }
425
426 int mal_get_regs_len(struct mal_instance *mal)
427 {
428 return sizeof(struct emac_ethtool_regs_subhdr) +
429 sizeof(struct mal_regs);
430 }
431
432 void *mal_dump_regs(struct mal_instance *mal, void *buf)
433 {
434 struct emac_ethtool_regs_subhdr *hdr = buf;
435 struct mal_regs *regs = (struct mal_regs *)(hdr + 1);
436 int i;
437
438 hdr->version = mal->version;
439 hdr->index = mal->index;
440
441 regs->tx_count = mal->num_tx_chans;
442 regs->rx_count = mal->num_rx_chans;
443
444 regs->cfg = get_mal_dcrn(mal, MAL_CFG);
445 regs->esr = get_mal_dcrn(mal, MAL_ESR);
446 regs->ier = get_mal_dcrn(mal, MAL_IER);
447 regs->tx_casr = get_mal_dcrn(mal, MAL_TXCASR);
448 regs->tx_carr = get_mal_dcrn(mal, MAL_TXCARR);
449 regs->tx_eobisr = get_mal_dcrn(mal, MAL_TXEOBISR);
450 regs->tx_deir = get_mal_dcrn(mal, MAL_TXDEIR);
451 regs->rx_casr = get_mal_dcrn(mal, MAL_RXCASR);
452 regs->rx_carr = get_mal_dcrn(mal, MAL_RXCARR);
453 regs->rx_eobisr = get_mal_dcrn(mal, MAL_RXEOBISR);
454 regs->rx_deir = get_mal_dcrn(mal, MAL_RXDEIR);
455
456 for (i = 0; i < regs->tx_count; ++i)
457 regs->tx_ctpr[i] = get_mal_dcrn(mal, MAL_TXCTPR(i));
458
459 for (i = 0; i < regs->rx_count; ++i) {
460 regs->rx_ctpr[i] = get_mal_dcrn(mal, MAL_RXCTPR(i));
461 regs->rcbs[i] = get_mal_dcrn(mal, MAL_RCBS(i));
462 }
463 return regs + 1;
464 }
465
466 static int __devinit mal_probe(struct of_device *ofdev,
467 const struct of_device_id *match)
468 {
469 struct mal_instance *mal;
470 int err = 0, i, bd_size;
471 int index = mal_count++;
472 unsigned int dcr_base;
473 const u32 *prop;
474 u32 cfg;
475
476 mal = kzalloc(sizeof(struct mal_instance), GFP_KERNEL);
477 if (!mal) {
478 printk(KERN_ERR
479 "mal%d: out of memory allocating MAL structure!\n",
480 index);
481 return -ENOMEM;
482 }
483 mal->index = index;
484 mal->ofdev = ofdev;
485 mal->version = of_device_is_compatible(ofdev->node, "ibm,mcmal2") ? 2 : 1;
486
487 MAL_DBG(mal, "probe" NL);
488
489 prop = of_get_property(ofdev->node, "num-tx-chans", NULL);
490 if (prop == NULL) {
491 printk(KERN_ERR
492 "mal%d: can't find MAL num-tx-chans property!\n",
493 index);
494 err = -ENODEV;
495 goto fail;
496 }
497 mal->num_tx_chans = prop[0];
498
499 prop = of_get_property(ofdev->node, "num-rx-chans", NULL);
500 if (prop == NULL) {
501 printk(KERN_ERR
502 "mal%d: can't find MAL num-rx-chans property!\n",
503 index);
504 err = -ENODEV;
505 goto fail;
506 }
507 mal->num_rx_chans = prop[0];
508
509 dcr_base = dcr_resource_start(ofdev->node, 0);
510 if (dcr_base == 0) {
511 printk(KERN_ERR
512 "mal%d: can't find DCR resource!\n", index);
513 err = -ENODEV;
514 goto fail;
515 }
516 mal->dcr_host = dcr_map(ofdev->node, dcr_base, 0x100);
517 if (!DCR_MAP_OK(mal->dcr_host)) {
518 printk(KERN_ERR
519 "mal%d: failed to map DCRs !\n", index);
520 err = -ENODEV;
521 goto fail;
522 }
523
524 mal->txeob_irq = irq_of_parse_and_map(ofdev->node, 0);
525 mal->rxeob_irq = irq_of_parse_and_map(ofdev->node, 1);
526 mal->serr_irq = irq_of_parse_and_map(ofdev->node, 2);
527 mal->txde_irq = irq_of_parse_and_map(ofdev->node, 3);
528 mal->rxde_irq = irq_of_parse_and_map(ofdev->node, 4);
529 if (mal->txeob_irq == NO_IRQ || mal->rxeob_irq == NO_IRQ ||
530 mal->serr_irq == NO_IRQ || mal->txde_irq == NO_IRQ ||
531 mal->rxde_irq == NO_IRQ) {
532 printk(KERN_ERR
533 "mal%d: failed to map interrupts !\n", index);
534 err = -ENODEV;
535 goto fail_unmap;
536 }
537
538 INIT_LIST_HEAD(&mal->poll_list);
539 INIT_LIST_HEAD(&mal->list);
540 spin_lock_init(&mal->lock);
541
542 netif_napi_add(NULL, &mal->napi, mal_poll,
543 CONFIG_IBM_NEW_EMAC_POLL_WEIGHT);
544
545 /* Load power-on reset defaults */
546 mal_reset(mal);
547
548 /* Set the MAL configuration register */
549 cfg = (mal->version == 2) ? MAL2_CFG_DEFAULT : MAL1_CFG_DEFAULT;
550 cfg |= MAL_CFG_PLBB | MAL_CFG_OPBBL | MAL_CFG_LEA;
551
552 /* Current Axon is not happy with priority being non-0, it can
553 * deadlock, fix it up here
554 */
555 if (of_device_is_compatible(ofdev->node, "ibm,mcmal-axon"))
556 cfg &= ~(MAL2_CFG_RPP_10 | MAL2_CFG_WPP_10);
557
558 /* Apply configuration */
559 set_mal_dcrn(mal, MAL_CFG, cfg);
560
561 /* Allocate space for BD rings */
562 BUG_ON(mal->num_tx_chans <= 0 || mal->num_tx_chans > 32);
563 BUG_ON(mal->num_rx_chans <= 0 || mal->num_rx_chans > 32);
564
565 bd_size = sizeof(struct mal_descriptor) *
566 (NUM_TX_BUFF * mal->num_tx_chans +
567 NUM_RX_BUFF * mal->num_rx_chans);
568 mal->bd_virt =
569 dma_alloc_coherent(&ofdev->dev, bd_size, &mal->bd_dma,
570 GFP_KERNEL);
571 if (mal->bd_virt == NULL) {
572 printk(KERN_ERR
573 "mal%d: out of memory allocating RX/TX descriptors!\n",
574 index);
575 err = -ENOMEM;
576 goto fail_unmap;
577 }
578 memset(mal->bd_virt, 0, bd_size);
579
580 for (i = 0; i < mal->num_tx_chans; ++i)
581 set_mal_dcrn(mal, MAL_TXCTPR(i), mal->bd_dma +
582 sizeof(struct mal_descriptor) *
583 mal_tx_bd_offset(mal, i));
584
585 for (i = 0; i < mal->num_rx_chans; ++i)
586 set_mal_dcrn(mal, MAL_RXCTPR(i), mal->bd_dma +
587 sizeof(struct mal_descriptor) *
588 mal_rx_bd_offset(mal, i));
589
590 err = request_irq(mal->serr_irq, mal_serr, 0, "MAL SERR", mal);
591 if (err)
592 goto fail2;
593 err = request_irq(mal->txde_irq, mal_txde, 0, "MAL TX DE", mal);
594 if (err)
595 goto fail3;
596 err = request_irq(mal->txeob_irq, mal_txeob, 0, "MAL TX EOB", mal);
597 if (err)
598 goto fail4;
599 err = request_irq(mal->rxde_irq, mal_rxde, 0, "MAL RX DE", mal);
600 if (err)
601 goto fail5;
602 err = request_irq(mal->rxeob_irq, mal_rxeob, 0, "MAL RX EOB", mal);
603 if (err)
604 goto fail6;
605
606 /* Enable all MAL SERR interrupt sources */
607 if (mal->version == 2)
608 set_mal_dcrn(mal, MAL_IER, MAL2_IER_EVENTS);
609 else
610 set_mal_dcrn(mal, MAL_IER, MAL1_IER_EVENTS);
611
612 /* Enable EOB interrupt */
613 mal_enable_eob_irq(mal);
614
615 printk(KERN_INFO
616 "MAL v%d %s, %d TX channels, %d RX channels\n",
617 mal->version, ofdev->node->full_name,
618 mal->num_tx_chans, mal->num_rx_chans);
619
620 /* Advertise this instance to the rest of the world */
621 wmb();
622 dev_set_drvdata(&ofdev->dev, mal);
623
624 mal_dbg_register(mal);
625
626 return 0;
627
628 fail6:
629 free_irq(mal->rxde_irq, mal);
630 fail5:
631 free_irq(mal->txeob_irq, mal);
632 fail4:
633 free_irq(mal->txde_irq, mal);
634 fail3:
635 free_irq(mal->serr_irq, mal);
636 fail2:
637 dma_free_coherent(&ofdev->dev, bd_size, mal->bd_virt, mal->bd_dma);
638 fail_unmap:
639 dcr_unmap(mal->dcr_host, 0x100);
640 fail:
641 kfree(mal);
642
643 return err;
644 }
645
646 static int __devexit mal_remove(struct of_device *ofdev)
647 {
648 struct mal_instance *mal = dev_get_drvdata(&ofdev->dev);
649
650 MAL_DBG(mal, "remove" NL);
651
652 /* Synchronize with scheduled polling */
653 napi_disable(&mal->napi);
654
655 if (!list_empty(&mal->list)) {
656 /* This is *very* bad */
657 printk(KERN_EMERG
658 "mal%d: commac list is not empty on remove!\n",
659 mal->index);
660 WARN_ON(1);
661 }
662
663 dev_set_drvdata(&ofdev->dev, NULL);
664
665 free_irq(mal->serr_irq, mal);
666 free_irq(mal->txde_irq, mal);
667 free_irq(mal->txeob_irq, mal);
668 free_irq(mal->rxde_irq, mal);
669 free_irq(mal->rxeob_irq, mal);
670
671 mal_reset(mal);
672
673 mal_dbg_unregister(mal);
674
675 dma_free_coherent(&ofdev->dev,
676 sizeof(struct mal_descriptor) *
677 (NUM_TX_BUFF * mal->num_tx_chans +
678 NUM_RX_BUFF * mal->num_rx_chans), mal->bd_virt,
679 mal->bd_dma);
680 kfree(mal);
681
682 return 0;
683 }
684
685 static struct of_device_id mal_platform_match[] =
686 {
687 {
688 .compatible = "ibm,mcmal",
689 },
690 {
691 .compatible = "ibm,mcmal2",
692 },
693 /* Backward compat */
694 {
695 .type = "mcmal-dma",
696 .compatible = "ibm,mcmal",
697 },
698 {
699 .type = "mcmal-dma",
700 .compatible = "ibm,mcmal2",
701 },
702 {},
703 };
704
705 static struct of_platform_driver mal_of_driver = {
706 .name = "mcmal",
707 .match_table = mal_platform_match,
708
709 .probe = mal_probe,
710 .remove = mal_remove,
711 };
712
713 int __init mal_init(void)
714 {
715 return of_register_platform_driver(&mal_of_driver);
716 }
717
718 void mal_exit(void)
719 {
720 of_unregister_platform_driver(&mal_of_driver);
721 }
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