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Pull bugzilla-9429 into release branch
[pv_ops_mirror.git] / drivers / net / wireless / b43 / phy.c
blob3d4ed647c311de9ebb84bc5b6b97c6af281f526e
1 /*
2
3 Broadcom B43 wireless driver
4
5 Copyright (c) 2005 Martin Langer <martin-langer@gmx.de>,
6 Copyright (c) 2005, 2006 Stefano Brivio <st3@riseup.net>
7 Copyright (c) 2005, 2006 Michael Buesch <mb@bu3sch.de>
8 Copyright (c) 2005, 2006 Danny van Dyk <kugelfang@gentoo.org>
9 Copyright (c) 2005, 2006 Andreas Jaggi <andreas.jaggi@waterwave.ch>
10
11 This program is free software; you can redistribute it and/or modify
12 it under the terms of the GNU General Public License as published by
13 the Free Software Foundation; either version 2 of the License, or
14 (at your option) any later version.
15
16 This program is distributed in the hope that it will be useful,
17 but WITHOUT ANY WARRANTY; without even the implied warranty of
18 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 GNU General Public License for more details.
20
21 You should have received a copy of the GNU General Public License
22 along with this program; see the file COPYING. If not, write to
23 the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor,
24 Boston, MA 02110-1301, USA.
25
26 */
27
28 #include <linux/delay.h>
29 #include <linux/io.h>
30 #include <linux/types.h>
31
32 #include "b43.h"
33 #include "phy.h"
34 #include "main.h"
35 #include "tables.h"
36 #include "lo.h"
37
38 static const s8 b43_tssi2dbm_b_table[] = {
39 0x4D, 0x4C, 0x4B, 0x4A,
40 0x4A, 0x49, 0x48, 0x47,
41 0x47, 0x46, 0x45, 0x45,
42 0x44, 0x43, 0x42, 0x42,
43 0x41, 0x40, 0x3F, 0x3E,
44 0x3D, 0x3C, 0x3B, 0x3A,
45 0x39, 0x38, 0x37, 0x36,
46 0x35, 0x34, 0x32, 0x31,
47 0x30, 0x2F, 0x2D, 0x2C,
48 0x2B, 0x29, 0x28, 0x26,
49 0x25, 0x23, 0x21, 0x1F,
50 0x1D, 0x1A, 0x17, 0x14,
51 0x10, 0x0C, 0x06, 0x00,
52 -7, -7, -7, -7,
53 -7, -7, -7, -7,
54 -7, -7, -7, -7,
55 };
56
57 static const s8 b43_tssi2dbm_g_table[] = {
58 77, 77, 77, 76,
59 76, 76, 75, 75,
60 74, 74, 73, 73,
61 73, 72, 72, 71,
62 71, 70, 70, 69,
63 68, 68, 67, 67,
64 66, 65, 65, 64,
65 63, 63, 62, 61,
66 60, 59, 58, 57,
67 56, 55, 54, 53,
68 52, 50, 49, 47,
69 45, 43, 40, 37,
70 33, 28, 22, 14,
71 5, -7, -20, -20,
72 -20, -20, -20, -20,
73 -20, -20, -20, -20,
74 };
75
76 const u8 b43_radio_channel_codes_bg[] = {
77 12, 17, 22, 27,
78 32, 37, 42, 47,
79 52, 57, 62, 67,
80 72, 84,
81 };
82
83 static void b43_phy_initg(struct b43_wldev *dev);
84
85 /* Reverse the bits of a 4bit value.
86 * Example: 1101 is flipped 1011
87 */
88 static u16 flip_4bit(u16 value)
89 {
90 u16 flipped = 0x0000;
91
92 B43_WARN_ON(value & ~0x000F);
93
94 flipped |= (value & 0x0001) << 3;
95 flipped |= (value & 0x0002) << 1;
96 flipped |= (value & 0x0004) >> 1;
97 flipped |= (value & 0x0008) >> 3;
98
99 return flipped;
100 }
101
102 static void generate_rfatt_list(struct b43_wldev *dev,
103 struct b43_rfatt_list *list)
104 {
105 struct b43_phy *phy = &dev->phy;
106
107 /* APHY.rev < 5 || GPHY.rev < 6 */
108 static const struct b43_rfatt rfatt_0[] = {
109 {.att = 3,.with_padmix = 0,},
110 {.att = 1,.with_padmix = 0,},
111 {.att = 5,.with_padmix = 0,},
112 {.att = 7,.with_padmix = 0,},
113 {.att = 9,.with_padmix = 0,},
114 {.att = 2,.with_padmix = 0,},
115 {.att = 0,.with_padmix = 0,},
116 {.att = 4,.with_padmix = 0,},
117 {.att = 6,.with_padmix = 0,},
118 {.att = 8,.with_padmix = 0,},
119 {.att = 1,.with_padmix = 1,},
120 {.att = 2,.with_padmix = 1,},
121 {.att = 3,.with_padmix = 1,},
122 {.att = 4,.with_padmix = 1,},
123 };
124 /* Radio.rev == 8 && Radio.version == 0x2050 */
125 static const struct b43_rfatt rfatt_1[] = {
126 {.att = 2,.with_padmix = 1,},
127 {.att = 4,.with_padmix = 1,},
128 {.att = 6,.with_padmix = 1,},
129 {.att = 8,.with_padmix = 1,},
130 {.att = 10,.with_padmix = 1,},
131 {.att = 12,.with_padmix = 1,},
132 {.att = 14,.with_padmix = 1,},
133 };
134 /* Otherwise */
135 static const struct b43_rfatt rfatt_2[] = {
136 {.att = 0,.with_padmix = 1,},
137 {.att = 2,.with_padmix = 1,},
138 {.att = 4,.with_padmix = 1,},
139 {.att = 6,.with_padmix = 1,},
140 {.att = 8,.with_padmix = 1,},
141 {.att = 9,.with_padmix = 1,},
142 {.att = 9,.with_padmix = 1,},
143 };
144
145 if ((phy->type == B43_PHYTYPE_A && phy->rev < 5) ||
146 (phy->type == B43_PHYTYPE_G && phy->rev < 6)) {
147 /* Software pctl */
148 list->list = rfatt_0;
149 list->len = ARRAY_SIZE(rfatt_0);
150 list->min_val = 0;
151 list->max_val = 9;
152 return;
153 }
154 if (phy->radio_ver == 0x2050 && phy->radio_rev == 8) {
155 /* Hardware pctl */
156 list->list = rfatt_1;
157 list->len = ARRAY_SIZE(rfatt_1);
158 list->min_val = 2;
159 list->max_val = 14;
160 return;
161 }
162 /* Hardware pctl */
163 list->list = rfatt_2;
164 list->len = ARRAY_SIZE(rfatt_2);
165 list->min_val = 0;
166 list->max_val = 9;
167 }
168
169 static void generate_bbatt_list(struct b43_wldev *dev,
170 struct b43_bbatt_list *list)
171 {
172 static const struct b43_bbatt bbatt_0[] = {
173 {.att = 0,},
174 {.att = 1,},
175 {.att = 2,},
176 {.att = 3,},
177 {.att = 4,},
178 {.att = 5,},
179 {.att = 6,},
180 {.att = 7,},
181 {.att = 8,},
182 };
183
184 list->list = bbatt_0;
185 list->len = ARRAY_SIZE(bbatt_0);
186 list->min_val = 0;
187 list->max_val = 8;
188 }
189
190 bool b43_has_hardware_pctl(struct b43_phy *phy)
191 {
192 if (!phy->hardware_power_control)
193 return 0;
194 switch (phy->type) {
195 case B43_PHYTYPE_A:
196 if (phy->rev >= 5)
197 return 1;
198 break;
199 case B43_PHYTYPE_G:
200 if (phy->rev >= 6)
201 return 1;
202 break;
203 default:
204 B43_WARN_ON(1);
205 }
206 return 0;
207 }
208
209 static void b43_shm_clear_tssi(struct b43_wldev *dev)
210 {
211 struct b43_phy *phy = &dev->phy;
212
213 switch (phy->type) {
214 case B43_PHYTYPE_A:
215 b43_shm_write16(dev, B43_SHM_SHARED, 0x0068, 0x7F7F);
216 b43_shm_write16(dev, B43_SHM_SHARED, 0x006a, 0x7F7F);
217 break;
218 case B43_PHYTYPE_B:
219 case B43_PHYTYPE_G:
220 b43_shm_write16(dev, B43_SHM_SHARED, 0x0058, 0x7F7F);
221 b43_shm_write16(dev, B43_SHM_SHARED, 0x005a, 0x7F7F);
222 b43_shm_write16(dev, B43_SHM_SHARED, 0x0070, 0x7F7F);
223 b43_shm_write16(dev, B43_SHM_SHARED, 0x0072, 0x7F7F);
224 break;
225 }
226 }
227
228 void b43_raw_phy_lock(struct b43_wldev *dev)
229 {
230 struct b43_phy *phy = &dev->phy;
231
232 B43_WARN_ON(!irqs_disabled());
233
234 /* We had a check for MACCTL==0 here, but I think that doesn't
235 * make sense, as MACCTL is never 0 when this is called.
236 * --mb */
237 B43_WARN_ON(b43_read32(dev, B43_MMIO_MACCTL) == 0);
238
239 if (dev->dev->id.revision < 3) {
240 b43_mac_suspend(dev);
241 spin_lock(&phy->lock);
242 } else {
243 if (!b43_is_mode(dev->wl, IEEE80211_IF_TYPE_AP))
244 b43_power_saving_ctl_bits(dev, B43_PS_AWAKE);
245 }
246 phy->locked = 1;
247 }
248
249 void b43_raw_phy_unlock(struct b43_wldev *dev)
250 {
251 struct b43_phy *phy = &dev->phy;
252
253 B43_WARN_ON(!irqs_disabled());
254 if (dev->dev->id.revision < 3) {
255 if (phy->locked) {
256 spin_unlock(&phy->lock);
257 b43_mac_enable(dev);
258 }
259 } else {
260 if (!b43_is_mode(dev->wl, IEEE80211_IF_TYPE_AP))
261 b43_power_saving_ctl_bits(dev, 0);
262 }
263 phy->locked = 0;
264 }
265
266 /* Different PHYs require different register routing flags.
267 * This adjusts (and does sanity checks on) the routing flags.
268 */
269 static inline u16 adjust_phyreg_for_phytype(struct b43_phy *phy,
270 u16 offset, struct b43_wldev *dev)
271 {
272 if (phy->type == B43_PHYTYPE_A) {
273 /* OFDM registers are base-registers for the A-PHY. */
274 offset &= ~B43_PHYROUTE_OFDM_GPHY;
275 }
276 if (offset & B43_PHYROUTE_EXT_GPHY) {
277 /* Ext-G registers are only available on G-PHYs */
278 if (phy->type != B43_PHYTYPE_G) {
279 b43dbg(dev->wl, "EXT-G PHY access at "
280 "0x%04X on %u type PHY\n", offset, phy->type);
281 }
282 }
283
284 return offset;
285 }
286
287 u16 b43_phy_read(struct b43_wldev * dev, u16 offset)
288 {
289 struct b43_phy *phy = &dev->phy;
290
291 offset = adjust_phyreg_for_phytype(phy, offset, dev);
292 b43_write16(dev, B43_MMIO_PHY_CONTROL, offset);
293 return b43_read16(dev, B43_MMIO_PHY_DATA);
294 }
295
296 void b43_phy_write(struct b43_wldev *dev, u16 offset, u16 val)
297 {
298 struct b43_phy *phy = &dev->phy;
299
300 offset = adjust_phyreg_for_phytype(phy, offset, dev);
301 b43_write16(dev, B43_MMIO_PHY_CONTROL, offset);
302 mmiowb();
303 b43_write16(dev, B43_MMIO_PHY_DATA, val);
304 }
305
306 static void b43_radio_set_txpower_a(struct b43_wldev *dev, u16 txpower);
307
308 /* Adjust the transmission power output (G-PHY) */
309 void b43_set_txpower_g(struct b43_wldev *dev,
310 const struct b43_bbatt *bbatt,
311 const struct b43_rfatt *rfatt, u8 tx_control)
312 {
313 struct b43_phy *phy = &dev->phy;
314 struct b43_txpower_lo_control *lo = phy->lo_control;
315 u16 bb, rf;
316 u16 tx_bias, tx_magn;
317
318 bb = bbatt->att;
319 rf = rfatt->att;
320 tx_bias = lo->tx_bias;
321 tx_magn = lo->tx_magn;
322 if (unlikely(tx_bias == 0xFF))
323 tx_bias = 0;
324
325 /* Save the values for later */
326 phy->tx_control = tx_control;
327 memcpy(&phy->rfatt, rfatt, sizeof(*rfatt));
328 memcpy(&phy->bbatt, bbatt, sizeof(*bbatt));
329
330 if (b43_debug(dev, B43_DBG_XMITPOWER)) {
331 b43dbg(dev->wl, "Tuning TX-power to bbatt(%u), "
332 "rfatt(%u), tx_control(0x%02X), "
333 "tx_bias(0x%02X), tx_magn(0x%02X)\n",
334 bb, rf, tx_control, tx_bias, tx_magn);
335 }
336
337 b43_phy_set_baseband_attenuation(dev, bb);
338 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_RFATT, rf);
339 if (phy->radio_ver == 0x2050 && phy->radio_rev == 8) {
340 b43_radio_write16(dev, 0x43,
341 (rf & 0x000F) | (tx_control & 0x0070));
342 } else {
343 b43_radio_write16(dev, 0x43, (b43_radio_read16(dev, 0x43)
344 & 0xFFF0) | (rf & 0x000F));
345 b43_radio_write16(dev, 0x52, (b43_radio_read16(dev, 0x52)
346 & ~0x0070) | (tx_control &
347 0x0070));
348 }
349 if (has_tx_magnification(phy)) {
350 b43_radio_write16(dev, 0x52, tx_magn | tx_bias);
351 } else {
352 b43_radio_write16(dev, 0x52, (b43_radio_read16(dev, 0x52)
353 & 0xFFF0) | (tx_bias & 0x000F));
354 }
355 if (phy->type == B43_PHYTYPE_G)
356 b43_lo_g_adjust(dev);
357 }
358
359 static void default_baseband_attenuation(struct b43_wldev *dev,
360 struct b43_bbatt *bb)
361 {
362 struct b43_phy *phy = &dev->phy;
363
364 if (phy->radio_ver == 0x2050 && phy->radio_rev < 6)
365 bb->att = 0;
366 else
367 bb->att = 2;
368 }
369
370 static void default_radio_attenuation(struct b43_wldev *dev,
371 struct b43_rfatt *rf)
372 {
373 struct ssb_bus *bus = dev->dev->bus;
374 struct b43_phy *phy = &dev->phy;
375
376 rf->with_padmix = 0;
377
378 if (bus->boardinfo.vendor == SSB_BOARDVENDOR_BCM &&
379 bus->boardinfo.type == SSB_BOARD_BCM4309G) {
380 if (bus->boardinfo.rev < 0x43) {
381 rf->att = 2;
382 return;
383 } else if (bus->boardinfo.rev < 0x51) {
384 rf->att = 3;
385 return;
386 }
387 }
388
389 if (phy->type == B43_PHYTYPE_A) {
390 rf->att = 0x60;
391 return;
392 }
393
394 switch (phy->radio_ver) {
395 case 0x2053:
396 switch (phy->radio_rev) {
397 case 1:
398 rf->att = 6;
399 return;
400 }
401 break;
402 case 0x2050:
403 switch (phy->radio_rev) {
404 case 0:
405 rf->att = 5;
406 return;
407 case 1:
408 if (phy->type == B43_PHYTYPE_G) {
409 if (bus->boardinfo.vendor == SSB_BOARDVENDOR_BCM
410 && bus->boardinfo.type == SSB_BOARD_BCM4309G
411 && bus->boardinfo.rev >= 30)
412 rf->att = 3;
413 else if (bus->boardinfo.vendor ==
414 SSB_BOARDVENDOR_BCM
415 && bus->boardinfo.type ==
416 SSB_BOARD_BU4306)
417 rf->att = 3;
418 else
419 rf->att = 1;
420 } else {
421 if (bus->boardinfo.vendor == SSB_BOARDVENDOR_BCM
422 && bus->boardinfo.type == SSB_BOARD_BCM4309G
423 && bus->boardinfo.rev >= 30)
424 rf->att = 7;
425 else
426 rf->att = 6;
427 }
428 return;
429 case 2:
430 if (phy->type == B43_PHYTYPE_G) {
431 if (bus->boardinfo.vendor == SSB_BOARDVENDOR_BCM
432 && bus->boardinfo.type == SSB_BOARD_BCM4309G
433 && bus->boardinfo.rev >= 30)
434 rf->att = 3;
435 else if (bus->boardinfo.vendor ==
436 SSB_BOARDVENDOR_BCM
437 && bus->boardinfo.type ==
438 SSB_BOARD_BU4306)
439 rf->att = 5;
440 else if (bus->chip_id == 0x4320)
441 rf->att = 4;
442 else
443 rf->att = 3;
444 } else
445 rf->att = 6;
446 return;
447 case 3:
448 rf->att = 5;
449 return;
450 case 4:
451 case 5:
452 rf->att = 1;
453 return;
454 case 6:
455 case 7:
456 rf->att = 5;
457 return;
458 case 8:
459 rf->att = 0xA;
460 rf->with_padmix = 1;
461 return;
462 case 9:
463 default:
464 rf->att = 5;
465 return;
466 }
467 }
468 rf->att = 5;
469 }
470
471 static u16 default_tx_control(struct b43_wldev *dev)
472 {
473 struct b43_phy *phy = &dev->phy;
474
475 if (phy->radio_ver != 0x2050)
476 return 0;
477 if (phy->radio_rev == 1)
478 return B43_TXCTL_PA2DB | B43_TXCTL_TXMIX;
479 if (phy->radio_rev < 6)
480 return B43_TXCTL_PA2DB;
481 if (phy->radio_rev == 8)
482 return B43_TXCTL_TXMIX;
483 return 0;
484 }
485
486 /* This func is called "PHY calibrate" in the specs... */
487 void b43_phy_early_init(struct b43_wldev *dev)
488 {
489 struct b43_phy *phy = &dev->phy;
490 struct b43_txpower_lo_control *lo = phy->lo_control;
491
492 default_baseband_attenuation(dev, &phy->bbatt);
493 default_radio_attenuation(dev, &phy->rfatt);
494 phy->tx_control = (default_tx_control(dev) << 4);
495
496 /* Commit previous writes */
497 b43_read32(dev, B43_MMIO_MACCTL);
498
499 if (phy->type == B43_PHYTYPE_B || phy->type == B43_PHYTYPE_G) {
500 generate_rfatt_list(dev, &lo->rfatt_list);
501 generate_bbatt_list(dev, &lo->bbatt_list);
502 }
503 if (phy->type == B43_PHYTYPE_G && phy->rev == 1) {
504 /* Workaround: Temporarly disable gmode through the early init
505 * phase, as the gmode stuff is not needed for phy rev 1 */
506 phy->gmode = 0;
507 b43_wireless_core_reset(dev, 0);
508 b43_phy_initg(dev);
509 phy->gmode = 1;
510 b43_wireless_core_reset(dev, B43_TMSLOW_GMODE);
511 }
512 }
513
514 /* GPHY_TSSI_Power_Lookup_Table_Init */
515 static void b43_gphy_tssi_power_lt_init(struct b43_wldev *dev)
516 {
517 struct b43_phy *phy = &dev->phy;
518 int i;
519 u16 value;
520
521 for (i = 0; i < 32; i++)
522 b43_ofdmtab_write16(dev, 0x3C20, i, phy->tssi2dbm[i]);
523 for (i = 32; i < 64; i++)
524 b43_ofdmtab_write16(dev, 0x3C00, i - 32, phy->tssi2dbm[i]);
525 for (i = 0; i < 64; i += 2) {
526 value = (u16) phy->tssi2dbm[i];
527 value |= ((u16) phy->tssi2dbm[i + 1]) << 8;
528 b43_phy_write(dev, 0x380 + (i / 2), value);
529 }
530 }
531
532 /* GPHY_Gain_Lookup_Table_Init */
533 static void b43_gphy_gain_lt_init(struct b43_wldev *dev)
534 {
535 struct b43_phy *phy = &dev->phy;
536 struct b43_txpower_lo_control *lo = phy->lo_control;
537 u16 nr_written = 0;
538 u16 tmp;
539 u8 rf, bb;
540
541 if (!lo->lo_measured) {
542 b43_phy_write(dev, 0x3FF, 0);
543 return;
544 }
545
546 for (rf = 0; rf < lo->rfatt_list.len; rf++) {
547 for (bb = 0; bb < lo->bbatt_list.len; bb++) {
548 if (nr_written >= 0x40)
549 return;
550 tmp = lo->bbatt_list.list[bb].att;
551 tmp <<= 8;
552 if (phy->radio_rev == 8)
553 tmp |= 0x50;
554 else
555 tmp |= 0x40;
556 tmp |= lo->rfatt_list.list[rf].att;
557 b43_phy_write(dev, 0x3C0 + nr_written, tmp);
558 nr_written++;
559 }
560 }
561 }
562
563 /* GPHY_DC_Lookup_Table */
564 void b43_gphy_dc_lt_init(struct b43_wldev *dev)
565 {
566 struct b43_phy *phy = &dev->phy;
567 struct b43_txpower_lo_control *lo = phy->lo_control;
568 struct b43_loctl *loctl0;
569 struct b43_loctl *loctl1;
570 int i;
571 int rf_offset, bb_offset;
572 u16 tmp;
573
574 for (i = 0; i < lo->rfatt_list.len + lo->bbatt_list.len; i += 2) {
575 rf_offset = i / lo->rfatt_list.len;
576 bb_offset = i % lo->rfatt_list.len;
577
578 loctl0 = b43_get_lo_g_ctl(dev, &lo->rfatt_list.list[rf_offset],
579 &lo->bbatt_list.list[bb_offset]);
580 if (i + 1 < lo->rfatt_list.len * lo->bbatt_list.len) {
581 rf_offset = (i + 1) / lo->rfatt_list.len;
582 bb_offset = (i + 1) % lo->rfatt_list.len;
583
584 loctl1 =
585 b43_get_lo_g_ctl(dev,
586 &lo->rfatt_list.list[rf_offset],
587 &lo->bbatt_list.list[bb_offset]);
588 } else
589 loctl1 = loctl0;
590
591 tmp = ((u16) loctl0->q & 0xF);
592 tmp |= ((u16) loctl0->i & 0xF) << 4;
593 tmp |= ((u16) loctl1->q & 0xF) << 8;
594 tmp |= ((u16) loctl1->i & 0xF) << 12; //FIXME?
595 b43_phy_write(dev, 0x3A0 + (i / 2), tmp);
596 }
597 }
598
599 static void hardware_pctl_init_aphy(struct b43_wldev *dev)
600 {
601 //TODO
602 }
603
604 static void hardware_pctl_init_gphy(struct b43_wldev *dev)
605 {
606 struct b43_phy *phy = &dev->phy;
607
608 b43_phy_write(dev, 0x0036, (b43_phy_read(dev, 0x0036) & 0xFFC0)
609 | (phy->tgt_idle_tssi - phy->cur_idle_tssi));
610 b43_phy_write(dev, 0x0478, (b43_phy_read(dev, 0x0478) & 0xFF00)
611 | (phy->tgt_idle_tssi - phy->cur_idle_tssi));
612 b43_gphy_tssi_power_lt_init(dev);
613 b43_gphy_gain_lt_init(dev);
614 b43_phy_write(dev, 0x0060, b43_phy_read(dev, 0x0060) & 0xFFBF);
615 b43_phy_write(dev, 0x0014, 0x0000);
616
617 B43_WARN_ON(phy->rev < 6);
618 b43_phy_write(dev, 0x0478, b43_phy_read(dev, 0x0478)
619 | 0x0800);
620 b43_phy_write(dev, 0x0478, b43_phy_read(dev, 0x0478)
621 & 0xFEFF);
622 b43_phy_write(dev, 0x0801, b43_phy_read(dev, 0x0801)
623 & 0xFFBF);
624
625 b43_gphy_dc_lt_init(dev);
626 }
627
628 /* HardwarePowerControl init for A and G PHY */
629 static void b43_hardware_pctl_init(struct b43_wldev *dev)
630 {
631 struct b43_phy *phy = &dev->phy;
632
633 if (!b43_has_hardware_pctl(phy)) {
634 /* No hardware power control */
635 b43_hf_write(dev, b43_hf_read(dev) & ~B43_HF_HWPCTL);
636 return;
637 }
638 /* Init the hwpctl related hardware */
639 switch (phy->type) {
640 case B43_PHYTYPE_A:
641 hardware_pctl_init_aphy(dev);
642 break;
643 case B43_PHYTYPE_G:
644 hardware_pctl_init_gphy(dev);
645 break;
646 default:
647 B43_WARN_ON(1);
648 }
649 /* Enable hardware pctl in firmware. */
650 b43_hf_write(dev, b43_hf_read(dev) | B43_HF_HWPCTL);
651 }
652
653 static void b43_hardware_pctl_early_init(struct b43_wldev *dev)
654 {
655 struct b43_phy *phy = &dev->phy;
656
657 if (!b43_has_hardware_pctl(phy)) {
658 b43_phy_write(dev, 0x047A, 0xC111);
659 return;
660 }
661
662 b43_phy_write(dev, 0x0036, b43_phy_read(dev, 0x0036) & 0xFEFF);
663 b43_phy_write(dev, 0x002F, 0x0202);
664 b43_phy_write(dev, 0x047C, b43_phy_read(dev, 0x047C) | 0x0002);
665 b43_phy_write(dev, 0x047A, b43_phy_read(dev, 0x047A) | 0xF000);
666 if (phy->radio_ver == 0x2050 && phy->radio_rev == 8) {
667 b43_phy_write(dev, 0x047A, (b43_phy_read(dev, 0x047A)
668 & 0xFF0F) | 0x0010);
669 b43_phy_write(dev, 0x005D, b43_phy_read(dev, 0x005D)
670 | 0x8000);
671 b43_phy_write(dev, 0x004E, (b43_phy_read(dev, 0x004E)
672 & 0xFFC0) | 0x0010);
673 b43_phy_write(dev, 0x002E, 0xC07F);
674 b43_phy_write(dev, 0x0036, b43_phy_read(dev, 0x0036)
675 | 0x0400);
676 } else {
677 b43_phy_write(dev, 0x0036, b43_phy_read(dev, 0x0036)
678 | 0x0200);
679 b43_phy_write(dev, 0x0036, b43_phy_read(dev, 0x0036)
680 | 0x0400);
681 b43_phy_write(dev, 0x005D, b43_phy_read(dev, 0x005D)
682 & 0x7FFF);
683 b43_phy_write(dev, 0x004F, b43_phy_read(dev, 0x004F)
684 & 0xFFFE);
685 b43_phy_write(dev, 0x004E, (b43_phy_read(dev, 0x004E)
686 & 0xFFC0) | 0x0010);
687 b43_phy_write(dev, 0x002E, 0xC07F);
688 b43_phy_write(dev, 0x047A, (b43_phy_read(dev, 0x047A)
689 & 0xFF0F) | 0x0010);
690 }
691 }
692
693 /* Intialize B/G PHY power control
694 * as described in http://bcm-specs.sipsolutions.net/InitPowerControl
695 */
696 static void b43_phy_init_pctl(struct b43_wldev *dev)
697 {
698 struct ssb_bus *bus = dev->dev->bus;
699 struct b43_phy *phy = &dev->phy;
700 struct b43_rfatt old_rfatt;
701 struct b43_bbatt old_bbatt;
702 u8 old_tx_control = 0;
703
704 if ((bus->boardinfo.vendor == SSB_BOARDVENDOR_BCM) &&
705 (bus->boardinfo.type == SSB_BOARD_BU4306))
706 return;
707
708 b43_phy_write(dev, 0x0028, 0x8018);
709
710 /* This does something with the Analog... */
711 b43_write16(dev, B43_MMIO_PHY0, b43_read16(dev, B43_MMIO_PHY0)
712 & 0xFFDF);
713
714 if (phy->type == B43_PHYTYPE_G && !phy->gmode)
715 return;
716 b43_hardware_pctl_early_init(dev);
717 if (phy->cur_idle_tssi == 0) {
718 if (phy->radio_ver == 0x2050 && phy->analog == 0) {
719 b43_radio_write16(dev, 0x0076,
720 (b43_radio_read16(dev, 0x0076)
721 & 0x00F7) | 0x0084);
722 } else {
723 struct b43_rfatt rfatt;
724 struct b43_bbatt bbatt;
725
726 memcpy(&old_rfatt, &phy->rfatt, sizeof(old_rfatt));
727 memcpy(&old_bbatt, &phy->bbatt, sizeof(old_bbatt));
728 old_tx_control = phy->tx_control;
729
730 bbatt.att = 11;
731 if (phy->radio_rev == 8) {
732 rfatt.att = 15;
733 rfatt.with_padmix = 1;
734 } else {
735 rfatt.att = 9;
736 rfatt.with_padmix = 0;
737 }
738 b43_set_txpower_g(dev, &bbatt, &rfatt, 0);
739 }
740 b43_dummy_transmission(dev);
741 phy->cur_idle_tssi = b43_phy_read(dev, B43_PHY_ITSSI);
742 if (B43_DEBUG) {
743 /* Current-Idle-TSSI sanity check. */
744 if (abs(phy->cur_idle_tssi - phy->tgt_idle_tssi) >= 20) {
745 b43dbg(dev->wl,
746 "!WARNING! Idle-TSSI phy->cur_idle_tssi "
747 "measuring failed. (cur=%d, tgt=%d). Disabling TX power "
748 "adjustment.\n", phy->cur_idle_tssi,
749 phy->tgt_idle_tssi);
750 phy->cur_idle_tssi = 0;
751 }
752 }
753 if (phy->radio_ver == 0x2050 && phy->analog == 0) {
754 b43_radio_write16(dev, 0x0076,
755 b43_radio_read16(dev, 0x0076)
756 & 0xFF7B);
757 } else {
758 b43_set_txpower_g(dev, &old_bbatt,
759 &old_rfatt, old_tx_control);
760 }
761 }
762 b43_hardware_pctl_init(dev);
763 b43_shm_clear_tssi(dev);
764 }
765
766 static void b43_phy_agcsetup(struct b43_wldev *dev)
767 {
768 struct b43_phy *phy = &dev->phy;
769 u16 offset = 0x0000;
770
771 if (phy->rev == 1)
772 offset = 0x4C00;
773
774 b43_ofdmtab_write16(dev, offset, 0, 0x00FE);
775 b43_ofdmtab_write16(dev, offset, 1, 0x000D);
776 b43_ofdmtab_write16(dev, offset, 2, 0x0013);
777 b43_ofdmtab_write16(dev, offset, 3, 0x0019);
778
779 if (phy->rev == 1) {
780 b43_ofdmtab_write16(dev, 0x1800, 0, 0x2710);
781 b43_ofdmtab_write16(dev, 0x1801, 0, 0x9B83);
782 b43_ofdmtab_write16(dev, 0x1802, 0, 0x9B83);
783 b43_ofdmtab_write16(dev, 0x1803, 0, 0x0F8D);
784 b43_phy_write(dev, 0x0455, 0x0004);
785 }
786
787 b43_phy_write(dev, 0x04A5, (b43_phy_read(dev, 0x04A5)
788 & 0x00FF) | 0x5700);
789 b43_phy_write(dev, 0x041A, (b43_phy_read(dev, 0x041A)
790 & 0xFF80) | 0x000F);
791 b43_phy_write(dev, 0x041A, (b43_phy_read(dev, 0x041A)
792 & 0xC07F) | 0x2B80);
793 b43_phy_write(dev, 0x048C, (b43_phy_read(dev, 0x048C)
794 & 0xF0FF) | 0x0300);
795
796 b43_radio_write16(dev, 0x007A, b43_radio_read16(dev, 0x007A)
797 | 0x0008);
798
799 b43_phy_write(dev, 0x04A0, (b43_phy_read(dev, 0x04A0)
800 & 0xFFF0) | 0x0008);
801 b43_phy_write(dev, 0x04A1, (b43_phy_read(dev, 0x04A1)
802 & 0xF0FF) | 0x0600);
803 b43_phy_write(dev, 0x04A2, (b43_phy_read(dev, 0x04A2)
804 & 0xF0FF) | 0x0700);
805 b43_phy_write(dev, 0x04A0, (b43_phy_read(dev, 0x04A0)
806 & 0xF0FF) | 0x0100);
807
808 if (phy->rev == 1) {
809 b43_phy_write(dev, 0x04A2, (b43_phy_read(dev, 0x04A2)
810 & 0xFFF0) | 0x0007);
811 }
812
813 b43_phy_write(dev, 0x0488, (b43_phy_read(dev, 0x0488)
814 & 0xFF00) | 0x001C);
815 b43_phy_write(dev, 0x0488, (b43_phy_read(dev, 0x0488)
816 & 0xC0FF) | 0x0200);
817 b43_phy_write(dev, 0x0496, (b43_phy_read(dev, 0x0496)
818 & 0xFF00) | 0x001C);
819 b43_phy_write(dev, 0x0489, (b43_phy_read(dev, 0x0489)
820 & 0xFF00) | 0x0020);
821 b43_phy_write(dev, 0x0489, (b43_phy_read(dev, 0x0489)
822 & 0xC0FF) | 0x0200);
823 b43_phy_write(dev, 0x0482, (b43_phy_read(dev, 0x0482)
824 & 0xFF00) | 0x002E);
825 b43_phy_write(dev, 0x0496, (b43_phy_read(dev, 0x0496)
826 & 0x00FF) | 0x1A00);
827 b43_phy_write(dev, 0x0481, (b43_phy_read(dev, 0x0481)
828 & 0xFF00) | 0x0028);
829 b43_phy_write(dev, 0x0481, (b43_phy_read(dev, 0x0481)
830 & 0x00FF) | 0x2C00);
831
832 if (phy->rev == 1) {
833 b43_phy_write(dev, 0x0430, 0x092B);
834 b43_phy_write(dev, 0x041B, (b43_phy_read(dev, 0x041B)
835 & 0xFFE1) | 0x0002);
836 } else {
837 b43_phy_write(dev, 0x041B, b43_phy_read(dev, 0x041B)
838 & 0xFFE1);
839 b43_phy_write(dev, 0x041F, 0x287A);
840 b43_phy_write(dev, 0x0420, (b43_phy_read(dev, 0x0420)
841 & 0xFFF0) | 0x0004);
842 }
843
844 if (phy->rev >= 6) {
845 b43_phy_write(dev, 0x0422, 0x287A);
846 b43_phy_write(dev, 0x0420, (b43_phy_read(dev, 0x0420)
847 & 0x0FFF) | 0x3000);
848 }
849
850 b43_phy_write(dev, 0x04A8, (b43_phy_read(dev, 0x04A8)
851 & 0x8080) | 0x7874);
852 b43_phy_write(dev, 0x048E, 0x1C00);
853
854 offset = 0x0800;
855 if (phy->rev == 1) {
856 offset = 0x5400;
857 b43_phy_write(dev, 0x04AB, (b43_phy_read(dev, 0x04AB)
858 & 0xF0FF) | 0x0600);
859 b43_phy_write(dev, 0x048B, 0x005E);
860 b43_phy_write(dev, 0x048C, (b43_phy_read(dev, 0x048C)
861 & 0xFF00) | 0x001E);
862 b43_phy_write(dev, 0x048D, 0x0002);
863 }
864 b43_ofdmtab_write16(dev, offset, 0, 0x00);
865 b43_ofdmtab_write16(dev, offset, 1, 0x07);
866 b43_ofdmtab_write16(dev, offset, 2, 0x10);
867 b43_ofdmtab_write16(dev, offset, 3, 0x1C);
868
869 if (phy->rev >= 6) {
870 b43_phy_write(dev, 0x0426, b43_phy_read(dev, 0x0426)
871 & 0xFFFC);
872 b43_phy_write(dev, 0x0426, b43_phy_read(dev, 0x0426)
873 & 0xEFFF);
874 }
875 }
876
877 static void b43_phy_setupg(struct b43_wldev *dev)
878 {
879 struct ssb_bus *bus = dev->dev->bus;
880 struct b43_phy *phy = &dev->phy;
881 u16 i;
882
883 B43_WARN_ON(phy->type != B43_PHYTYPE_G);
884 if (phy->rev == 1) {
885 b43_phy_write(dev, 0x0406, 0x4F19);
886 b43_phy_write(dev, B43_PHY_G_CRS,
887 (b43_phy_read(dev, B43_PHY_G_CRS) & 0xFC3F) |
888 0x0340);
889 b43_phy_write(dev, 0x042C, 0x005A);
890 b43_phy_write(dev, 0x0427, 0x001A);
891
892 for (i = 0; i < B43_TAB_FINEFREQG_SIZE; i++)
893 b43_ofdmtab_write16(dev, 0x5800, i,
894 b43_tab_finefreqg[i]);
895 for (i = 0; i < B43_TAB_NOISEG1_SIZE; i++)
896 b43_ofdmtab_write16(dev, 0x1800, i, b43_tab_noiseg1[i]);
897 for (i = 0; i < B43_TAB_ROTOR_SIZE; i++)
898 b43_ofdmtab_write16(dev, 0x2000, i, b43_tab_rotor[i]);
899 } else {
900 /* nrssi values are signed 6-bit values. Not sure why we write 0x7654 here... */
901 b43_nrssi_hw_write(dev, 0xBA98, (s16) 0x7654);
902
903 if (phy->rev == 2) {
904 b43_phy_write(dev, 0x04C0, 0x1861);
905 b43_phy_write(dev, 0x04C1, 0x0271);
906 } else if (phy->rev > 2) {
907 b43_phy_write(dev, 0x04C0, 0x0098);
908 b43_phy_write(dev, 0x04C1, 0x0070);
909 b43_phy_write(dev, 0x04C9, 0x0080);
910 }
911 b43_phy_write(dev, 0x042B, b43_phy_read(dev, 0x042B) | 0x800);
912
913 for (i = 0; i < 64; i++)
914 b43_ofdmtab_write16(dev, 0x4000, i, i);
915 for (i = 0; i < B43_TAB_NOISEG2_SIZE; i++)
916 b43_ofdmtab_write16(dev, 0x1800, i, b43_tab_noiseg2[i]);
917 }
918
919 if (phy->rev <= 2)
920 for (i = 0; i < B43_TAB_NOISESCALEG_SIZE; i++)
921 b43_ofdmtab_write16(dev, 0x1400, i,
922 b43_tab_noisescaleg1[i]);
923 else if ((phy->rev >= 7) && (b43_phy_read(dev, 0x0449) & 0x0200))
924 for (i = 0; i < B43_TAB_NOISESCALEG_SIZE; i++)
925 b43_ofdmtab_write16(dev, 0x1400, i,
926 b43_tab_noisescaleg3[i]);
927 else
928 for (i = 0; i < B43_TAB_NOISESCALEG_SIZE; i++)
929 b43_ofdmtab_write16(dev, 0x1400, i,
930 b43_tab_noisescaleg2[i]);
931
932 if (phy->rev == 2)
933 for (i = 0; i < B43_TAB_SIGMASQR_SIZE; i++)
934 b43_ofdmtab_write16(dev, 0x5000, i,
935 b43_tab_sigmasqr1[i]);
936 else if ((phy->rev > 2) && (phy->rev <= 8))
937 for (i = 0; i < B43_TAB_SIGMASQR_SIZE; i++)
938 b43_ofdmtab_write16(dev, 0x5000, i,
939 b43_tab_sigmasqr2[i]);
940
941 if (phy->rev == 1) {
942 for (i = 0; i < B43_TAB_RETARD_SIZE; i++)
943 b43_ofdmtab_write32(dev, 0x2400, i, b43_tab_retard[i]);
944 for (i = 4; i < 20; i++)
945 b43_ofdmtab_write16(dev, 0x5400, i, 0x0020);
946 b43_phy_agcsetup(dev);
947
948 if ((bus->boardinfo.vendor == SSB_BOARDVENDOR_BCM) &&
949 (bus->boardinfo.type == SSB_BOARD_BU4306) &&
950 (bus->boardinfo.rev == 0x17))
951 return;
952
953 b43_ofdmtab_write16(dev, 0x5001, 0, 0x0002);
954 b43_ofdmtab_write16(dev, 0x5002, 0, 0x0001);
955 } else {
956 for (i = 0; i < 0x20; i++)
957 b43_ofdmtab_write16(dev, 0x1000, i, 0x0820);
958 b43_phy_agcsetup(dev);
959 b43_phy_read(dev, 0x0400); /* dummy read */
960 b43_phy_write(dev, 0x0403, 0x1000);
961 b43_ofdmtab_write16(dev, 0x3C02, 0, 0x000F);
962 b43_ofdmtab_write16(dev, 0x3C03, 0, 0x0014);
963
964 if ((bus->boardinfo.vendor == SSB_BOARDVENDOR_BCM) &&
965 (bus->boardinfo.type == SSB_BOARD_BU4306) &&
966 (bus->boardinfo.rev == 0x17))
967 return;
968
969 b43_ofdmtab_write16(dev, 0x0401, 0, 0x0002);
970 b43_ofdmtab_write16(dev, 0x0402, 0, 0x0001);
971 }
972 }
973
974 /* Initialize the noisescaletable for APHY */
975 static void b43_phy_init_noisescaletbl(struct b43_wldev *dev)
976 {
977 struct b43_phy *phy = &dev->phy;
978 int i;
979
980 for (i = 0; i < 12; i++) {
981 if (phy->rev == 2)
982 b43_ofdmtab_write16(dev, 0x1400, i, 0x6767);
983 else
984 b43_ofdmtab_write16(dev, 0x1400, i, 0x2323);
985 }
986 if (phy->rev == 2)
987 b43_ofdmtab_write16(dev, 0x1400, i, 0x6700);
988 else
989 b43_ofdmtab_write16(dev, 0x1400, i, 0x2300);
990 for (i = 0; i < 11; i++) {
991 if (phy->rev == 2)
992 b43_ofdmtab_write16(dev, 0x1400, i, 0x6767);
993 else
994 b43_ofdmtab_write16(dev, 0x1400, i, 0x2323);
995 }
996 if (phy->rev == 2)
997 b43_ofdmtab_write16(dev, 0x1400, i, 0x0067);
998 else
999 b43_ofdmtab_write16(dev, 0x1400, i, 0x0023);
1000 }
1001
1002 static void b43_phy_setupa(struct b43_wldev *dev)
1003 {
1004 struct b43_phy *phy = &dev->phy;
1005 u16 i;
1006
1007 B43_WARN_ON(phy->type != B43_PHYTYPE_A);
1008 switch (phy->rev) {
1009 case 2:
1010 b43_phy_write(dev, 0x008E, 0x3800);
1011 b43_phy_write(dev, 0x0035, 0x03FF);
1012 b43_phy_write(dev, 0x0036, 0x0400);
1013
1014 b43_ofdmtab_write16(dev, 0x3807, 0, 0x0051);
1015
1016 b43_phy_write(dev, 0x001C, 0x0FF9);
1017 b43_phy_write(dev, 0x0020, b43_phy_read(dev, 0x0020) & 0xFF0F);
1018 b43_ofdmtab_write16(dev, 0x3C0C, 0, 0x07BF);
1019 b43_radio_write16(dev, 0x0002, 0x07BF);
1020
1021 b43_phy_write(dev, 0x0024, 0x4680);
1022 b43_phy_write(dev, 0x0020, 0x0003);
1023 b43_phy_write(dev, 0x001D, 0x0F40);
1024 b43_phy_write(dev, 0x001F, 0x1C00);
1025
1026 b43_phy_write(dev, 0x002A, (b43_phy_read(dev, 0x002A)
1027 & 0x00FF) | 0x0400);
1028 b43_phy_write(dev, 0x002B, b43_phy_read(dev, 0x002B)
1029 & 0xFBFF);
1030 b43_phy_write(dev, 0x008E, 0x58C1);
1031
1032 b43_ofdmtab_write16(dev, 0x0803, 0, 0x000F);
1033 b43_ofdmtab_write16(dev, 0x0804, 0, 0x001F);
1034 b43_ofdmtab_write16(dev, 0x0805, 0, 0x002A);
1035 b43_ofdmtab_write16(dev, 0x0805, 0, 0x0030);
1036 b43_ofdmtab_write16(dev, 0x0807, 0, 0x003A);
1037
1038 b43_ofdmtab_write16(dev, 0x0000, 0, 0x0013);
1039 b43_ofdmtab_write16(dev, 0x0000, 1, 0x0013);
1040 b43_ofdmtab_write16(dev, 0x0000, 2, 0x0013);
1041 b43_ofdmtab_write16(dev, 0x0000, 3, 0x0013);
1042 b43_ofdmtab_write16(dev, 0x0000, 4, 0x0015);
1043 b43_ofdmtab_write16(dev, 0x0000, 5, 0x0015);
1044 b43_ofdmtab_write16(dev, 0x0000, 6, 0x0019);
1045
1046 b43_ofdmtab_write16(dev, 0x0404, 0, 0x0003);
1047 b43_ofdmtab_write16(dev, 0x0405, 0, 0x0003);
1048 b43_ofdmtab_write16(dev, 0x0406, 0, 0x0007);
1049
1050 for (i = 0; i < 16; i++)
1051 b43_ofdmtab_write16(dev, 0x4000, i, (0x8 + i) & 0x000F);
1052
1053 b43_ofdmtab_write16(dev, 0x3003, 0, 0x1044);
1054 b43_ofdmtab_write16(dev, 0x3004, 0, 0x7201);
1055 b43_ofdmtab_write16(dev, 0x3006, 0, 0x0040);
1056 b43_ofdmtab_write16(dev, 0x3001, 0,
1057 (b43_ofdmtab_read16(dev, 0x3001, 0) &
1058 0x0010) | 0x0008);
1059
1060 for (i = 0; i < B43_TAB_FINEFREQA_SIZE; i++)
1061 b43_ofdmtab_write16(dev, 0x5800, i,
1062 b43_tab_finefreqa[i]);
1063 for (i = 0; i < B43_TAB_NOISEA2_SIZE; i++)
1064 b43_ofdmtab_write16(dev, 0x1800, i, b43_tab_noisea2[i]);
1065 for (i = 0; i < B43_TAB_ROTOR_SIZE; i++)
1066 b43_ofdmtab_write32(dev, 0x2000, i, b43_tab_rotor[i]);
1067 b43_phy_init_noisescaletbl(dev);
1068 for (i = 0; i < B43_TAB_RETARD_SIZE; i++)
1069 b43_ofdmtab_write32(dev, 0x2400, i, b43_tab_retard[i]);
1070 break;
1071 case 3:
1072 for (i = 0; i < 64; i++)
1073 b43_ofdmtab_write16(dev, 0x4000, i, i);
1074
1075 b43_ofdmtab_write16(dev, 0x3807, 0, 0x0051);
1076
1077 b43_phy_write(dev, 0x001C, 0x0FF9);
1078 b43_phy_write(dev, 0x0020, b43_phy_read(dev, 0x0020) & 0xFF0F);
1079 b43_radio_write16(dev, 0x0002, 0x07BF);
1080
1081 b43_phy_write(dev, 0x0024, 0x4680);
1082 b43_phy_write(dev, 0x0020, 0x0003);
1083 b43_phy_write(dev, 0x001D, 0x0F40);
1084 b43_phy_write(dev, 0x001F, 0x1C00);
1085 b43_phy_write(dev, 0x002A, (b43_phy_read(dev, 0x002A)
1086 & 0x00FF) | 0x0400);
1087
1088 b43_ofdmtab_write16(dev, 0x3000, 1,
1089 (b43_ofdmtab_read16(dev, 0x3000, 1)
1090 & 0x0010) | 0x0008);
1091 for (i = 0; i < B43_TAB_NOISEA3_SIZE; i++) {
1092 b43_ofdmtab_write16(dev, 0x1800, i, b43_tab_noisea3[i]);
1093 }
1094 b43_phy_init_noisescaletbl(dev);
1095 for (i = 0; i < B43_TAB_SIGMASQR_SIZE; i++) {
1096 b43_ofdmtab_write16(dev, 0x5000, i,
1097 b43_tab_sigmasqr1[i]);
1098 }
1099
1100 b43_phy_write(dev, 0x0003, 0x1808);
1101
1102 b43_ofdmtab_write16(dev, 0x0803, 0, 0x000F);
1103 b43_ofdmtab_write16(dev, 0x0804, 0, 0x001F);
1104 b43_ofdmtab_write16(dev, 0x0805, 0, 0x002A);
1105 b43_ofdmtab_write16(dev, 0x0805, 0, 0x0030);
1106 b43_ofdmtab_write16(dev, 0x0807, 0, 0x003A);
1107
1108 b43_ofdmtab_write16(dev, 0x0000, 0, 0x0013);
1109 b43_ofdmtab_write16(dev, 0x0001, 0, 0x0013);
1110 b43_ofdmtab_write16(dev, 0x0002, 0, 0x0013);
1111 b43_ofdmtab_write16(dev, 0x0003, 0, 0x0013);
1112 b43_ofdmtab_write16(dev, 0x0004, 0, 0x0015);
1113 b43_ofdmtab_write16(dev, 0x0005, 0, 0x0015);
1114 b43_ofdmtab_write16(dev, 0x0006, 0, 0x0019);
1115
1116 b43_ofdmtab_write16(dev, 0x0404, 0, 0x0003);
1117 b43_ofdmtab_write16(dev, 0x0405, 0, 0x0003);
1118 b43_ofdmtab_write16(dev, 0x0406, 0, 0x0007);
1119
1120 b43_ofdmtab_write16(dev, 0x3C02, 0, 0x000F);
1121 b43_ofdmtab_write16(dev, 0x3C03, 0, 0x0014);
1122 break;
1123 default:
1124 B43_WARN_ON(1);
1125 }
1126 }
1127
1128 /* Initialize APHY. This is also called for the GPHY in some cases. */
1129 static void b43_phy_inita(struct b43_wldev *dev)
1130 {
1131 struct ssb_bus *bus = dev->dev->bus;
1132 struct b43_phy *phy = &dev->phy;
1133 u16 tval;
1134
1135 might_sleep();
1136
1137 if (phy->type == B43_PHYTYPE_A) {
1138 b43_phy_setupa(dev);
1139 } else {
1140 b43_phy_setupg(dev);
1141 if (phy->gmode &&
1142 (dev->dev->bus->sprom.r1.boardflags_lo & B43_BFL_PACTRL))
1143 b43_phy_write(dev, 0x046E, 0x03CF);
1144 return;
1145 }
1146
1147 b43_phy_write(dev, B43_PHY_A_CRS,
1148 (b43_phy_read(dev, B43_PHY_A_CRS) & 0xF83C) | 0x0340);
1149 b43_phy_write(dev, 0x0034, 0x0001);
1150
1151 //TODO: RSSI AGC
1152 b43_phy_write(dev, B43_PHY_A_CRS,
1153 b43_phy_read(dev, B43_PHY_A_CRS) | (1 << 14));
1154 b43_radio_init2060(dev);
1155
1156 if ((bus->boardinfo.vendor == SSB_BOARDVENDOR_BCM) &&
1157 ((bus->boardinfo.type == SSB_BOARD_BU4306) ||
1158 (bus->boardinfo.type == SSB_BOARD_BU4309))) {
1159 if (phy->lofcal == 0xFFFF) {
1160 //TODO: LOF Cal
1161 b43_radio_set_tx_iq(dev);
1162 } else
1163 b43_radio_write16(dev, 0x001E, phy->lofcal);
1164 }
1165
1166 b43_phy_write(dev, 0x007A, 0xF111);
1167
1168 if (phy->cur_idle_tssi == 0) {
1169 b43_radio_write16(dev, 0x0019, 0x0000);
1170 b43_radio_write16(dev, 0x0017, 0x0020);
1171
1172 tval = b43_ofdmtab_read16(dev, 0x3001, 0);
1173 if (phy->rev == 1) {
1174 b43_ofdmtab_write16(dev, 0x3001, 0,
1175 (b43_ofdmtab_read16(dev, 0x3001, 0)
1176 & 0xFF87)
1177 | 0x0058);
1178 } else {
1179 b43_ofdmtab_write16(dev, 0x3001, 0,
1180 (b43_ofdmtab_read16(dev, 0x3001, 0)
1181 & 0xFFC3)
1182 | 0x002C);
1183 }
1184 b43_dummy_transmission(dev);
1185 phy->cur_idle_tssi = b43_phy_read(dev, B43_PHY_A_PCTL);
1186 b43_ofdmtab_write16(dev, 0x3001, 0, tval);
1187
1188 b43_radio_set_txpower_a(dev, 0x0018);
1189 }
1190 b43_shm_clear_tssi(dev);
1191 }
1192
1193 static void b43_phy_initb2(struct b43_wldev *dev)
1194 {
1195 struct b43_phy *phy = &dev->phy;
1196 u16 offset, val;
1197
1198 b43_write16(dev, 0x03EC, 0x3F22);
1199 b43_phy_write(dev, 0x0020, 0x301C);
1200 b43_phy_write(dev, 0x0026, 0x0000);
1201 b43_phy_write(dev, 0x0030, 0x00C6);
1202 b43_phy_write(dev, 0x0088, 0x3E00);
1203 val = 0x3C3D;
1204 for (offset = 0x0089; offset < 0x00A7; offset++) {
1205 b43_phy_write(dev, offset, val);
1206 val -= 0x0202;
1207 }
1208 b43_phy_write(dev, 0x03E4, 0x3000);
1209 b43_radio_selectchannel(dev, phy->channel, 0);
1210 if (phy->radio_ver != 0x2050) {
1211 b43_radio_write16(dev, 0x0075, 0x0080);
1212 b43_radio_write16(dev, 0x0079, 0x0081);
1213 }
1214 b43_radio_write16(dev, 0x0050, 0x0020);
1215 b43_radio_write16(dev, 0x0050, 0x0023);
1216 if (phy->radio_ver == 0x2050) {
1217 b43_radio_write16(dev, 0x0050, 0x0020);
1218 b43_radio_write16(dev, 0x005A, 0x0070);
1219 b43_radio_write16(dev, 0x005B, 0x007B);
1220 b43_radio_write16(dev, 0x005C, 0x00B0);
1221 b43_radio_write16(dev, 0x007A, 0x000F);
1222 b43_phy_write(dev, 0x0038, 0x0677);
1223 b43_radio_init2050(dev);
1224 }
1225 b43_phy_write(dev, 0x0014, 0x0080);
1226 b43_phy_write(dev, 0x0032, 0x00CA);
1227 b43_phy_write(dev, 0x0032, 0x00CC);
1228 b43_phy_write(dev, 0x0035, 0x07C2);
1229 b43_lo_b_measure(dev);
1230 b43_phy_write(dev, 0x0026, 0xCC00);
1231 if (phy->radio_ver != 0x2050)
1232 b43_phy_write(dev, 0x0026, 0xCE00);
1233 b43_write16(dev, B43_MMIO_CHANNEL_EXT, 0x1000);
1234 b43_phy_write(dev, 0x002A, 0x88A3);
1235 if (phy->radio_ver != 0x2050)
1236 b43_phy_write(dev, 0x002A, 0x88C2);
1237 b43_set_txpower_g(dev, &phy->bbatt, &phy->rfatt, phy->tx_control);
1238 b43_phy_init_pctl(dev);
1239 }
1240
1241 static void b43_phy_initb4(struct b43_wldev *dev)
1242 {
1243 struct b43_phy *phy = &dev->phy;
1244 u16 offset, val;
1245
1246 b43_write16(dev, 0x03EC, 0x3F22);
1247 b43_phy_write(dev, 0x0020, 0x301C);
1248 b43_phy_write(dev, 0x0026, 0x0000);
1249 b43_phy_write(dev, 0x0030, 0x00C6);
1250 b43_phy_write(dev, 0x0088, 0x3E00);
1251 val = 0x3C3D;
1252 for (offset = 0x0089; offset < 0x00A7; offset++) {
1253 b43_phy_write(dev, offset, val);
1254 val -= 0x0202;
1255 }
1256 b43_phy_write(dev, 0x03E4, 0x3000);
1257 b43_radio_selectchannel(dev, phy->channel, 0);
1258 if (phy->radio_ver != 0x2050) {
1259 b43_radio_write16(dev, 0x0075, 0x0080);
1260 b43_radio_write16(dev, 0x0079, 0x0081);
1261 }
1262 b43_radio_write16(dev, 0x0050, 0x0020);
1263 b43_radio_write16(dev, 0x0050, 0x0023);
1264 if (phy->radio_ver == 0x2050) {
1265 b43_radio_write16(dev, 0x0050, 0x0020);
1266 b43_radio_write16(dev, 0x005A, 0x0070);
1267 b43_radio_write16(dev, 0x005B, 0x007B);
1268 b43_radio_write16(dev, 0x005C, 0x00B0);
1269 b43_radio_write16(dev, 0x007A, 0x000F);
1270 b43_phy_write(dev, 0x0038, 0x0677);
1271 b43_radio_init2050(dev);
1272 }
1273 b43_phy_write(dev, 0x0014, 0x0080);
1274 b43_phy_write(dev, 0x0032, 0x00CA);
1275 if (phy->radio_ver == 0x2050)
1276 b43_phy_write(dev, 0x0032, 0x00E0);
1277 b43_phy_write(dev, 0x0035, 0x07C2);
1278
1279 b43_lo_b_measure(dev);
1280
1281 b43_phy_write(dev, 0x0026, 0xCC00);
1282 if (phy->radio_ver == 0x2050)
1283 b43_phy_write(dev, 0x0026, 0xCE00);
1284 b43_write16(dev, B43_MMIO_CHANNEL_EXT, 0x1100);
1285 b43_phy_write(dev, 0x002A, 0x88A3);
1286 if (phy->radio_ver == 0x2050)
1287 b43_phy_write(dev, 0x002A, 0x88C2);
1288 b43_set_txpower_g(dev, &phy->bbatt, &phy->rfatt, phy->tx_control);
1289 if (dev->dev->bus->sprom.r1.boardflags_lo & B43_BFL_RSSI) {
1290 b43_calc_nrssi_slope(dev);
1291 b43_calc_nrssi_threshold(dev);
1292 }
1293 b43_phy_init_pctl(dev);
1294 }
1295
1296 static void b43_phy_initb5(struct b43_wldev *dev)
1297 {
1298 struct ssb_bus *bus = dev->dev->bus;
1299 struct b43_phy *phy = &dev->phy;
1300 u16 offset, value;
1301 u8 old_channel;
1302
1303 if (phy->analog == 1) {
1304 b43_radio_write16(dev, 0x007A, b43_radio_read16(dev, 0x007A)
1305 | 0x0050);
1306 }
1307 if ((bus->boardinfo.vendor != SSB_BOARDVENDOR_BCM) &&
1308 (bus->boardinfo.type != SSB_BOARD_BU4306)) {
1309 value = 0x2120;
1310 for (offset = 0x00A8; offset < 0x00C7; offset++) {
1311 b43_phy_write(dev, offset, value);
1312 value += 0x202;
1313 }
1314 }
1315 b43_phy_write(dev, 0x0035, (b43_phy_read(dev, 0x0035) & 0xF0FF)
1316 | 0x0700);
1317 if (phy->radio_ver == 0x2050)
1318 b43_phy_write(dev, 0x0038, 0x0667);
1319
1320 if (phy->gmode || phy->rev >= 2) {
1321 if (phy->radio_ver == 0x2050) {
1322 b43_radio_write16(dev, 0x007A,
1323 b43_radio_read16(dev, 0x007A)
1324 | 0x0020);
1325 b43_radio_write16(dev, 0x0051,
1326 b43_radio_read16(dev, 0x0051)
1327 | 0x0004);
1328 }
1329 b43_write16(dev, B43_MMIO_PHY_RADIO, 0x0000);
1330
1331 b43_phy_write(dev, 0x0802, b43_phy_read(dev, 0x0802) | 0x0100);
1332 b43_phy_write(dev, 0x042B, b43_phy_read(dev, 0x042B) | 0x2000);
1333
1334 b43_phy_write(dev, 0x001C, 0x186A);
1335
1336 b43_phy_write(dev, 0x0013,
1337 (b43_phy_read(dev, 0x0013) & 0x00FF) | 0x1900);
1338 b43_phy_write(dev, 0x0035,
1339 (b43_phy_read(dev, 0x0035) & 0xFFC0) | 0x0064);
1340 b43_phy_write(dev, 0x005D,
1341 (b43_phy_read(dev, 0x005D) & 0xFF80) | 0x000A);
1342 }
1343
1344 if (dev->bad_frames_preempt) {
1345 b43_phy_write(dev, B43_PHY_RADIO_BITFIELD,
1346 b43_phy_read(dev,
1347 B43_PHY_RADIO_BITFIELD) | (1 << 11));
1348 }
1349
1350 if (phy->analog == 1) {
1351 b43_phy_write(dev, 0x0026, 0xCE00);
1352 b43_phy_write(dev, 0x0021, 0x3763);
1353 b43_phy_write(dev, 0x0022, 0x1BC3);
1354 b43_phy_write(dev, 0x0023, 0x06F9);
1355 b43_phy_write(dev, 0x0024, 0x037E);
1356 } else
1357 b43_phy_write(dev, 0x0026, 0xCC00);
1358 b43_phy_write(dev, 0x0030, 0x00C6);
1359 b43_write16(dev, 0x03EC, 0x3F22);
1360
1361 if (phy->analog == 1)
1362 b43_phy_write(dev, 0x0020, 0x3E1C);
1363 else
1364 b43_phy_write(dev, 0x0020, 0x301C);
1365
1366 if (phy->analog == 0)
1367 b43_write16(dev, 0x03E4, 0x3000);
1368
1369 old_channel = phy->channel;
1370 /* Force to channel 7, even if not supported. */
1371 b43_radio_selectchannel(dev, 7, 0);
1372
1373 if (phy->radio_ver != 0x2050) {
1374 b43_radio_write16(dev, 0x0075, 0x0080);
1375 b43_radio_write16(dev, 0x0079, 0x0081);
1376 }
1377
1378 b43_radio_write16(dev, 0x0050, 0x0020);
1379 b43_radio_write16(dev, 0x0050, 0x0023);
1380
1381 if (phy->radio_ver == 0x2050) {
1382 b43_radio_write16(dev, 0x0050, 0x0020);
1383 b43_radio_write16(dev, 0x005A, 0x0070);
1384 }
1385
1386 b43_radio_write16(dev, 0x005B, 0x007B);
1387 b43_radio_write16(dev, 0x005C, 0x00B0);
1388
1389 b43_radio_write16(dev, 0x007A, b43_radio_read16(dev, 0x007A) | 0x0007);
1390
1391 b43_radio_selectchannel(dev, old_channel, 0);
1392
1393 b43_phy_write(dev, 0x0014, 0x0080);
1394 b43_phy_write(dev, 0x0032, 0x00CA);
1395 b43_phy_write(dev, 0x002A, 0x88A3);
1396
1397 b43_set_txpower_g(dev, &phy->bbatt, &phy->rfatt, phy->tx_control);
1398
1399 if (phy->radio_ver == 0x2050)
1400 b43_radio_write16(dev, 0x005D, 0x000D);
1401
1402 b43_write16(dev, 0x03E4, (b43_read16(dev, 0x03E4) & 0xFFC0) | 0x0004);
1403 }
1404
1405 static void b43_phy_initb6(struct b43_wldev *dev)
1406 {
1407 struct b43_phy *phy = &dev->phy;
1408 u16 offset, val;
1409 u8 old_channel;
1410
1411 b43_phy_write(dev, 0x003E, 0x817A);
1412 b43_radio_write16(dev, 0x007A,
1413 (b43_radio_read16(dev, 0x007A) | 0x0058));
1414 if (phy->radio_rev == 4 || phy->radio_rev == 5) {
1415 b43_radio_write16(dev, 0x51, 0x37);
1416 b43_radio_write16(dev, 0x52, 0x70);
1417 b43_radio_write16(dev, 0x53, 0xB3);
1418 b43_radio_write16(dev, 0x54, 0x9B);
1419 b43_radio_write16(dev, 0x5A, 0x88);
1420 b43_radio_write16(dev, 0x5B, 0x88);
1421 b43_radio_write16(dev, 0x5D, 0x88);
1422 b43_radio_write16(dev, 0x5E, 0x88);
1423 b43_radio_write16(dev, 0x7D, 0x88);
1424 b43_hf_write(dev, b43_hf_read(dev)
1425 | B43_HF_TSSIRPSMW);
1426 }
1427 B43_WARN_ON(phy->radio_rev == 6 || phy->radio_rev == 7); /* We had code for these revs here... */
1428 if (phy->radio_rev == 8) {
1429 b43_radio_write16(dev, 0x51, 0);
1430 b43_radio_write16(dev, 0x52, 0x40);
1431 b43_radio_write16(dev, 0x53, 0xB7);
1432 b43_radio_write16(dev, 0x54, 0x98);
1433 b43_radio_write16(dev, 0x5A, 0x88);
1434 b43_radio_write16(dev, 0x5B, 0x6B);
1435 b43_radio_write16(dev, 0x5C, 0x0F);
1436 if (dev->dev->bus->sprom.r1.boardflags_lo & B43_BFL_ALTIQ) {
1437 b43_radio_write16(dev, 0x5D, 0xFA);
1438 b43_radio_write16(dev, 0x5E, 0xD8);
1439 } else {
1440 b43_radio_write16(dev, 0x5D, 0xF5);
1441 b43_radio_write16(dev, 0x5E, 0xB8);
1442 }
1443 b43_radio_write16(dev, 0x0073, 0x0003);
1444 b43_radio_write16(dev, 0x007D, 0x00A8);
1445 b43_radio_write16(dev, 0x007C, 0x0001);
1446 b43_radio_write16(dev, 0x007E, 0x0008);
1447 }
1448 val = 0x1E1F;
1449 for (offset = 0x0088; offset < 0x0098; offset++) {
1450 b43_phy_write(dev, offset, val);
1451 val -= 0x0202;
1452 }
1453 val = 0x3E3F;
1454 for (offset = 0x0098; offset < 0x00A8; offset++) {
1455 b43_phy_write(dev, offset, val);
1456 val -= 0x0202;
1457 }
1458 val = 0x2120;
1459 for (offset = 0x00A8; offset < 0x00C8; offset++) {
1460 b43_phy_write(dev, offset, (val & 0x3F3F));
1461 val += 0x0202;
1462 }
1463 if (phy->type == B43_PHYTYPE_G) {
1464 b43_radio_write16(dev, 0x007A,
1465 b43_radio_read16(dev, 0x007A) | 0x0020);
1466 b43_radio_write16(dev, 0x0051,
1467 b43_radio_read16(dev, 0x0051) | 0x0004);
1468 b43_phy_write(dev, 0x0802, b43_phy_read(dev, 0x0802) | 0x0100);
1469 b43_phy_write(dev, 0x042B, b43_phy_read(dev, 0x042B) | 0x2000);
1470 b43_phy_write(dev, 0x5B, 0);
1471 b43_phy_write(dev, 0x5C, 0);
1472 }
1473
1474 old_channel = phy->channel;
1475 if (old_channel >= 8)
1476 b43_radio_selectchannel(dev, 1, 0);
1477 else
1478 b43_radio_selectchannel(dev, 13, 0);
1479
1480 b43_radio_write16(dev, 0x0050, 0x0020);
1481 b43_radio_write16(dev, 0x0050, 0x0023);
1482 udelay(40);
1483 if (phy->radio_rev < 6 || phy->radio_rev == 8) {
1484 b43_radio_write16(dev, 0x7C, (b43_radio_read16(dev, 0x7C)
1485 | 0x0002));
1486 b43_radio_write16(dev, 0x50, 0x20);
1487 }
1488 if (phy->radio_rev <= 2) {
1489 b43_radio_write16(dev, 0x7C, 0x20);
1490 b43_radio_write16(dev, 0x5A, 0x70);
1491 b43_radio_write16(dev, 0x5B, 0x7B);
1492 b43_radio_write16(dev, 0x5C, 0xB0);
1493 }
1494 b43_radio_write16(dev, 0x007A,
1495 (b43_radio_read16(dev, 0x007A) & 0x00F8) | 0x0007);
1496
1497 b43_radio_selectchannel(dev, old_channel, 0);
1498
1499 b43_phy_write(dev, 0x0014, 0x0200);
1500 if (phy->radio_rev >= 6)
1501 b43_phy_write(dev, 0x2A, 0x88C2);
1502 else
1503 b43_phy_write(dev, 0x2A, 0x8AC0);
1504 b43_phy_write(dev, 0x0038, 0x0668);
1505 b43_set_txpower_g(dev, &phy->bbatt, &phy->rfatt, phy->tx_control);
1506 if (phy->radio_rev <= 5) {
1507 b43_phy_write(dev, 0x5D, (b43_phy_read(dev, 0x5D)
1508 & 0xFF80) | 0x0003);
1509 }
1510 if (phy->radio_rev <= 2)
1511 b43_radio_write16(dev, 0x005D, 0x000D);
1512
1513 if (phy->analog == 4) {
1514 b43_write16(dev, 0x3E4, 9);
1515 b43_phy_write(dev, 0x61, b43_phy_read(dev, 0x61)
1516 & 0x0FFF);
1517 } else {
1518 b43_phy_write(dev, 0x0002, (b43_phy_read(dev, 0x0002) & 0xFFC0)
1519 | 0x0004);
1520 }
1521 if (phy->type == B43_PHYTYPE_B) {
1522 b43_write16(dev, 0x03E6, 0x8140);
1523 b43_phy_write(dev, 0x0016, 0x0410);
1524 b43_phy_write(dev, 0x0017, 0x0820);
1525 b43_phy_write(dev, 0x0062, 0x0007);
1526 b43_radio_init2050(dev);
1527 b43_lo_g_measure(dev);
1528 if (dev->dev->bus->sprom.r1.boardflags_lo & B43_BFL_RSSI) {
1529 b43_calc_nrssi_slope(dev);
1530 b43_calc_nrssi_threshold(dev);
1531 }
1532 b43_phy_init_pctl(dev);
1533 } else if (phy->type == B43_PHYTYPE_G)
1534 b43_write16(dev, 0x03E6, 0x0);
1535 }
1536
1537 static void b43_calc_loopback_gain(struct b43_wldev *dev)
1538 {
1539 struct b43_phy *phy = &dev->phy;
1540 u16 backup_phy[16] = { 0 };
1541 u16 backup_radio[3];
1542 u16 backup_bband;
1543 u16 i, j, loop_i_max;
1544 u16 trsw_rx;
1545 u16 loop1_outer_done, loop1_inner_done;
1546
1547 backup_phy[0] = b43_phy_read(dev, B43_PHY_CRS0);
1548 backup_phy[1] = b43_phy_read(dev, B43_PHY_CCKBBANDCFG);
1549 backup_phy[2] = b43_phy_read(dev, B43_PHY_RFOVER);
1550 backup_phy[3] = b43_phy_read(dev, B43_PHY_RFOVERVAL);
1551 if (phy->rev != 1) { /* Not in specs, but needed to prevent PPC machine check */
1552 backup_phy[4] = b43_phy_read(dev, B43_PHY_ANALOGOVER);
1553 backup_phy[5] = b43_phy_read(dev, B43_PHY_ANALOGOVERVAL);
1554 }
1555 backup_phy[6] = b43_phy_read(dev, B43_PHY_BASE(0x5A));
1556 backup_phy[7] = b43_phy_read(dev, B43_PHY_BASE(0x59));
1557 backup_phy[8] = b43_phy_read(dev, B43_PHY_BASE(0x58));
1558 backup_phy[9] = b43_phy_read(dev, B43_PHY_BASE(0x0A));
1559 backup_phy[10] = b43_phy_read(dev, B43_PHY_BASE(0x03));
1560 backup_phy[11] = b43_phy_read(dev, B43_PHY_LO_MASK);
1561 backup_phy[12] = b43_phy_read(dev, B43_PHY_LO_CTL);
1562 backup_phy[13] = b43_phy_read(dev, B43_PHY_BASE(0x2B));
1563 backup_phy[14] = b43_phy_read(dev, B43_PHY_PGACTL);
1564 backup_phy[15] = b43_phy_read(dev, B43_PHY_LO_LEAKAGE);
1565 backup_bband = phy->bbatt.att;
1566 backup_radio[0] = b43_radio_read16(dev, 0x52);
1567 backup_radio[1] = b43_radio_read16(dev, 0x43);
1568 backup_radio[2] = b43_radio_read16(dev, 0x7A);
1569
1570 b43_phy_write(dev, B43_PHY_CRS0,
1571 b43_phy_read(dev, B43_PHY_CRS0) & 0x3FFF);
1572 b43_phy_write(dev, B43_PHY_CCKBBANDCFG,
1573 b43_phy_read(dev, B43_PHY_CCKBBANDCFG) | 0x8000);
1574 b43_phy_write(dev, B43_PHY_RFOVER,
1575 b43_phy_read(dev, B43_PHY_RFOVER) | 0x0002);
1576 b43_phy_write(dev, B43_PHY_RFOVERVAL,
1577 b43_phy_read(dev, B43_PHY_RFOVERVAL) & 0xFFFD);
1578 b43_phy_write(dev, B43_PHY_RFOVER,
1579 b43_phy_read(dev, B43_PHY_RFOVER) | 0x0001);
1580 b43_phy_write(dev, B43_PHY_RFOVERVAL,
1581 b43_phy_read(dev, B43_PHY_RFOVERVAL) & 0xFFFE);
1582 if (phy->rev != 1) { /* Not in specs, but needed to prevent PPC machine check */
1583 b43_phy_write(dev, B43_PHY_ANALOGOVER,
1584 b43_phy_read(dev, B43_PHY_ANALOGOVER) | 0x0001);
1585 b43_phy_write(dev, B43_PHY_ANALOGOVERVAL,
1586 b43_phy_read(dev,
1587 B43_PHY_ANALOGOVERVAL) & 0xFFFE);
1588 b43_phy_write(dev, B43_PHY_ANALOGOVER,
1589 b43_phy_read(dev, B43_PHY_ANALOGOVER) | 0x0002);
1590 b43_phy_write(dev, B43_PHY_ANALOGOVERVAL,
1591 b43_phy_read(dev,
1592 B43_PHY_ANALOGOVERVAL) & 0xFFFD);
1593 }
1594 b43_phy_write(dev, B43_PHY_RFOVER,
1595 b43_phy_read(dev, B43_PHY_RFOVER) | 0x000C);
1596 b43_phy_write(dev, B43_PHY_RFOVERVAL,
1597 b43_phy_read(dev, B43_PHY_RFOVERVAL) | 0x000C);
1598 b43_phy_write(dev, B43_PHY_RFOVER,
1599 b43_phy_read(dev, B43_PHY_RFOVER) | 0x0030);
1600 b43_phy_write(dev, B43_PHY_RFOVERVAL,
1601 (b43_phy_read(dev, B43_PHY_RFOVERVAL)
1602 & 0xFFCF) | 0x10);
1603
1604 b43_phy_write(dev, B43_PHY_BASE(0x5A), 0x0780);
1605 b43_phy_write(dev, B43_PHY_BASE(0x59), 0xC810);
1606 b43_phy_write(dev, B43_PHY_BASE(0x58), 0x000D);
1607
1608 b43_phy_write(dev, B43_PHY_BASE(0x0A),
1609 b43_phy_read(dev, B43_PHY_BASE(0x0A)) | 0x2000);
1610 if (phy->rev != 1) { /* Not in specs, but needed to prevent PPC machine check */
1611 b43_phy_write(dev, B43_PHY_ANALOGOVER,
1612 b43_phy_read(dev, B43_PHY_ANALOGOVER) | 0x0004);
1613 b43_phy_write(dev, B43_PHY_ANALOGOVERVAL,
1614 b43_phy_read(dev,
1615 B43_PHY_ANALOGOVERVAL) & 0xFFFB);
1616 }
1617 b43_phy_write(dev, B43_PHY_BASE(0x03),
1618 (b43_phy_read(dev, B43_PHY_BASE(0x03))
1619 & 0xFF9F) | 0x40);
1620
1621 if (phy->radio_rev == 8) {
1622 b43_radio_write16(dev, 0x43, 0x000F);
1623 } else {
1624 b43_radio_write16(dev, 0x52, 0);
1625 b43_radio_write16(dev, 0x43, (b43_radio_read16(dev, 0x43)
1626 & 0xFFF0) | 0x9);
1627 }
1628 b43_phy_set_baseband_attenuation(dev, 11);
1629
1630 if (phy->rev >= 3)
1631 b43_phy_write(dev, B43_PHY_LO_MASK, 0xC020);
1632 else
1633 b43_phy_write(dev, B43_PHY_LO_MASK, 0x8020);
1634 b43_phy_write(dev, B43_PHY_LO_CTL, 0);
1635
1636 b43_phy_write(dev, B43_PHY_BASE(0x2B),
1637 (b43_phy_read(dev, B43_PHY_BASE(0x2B))
1638 & 0xFFC0) | 0x01);
1639 b43_phy_write(dev, B43_PHY_BASE(0x2B),
1640 (b43_phy_read(dev, B43_PHY_BASE(0x2B))
1641 & 0xC0FF) | 0x800);
1642
1643 b43_phy_write(dev, B43_PHY_RFOVER,
1644 b43_phy_read(dev, B43_PHY_RFOVER) | 0x0100);
1645 b43_phy_write(dev, B43_PHY_RFOVERVAL,
1646 b43_phy_read(dev, B43_PHY_RFOVERVAL) & 0xCFFF);
1647
1648 if (dev->dev->bus->sprom.r1.boardflags_lo & B43_BFL_EXTLNA) {
1649 if (phy->rev >= 7) {
1650 b43_phy_write(dev, B43_PHY_RFOVER,
1651 b43_phy_read(dev, B43_PHY_RFOVER)
1652 | 0x0800);
1653 b43_phy_write(dev, B43_PHY_RFOVERVAL,
1654 b43_phy_read(dev, B43_PHY_RFOVERVAL)
1655 | 0x8000);
1656 }
1657 }
1658 b43_radio_write16(dev, 0x7A, b43_radio_read16(dev, 0x7A)
1659 & 0x00F7);
1660
1661 j = 0;
1662 loop_i_max = (phy->radio_rev == 8) ? 15 : 9;
1663 for (i = 0; i < loop_i_max; i++) {
1664 for (j = 0; j < 16; j++) {
1665 b43_radio_write16(dev, 0x43, i);
1666 b43_phy_write(dev, B43_PHY_RFOVERVAL,
1667 (b43_phy_read(dev, B43_PHY_RFOVERVAL)
1668 & 0xF0FF) | (j << 8));
1669 b43_phy_write(dev, B43_PHY_PGACTL,
1670 (b43_phy_read(dev, B43_PHY_PGACTL)
1671 & 0x0FFF) | 0xA000);
1672 b43_phy_write(dev, B43_PHY_PGACTL,
1673 b43_phy_read(dev, B43_PHY_PGACTL)
1674 | 0xF000);
1675 udelay(20);
1676 if (b43_phy_read(dev, B43_PHY_LO_LEAKAGE) >= 0xDFC)
1677 goto exit_loop1;
1678 }
1679 }
1680 exit_loop1:
1681 loop1_outer_done = i;
1682 loop1_inner_done = j;
1683 if (j >= 8) {
1684 b43_phy_write(dev, B43_PHY_RFOVERVAL,
1685 b43_phy_read(dev, B43_PHY_RFOVERVAL)
1686 | 0x30);
1687 trsw_rx = 0x1B;
1688 for (j = j - 8; j < 16; j++) {
1689 b43_phy_write(dev, B43_PHY_RFOVERVAL,
1690 (b43_phy_read(dev, B43_PHY_RFOVERVAL)
1691 & 0xF0FF) | (j << 8));
1692 b43_phy_write(dev, B43_PHY_PGACTL,
1693 (b43_phy_read(dev, B43_PHY_PGACTL)
1694 & 0x0FFF) | 0xA000);
1695 b43_phy_write(dev, B43_PHY_PGACTL,
1696 b43_phy_read(dev, B43_PHY_PGACTL)
1697 | 0xF000);
1698 udelay(20);
1699 trsw_rx -= 3;
1700 if (b43_phy_read(dev, B43_PHY_LO_LEAKAGE) >= 0xDFC)
1701 goto exit_loop2;
1702 }
1703 } else
1704 trsw_rx = 0x18;
1705 exit_loop2:
1706
1707 if (phy->rev != 1) { /* Not in specs, but needed to prevent PPC machine check */
1708 b43_phy_write(dev, B43_PHY_ANALOGOVER, backup_phy[4]);
1709 b43_phy_write(dev, B43_PHY_ANALOGOVERVAL, backup_phy[5]);
1710 }
1711 b43_phy_write(dev, B43_PHY_BASE(0x5A), backup_phy[6]);
1712 b43_phy_write(dev, B43_PHY_BASE(0x59), backup_phy[7]);
1713 b43_phy_write(dev, B43_PHY_BASE(0x58), backup_phy[8]);
1714 b43_phy_write(dev, B43_PHY_BASE(0x0A), backup_phy[9]);
1715 b43_phy_write(dev, B43_PHY_BASE(0x03), backup_phy[10]);
1716 b43_phy_write(dev, B43_PHY_LO_MASK, backup_phy[11]);
1717 b43_phy_write(dev, B43_PHY_LO_CTL, backup_phy[12]);
1718 b43_phy_write(dev, B43_PHY_BASE(0x2B), backup_phy[13]);
1719 b43_phy_write(dev, B43_PHY_PGACTL, backup_phy[14]);
1720
1721 b43_phy_set_baseband_attenuation(dev, backup_bband);
1722
1723 b43_radio_write16(dev, 0x52, backup_radio[0]);
1724 b43_radio_write16(dev, 0x43, backup_radio[1]);
1725 b43_radio_write16(dev, 0x7A, backup_radio[2]);
1726
1727 b43_phy_write(dev, B43_PHY_RFOVER, backup_phy[2] | 0x0003);
1728 udelay(10);
1729 b43_phy_write(dev, B43_PHY_RFOVER, backup_phy[2]);
1730 b43_phy_write(dev, B43_PHY_RFOVERVAL, backup_phy[3]);
1731 b43_phy_write(dev, B43_PHY_CRS0, backup_phy[0]);
1732 b43_phy_write(dev, B43_PHY_CCKBBANDCFG, backup_phy[1]);
1733
1734 phy->max_lb_gain =
1735 ((loop1_inner_done * 6) - (loop1_outer_done * 4)) - 11;
1736 phy->trsw_rx_gain = trsw_rx * 2;
1737 }
1738
1739 static void b43_phy_initg(struct b43_wldev *dev)
1740 {
1741 struct b43_phy *phy = &dev->phy;
1742 u16 tmp;
1743
1744 if (phy->rev == 1)
1745 b43_phy_initb5(dev);
1746 else
1747 b43_phy_initb6(dev);
1748
1749 if (phy->rev >= 2 || phy->gmode)
1750 b43_phy_inita(dev);
1751
1752 if (phy->rev >= 2) {
1753 b43_phy_write(dev, B43_PHY_ANALOGOVER, 0);
1754 b43_phy_write(dev, B43_PHY_ANALOGOVERVAL, 0);
1755 }
1756 if (phy->rev == 2) {
1757 b43_phy_write(dev, B43_PHY_RFOVER, 0);
1758 b43_phy_write(dev, B43_PHY_PGACTL, 0xC0);
1759 }
1760 if (phy->rev > 5) {
1761 b43_phy_write(dev, B43_PHY_RFOVER, 0x400);
1762 b43_phy_write(dev, B43_PHY_PGACTL, 0xC0);
1763 }
1764 if (phy->gmode || phy->rev >= 2) {
1765 tmp = b43_phy_read(dev, B43_PHY_VERSION_OFDM);
1766 tmp &= B43_PHYVER_VERSION;
1767 if (tmp == 3 || tmp == 5) {
1768 b43_phy_write(dev, B43_PHY_OFDM(0xC2), 0x1816);
1769 b43_phy_write(dev, B43_PHY_OFDM(0xC3), 0x8006);
1770 }
1771 if (tmp == 5) {
1772 b43_phy_write(dev, B43_PHY_OFDM(0xCC),
1773 (b43_phy_read(dev, B43_PHY_OFDM(0xCC))
1774 & 0x00FF) | 0x1F00);
1775 }
1776 }
1777 if ((phy->rev <= 2 && phy->gmode) || phy->rev >= 2)
1778 b43_phy_write(dev, B43_PHY_OFDM(0x7E), 0x78);
1779 if (phy->radio_rev == 8) {
1780 b43_phy_write(dev, B43_PHY_EXTG(0x01),
1781 b43_phy_read(dev, B43_PHY_EXTG(0x01))
1782 | 0x80);
1783 b43_phy_write(dev, B43_PHY_OFDM(0x3E),
1784 b43_phy_read(dev, B43_PHY_OFDM(0x3E))
1785 | 0x4);
1786 }
1787 if (has_loopback_gain(phy))
1788 b43_calc_loopback_gain(dev);
1789
1790 if (phy->radio_rev != 8) {
1791 if (phy->initval == 0xFFFF)
1792 phy->initval = b43_radio_init2050(dev);
1793 else
1794 b43_radio_write16(dev, 0x0078, phy->initval);
1795 }
1796 if (phy->lo_control->tx_bias == 0xFF) {
1797 b43_lo_g_measure(dev);
1798 } else {
1799 if (has_tx_magnification(phy)) {
1800 b43_radio_write16(dev, 0x52,
1801 (b43_radio_read16(dev, 0x52) & 0xFF00)
1802 | phy->lo_control->tx_bias | phy->
1803 lo_control->tx_magn);
1804 } else {
1805 b43_radio_write16(dev, 0x52,
1806 (b43_radio_read16(dev, 0x52) & 0xFFF0)
1807 | phy->lo_control->tx_bias);
1808 }
1809 if (phy->rev >= 6) {
1810 b43_phy_write(dev, B43_PHY_BASE(0x36),
1811 (b43_phy_read(dev, B43_PHY_BASE(0x36))
1812 & 0x0FFF) | (phy->lo_control->
1813 tx_bias << 12));
1814 }
1815 if (dev->dev->bus->sprom.r1.boardflags_lo & B43_BFL_PACTRL)
1816 b43_phy_write(dev, B43_PHY_BASE(0x2E), 0x8075);
1817 else
1818 b43_phy_write(dev, B43_PHY_BASE(0x2E), 0x807F);
1819 if (phy->rev < 2)
1820 b43_phy_write(dev, B43_PHY_BASE(0x2F), 0x101);
1821 else
1822 b43_phy_write(dev, B43_PHY_BASE(0x2F), 0x202);
1823 }
1824 if (phy->gmode || phy->rev >= 2) {
1825 b43_lo_g_adjust(dev);
1826 b43_phy_write(dev, B43_PHY_LO_MASK, 0x8078);
1827 }
1828
1829 if (!(dev->dev->bus->sprom.r1.boardflags_lo & B43_BFL_RSSI)) {
1830 /* The specs state to update the NRSSI LT with
1831 * the value 0x7FFFFFFF here. I think that is some weird
1832 * compiler optimization in the original driver.
1833 * Essentially, what we do here is resetting all NRSSI LT
1834 * entries to -32 (see the limit_value() in nrssi_hw_update())
1835 */
1836 b43_nrssi_hw_update(dev, 0xFFFF); //FIXME?
1837 b43_calc_nrssi_threshold(dev);
1838 } else if (phy->gmode || phy->rev >= 2) {
1839 if (phy->nrssi[0] == -1000) {
1840 B43_WARN_ON(phy->nrssi[1] != -1000);
1841 b43_calc_nrssi_slope(dev);
1842 } else
1843 b43_calc_nrssi_threshold(dev);
1844 }
1845 if (phy->radio_rev == 8)
1846 b43_phy_write(dev, B43_PHY_EXTG(0x05), 0x3230);
1847 b43_phy_init_pctl(dev);
1848 /* FIXME: The spec says in the following if, the 0 should be replaced
1849 'if OFDM may not be used in the current locale'
1850 but OFDM is legal everywhere */
1851 if ((dev->dev->bus->chip_id == 0x4306
1852 && dev->dev->bus->chip_package == 2) || 0) {
1853 b43_phy_write(dev, B43_PHY_CRS0, b43_phy_read(dev, B43_PHY_CRS0)
1854 & 0xBFFF);
1855 b43_phy_write(dev, B43_PHY_OFDM(0xC3),
1856 b43_phy_read(dev, B43_PHY_OFDM(0xC3))
1857 & 0x7FFF);
1858 }
1859 }
1860
1861 /* Set the baseband attenuation value on chip. */
1862 void b43_phy_set_baseband_attenuation(struct b43_wldev *dev,
1863 u16 baseband_attenuation)
1864 {
1865 struct b43_phy *phy = &dev->phy;
1866
1867 if (phy->analog == 0) {
1868 b43_write16(dev, B43_MMIO_PHY0, (b43_read16(dev, B43_MMIO_PHY0)
1869 & 0xFFF0) |
1870 baseband_attenuation);
1871 } else if (phy->analog > 1) {
1872 b43_phy_write(dev, B43_PHY_DACCTL,
1873 (b43_phy_read(dev, B43_PHY_DACCTL)
1874 & 0xFFC3) | (baseband_attenuation << 2));
1875 } else {
1876 b43_phy_write(dev, B43_PHY_DACCTL,
1877 (b43_phy_read(dev, B43_PHY_DACCTL)
1878 & 0xFF87) | (baseband_attenuation << 3));
1879 }
1880 }
1881
1882 /* http://bcm-specs.sipsolutions.net/EstimatePowerOut
1883 * This function converts a TSSI value to dBm in Q5.2
1884 */
1885 static s8 b43_phy_estimate_power_out(struct b43_wldev *dev, s8 tssi)
1886 {
1887 struct b43_phy *phy = &dev->phy;
1888 s8 dbm = 0;
1889 s32 tmp;
1890
1891 tmp = (phy->tgt_idle_tssi - phy->cur_idle_tssi + tssi);
1892
1893 switch (phy->type) {
1894 case B43_PHYTYPE_A:
1895 tmp += 0x80;
1896 tmp = limit_value(tmp, 0x00, 0xFF);
1897 dbm = phy->tssi2dbm[tmp];
1898 //TODO: There's a FIXME on the specs
1899 break;
1900 case B43_PHYTYPE_B:
1901 case B43_PHYTYPE_G:
1902 tmp = limit_value(tmp, 0x00, 0x3F);
1903 dbm = phy->tssi2dbm[tmp];
1904 break;
1905 default:
1906 B43_WARN_ON(1);
1907 }
1908
1909 return dbm;
1910 }
1911
1912 void b43_put_attenuation_into_ranges(struct b43_wldev *dev,
1913 int *_bbatt, int *_rfatt)
1914 {
1915 int rfatt = *_rfatt;
1916 int bbatt = *_bbatt;
1917 struct b43_txpower_lo_control *lo = dev->phy.lo_control;
1918
1919 /* Get baseband and radio attenuation values into their permitted ranges.
1920 * Radio attenuation affects power level 4 times as much as baseband. */
1921
1922 /* Range constants */
1923 const int rf_min = lo->rfatt_list.min_val;
1924 const int rf_max = lo->rfatt_list.max_val;
1925 const int bb_min = lo->bbatt_list.min_val;
1926 const int bb_max = lo->bbatt_list.max_val;
1927
1928 while (1) {
1929 if (rfatt > rf_max && bbatt > bb_max - 4)
1930 break; /* Can not get it into ranges */
1931 if (rfatt < rf_min && bbatt < bb_min + 4)
1932 break; /* Can not get it into ranges */
1933 if (bbatt > bb_max && rfatt > rf_max - 1)
1934 break; /* Can not get it into ranges */
1935 if (bbatt < bb_min && rfatt < rf_min + 1)
1936 break; /* Can not get it into ranges */
1937
1938 if (bbatt > bb_max) {
1939 bbatt -= 4;
1940 rfatt += 1;
1941 continue;
1942 }
1943 if (bbatt < bb_min) {
1944 bbatt += 4;
1945 rfatt -= 1;
1946 continue;
1947 }
1948 if (rfatt > rf_max) {
1949 rfatt -= 1;
1950 bbatt += 4;
1951 continue;
1952 }
1953 if (rfatt < rf_min) {
1954 rfatt += 1;
1955 bbatt -= 4;
1956 continue;
1957 }
1958 break;
1959 }
1960
1961 *_rfatt = limit_value(rfatt, rf_min, rf_max);
1962 *_bbatt = limit_value(bbatt, bb_min, bb_max);
1963 }
1964
1965 /* http://bcm-specs.sipsolutions.net/RecalculateTransmissionPower */
1966 void b43_phy_xmitpower(struct b43_wldev *dev)
1967 {
1968 struct ssb_bus *bus = dev->dev->bus;
1969 struct b43_phy *phy = &dev->phy;
1970
1971 if (phy->cur_idle_tssi == 0)
1972 return;
1973 if ((bus->boardinfo.vendor == SSB_BOARDVENDOR_BCM) &&
1974 (bus->boardinfo.type == SSB_BOARD_BU4306))
1975 return;
1976 #ifdef CONFIG_B43_DEBUG
1977 if (phy->manual_txpower_control)
1978 return;
1979 #endif
1980
1981 switch (phy->type) {
1982 case B43_PHYTYPE_A:{
1983
1984 //TODO: Nothing for A PHYs yet :-/
1985
1986 break;
1987 }
1988 case B43_PHYTYPE_B:
1989 case B43_PHYTYPE_G:{
1990 u16 tmp;
1991 s8 v0, v1, v2, v3;
1992 s8 average;
1993 int max_pwr;
1994 int desired_pwr, estimated_pwr, pwr_adjust;
1995 int rfatt_delta, bbatt_delta;
1996 int rfatt, bbatt;
1997 u8 tx_control;
1998 unsigned long phylock_flags;
1999
2000 tmp = b43_shm_read16(dev, B43_SHM_SHARED, 0x0058);
2001 v0 = (s8) (tmp & 0x00FF);
2002 v1 = (s8) ((tmp & 0xFF00) >> 8);
2003 tmp = b43_shm_read16(dev, B43_SHM_SHARED, 0x005A);
2004 v2 = (s8) (tmp & 0x00FF);
2005 v3 = (s8) ((tmp & 0xFF00) >> 8);
2006 tmp = 0;
2007
2008 if (v0 == 0x7F || v1 == 0x7F || v2 == 0x7F
2009 || v3 == 0x7F) {
2010 tmp =
2011 b43_shm_read16(dev, B43_SHM_SHARED, 0x0070);
2012 v0 = (s8) (tmp & 0x00FF);
2013 v1 = (s8) ((tmp & 0xFF00) >> 8);
2014 tmp =
2015 b43_shm_read16(dev, B43_SHM_SHARED, 0x0072);
2016 v2 = (s8) (tmp & 0x00FF);
2017 v3 = (s8) ((tmp & 0xFF00) >> 8);
2018 if (v0 == 0x7F || v1 == 0x7F || v2 == 0x7F
2019 || v3 == 0x7F)
2020 return;
2021 v0 = (v0 + 0x20) & 0x3F;
2022 v1 = (v1 + 0x20) & 0x3F;
2023 v2 = (v2 + 0x20) & 0x3F;
2024 v3 = (v3 + 0x20) & 0x3F;
2025 tmp = 1;
2026 }
2027 b43_shm_clear_tssi(dev);
2028
2029 average = (v0 + v1 + v2 + v3 + 2) / 4;
2030
2031 if (tmp
2032 && (b43_shm_read16(dev, B43_SHM_SHARED, 0x005E) &
2033 0x8))
2034 average -= 13;
2035
2036 estimated_pwr =
2037 b43_phy_estimate_power_out(dev, average);
2038
2039 max_pwr = dev->dev->bus->sprom.r1.maxpwr_bg;
2040 if ((dev->dev->bus->sprom.r1.
2041 boardflags_lo & B43_BFL_PACTRL)
2042 && (phy->type == B43_PHYTYPE_G))
2043 max_pwr -= 0x3;
2044 if (unlikely(max_pwr <= 0)) {
2045 b43warn(dev->wl,
2046 "Invalid max-TX-power value in SPROM.\n");
2047 max_pwr = 60; /* fake it */
2048 dev->dev->bus->sprom.r1.maxpwr_bg = max_pwr;
2049 }
2050
2051 /*TODO:
2052 max_pwr = min(REG - dev->dev->bus->sprom.antennagain_bgphy - 0x6, max_pwr)
2053 where REG is the max power as per the regulatory domain
2054 */
2055
2056 /* Get desired power (in Q5.2) */
2057 desired_pwr = INT_TO_Q52(phy->power_level);
2058 /* And limit it. max_pwr already is Q5.2 */
2059 desired_pwr = limit_value(desired_pwr, 0, max_pwr);
2060 if (b43_debug(dev, B43_DBG_XMITPOWER)) {
2061 b43dbg(dev->wl,
2062 "Current TX power output: " Q52_FMT
2063 " dBm, " "Desired TX power output: "
2064 Q52_FMT " dBm\n", Q52_ARG(estimated_pwr),
2065 Q52_ARG(desired_pwr));
2066 }
2067
2068 /* Calculate the adjustment delta. */
2069 pwr_adjust = desired_pwr - estimated_pwr;
2070
2071 /* RF attenuation delta. */
2072 rfatt_delta = ((pwr_adjust + 7) / 8);
2073 /* Lower attenuation => Bigger power output. Negate it. */
2074 rfatt_delta = -rfatt_delta;
2075
2076 /* Baseband attenuation delta. */
2077 bbatt_delta = pwr_adjust / 2;
2078 /* Lower attenuation => Bigger power output. Negate it. */
2079 bbatt_delta = -bbatt_delta;
2080 /* RF att affects power level 4 times as much as
2081 * Baseband attennuation. Subtract it. */
2082 bbatt_delta -= 4 * rfatt_delta;
2083
2084 /* So do we finally need to adjust something? */
2085 if ((rfatt_delta == 0) && (bbatt_delta == 0)) {
2086 b43_lo_g_ctl_mark_cur_used(dev);
2087 return;
2088 }
2089
2090 /* Calculate the new attenuation values. */
2091 bbatt = phy->bbatt.att;
2092 bbatt += bbatt_delta;
2093 rfatt = phy->rfatt.att;
2094 rfatt += rfatt_delta;
2095
2096 b43_put_attenuation_into_ranges(dev, &bbatt, &rfatt);
2097 tx_control = phy->tx_control;
2098 if ((phy->radio_ver == 0x2050) && (phy->radio_rev == 2)) {
2099 if (rfatt <= 1) {
2100 if (tx_control == 0) {
2101 tx_control =
2102 B43_TXCTL_PA2DB |
2103 B43_TXCTL_TXMIX;
2104 rfatt += 2;
2105 bbatt += 2;
2106 } else if (dev->dev->bus->sprom.r1.
2107 boardflags_lo &
2108 B43_BFL_PACTRL) {
2109 bbatt += 4 * (rfatt - 2);
2110 rfatt = 2;
2111 }
2112 } else if (rfatt > 4 && tx_control) {
2113 tx_control = 0;
2114 if (bbatt < 3) {
2115 rfatt -= 3;
2116 bbatt += 2;
2117 } else {
2118 rfatt -= 2;
2119 bbatt -= 2;
2120 }
2121 }
2122 }
2123 /* Save the control values */
2124 phy->tx_control = tx_control;
2125 b43_put_attenuation_into_ranges(dev, &bbatt, &rfatt);
2126 phy->rfatt.att = rfatt;
2127 phy->bbatt.att = bbatt;
2128
2129 /* Adjust the hardware */
2130 b43_phy_lock(dev, phylock_flags);
2131 b43_radio_lock(dev);
2132 b43_set_txpower_g(dev, &phy->bbatt, &phy->rfatt,
2133 phy->tx_control);
2134 b43_lo_g_ctl_mark_cur_used(dev);
2135 b43_radio_unlock(dev);
2136 b43_phy_unlock(dev, phylock_flags);
2137 break;
2138 }
2139 default:
2140 B43_WARN_ON(1);
2141 }
2142 }
2143
2144 static inline s32 b43_tssi2dbm_ad(s32 num, s32 den)
2145 {
2146 if (num < 0)
2147 return num / den;
2148 else
2149 return (num + den / 2) / den;
2150 }
2151
2152 static inline
2153 s8 b43_tssi2dbm_entry(s8 entry[], u8 index, s16 pab0, s16 pab1, s16 pab2)
2154 {
2155 s32 m1, m2, f = 256, q, delta;
2156 s8 i = 0;
2157
2158 m1 = b43_tssi2dbm_ad(16 * pab0 + index * pab1, 32);
2159 m2 = max(b43_tssi2dbm_ad(32768 + index * pab2, 256), 1);
2160 do {
2161 if (i > 15)
2162 return -EINVAL;
2163 q = b43_tssi2dbm_ad(f * 4096 -
2164 b43_tssi2dbm_ad(m2 * f, 16) * f, 2048);
2165 delta = abs(q - f);
2166 f = q;
2167 i++;
2168 } while (delta >= 2);
2169 entry[index] = limit_value(b43_tssi2dbm_ad(m1 * f, 8192), -127, 128);
2170 return 0;
2171 }
2172
2173 /* http://bcm-specs.sipsolutions.net/TSSI_to_DBM_Table */
2174 int b43_phy_init_tssi2dbm_table(struct b43_wldev *dev)
2175 {
2176 struct b43_phy *phy = &dev->phy;
2177 s16 pab0, pab1, pab2;
2178 u8 idx;
2179 s8 *dyn_tssi2dbm;
2180
2181 if (phy->type == B43_PHYTYPE_A) {
2182 pab0 = (s16) (dev->dev->bus->sprom.r1.pa1b0);
2183 pab1 = (s16) (dev->dev->bus->sprom.r1.pa1b1);
2184 pab2 = (s16) (dev->dev->bus->sprom.r1.pa1b2);
2185 } else {
2186 pab0 = (s16) (dev->dev->bus->sprom.r1.pa0b0);
2187 pab1 = (s16) (dev->dev->bus->sprom.r1.pa0b1);
2188 pab2 = (s16) (dev->dev->bus->sprom.r1.pa0b2);
2189 }
2190
2191 if ((dev->dev->bus->chip_id == 0x4301) && (phy->radio_ver != 0x2050)) {
2192 phy->tgt_idle_tssi = 0x34;
2193 phy->tssi2dbm = b43_tssi2dbm_b_table;
2194 return 0;
2195 }
2196
2197 if (pab0 != 0 && pab1 != 0 && pab2 != 0 &&
2198 pab0 != -1 && pab1 != -1 && pab2 != -1) {
2199 /* The pabX values are set in SPROM. Use them. */
2200 if (phy->type == B43_PHYTYPE_A) {
2201 if ((s8) dev->dev->bus->sprom.r1.itssi_a != 0 &&
2202 (s8) dev->dev->bus->sprom.r1.itssi_a != -1)
2203 phy->tgt_idle_tssi =
2204 (s8) (dev->dev->bus->sprom.r1.itssi_a);
2205 else
2206 phy->tgt_idle_tssi = 62;
2207 } else {
2208 if ((s8) dev->dev->bus->sprom.r1.itssi_bg != 0 &&
2209 (s8) dev->dev->bus->sprom.r1.itssi_bg != -1)
2210 phy->tgt_idle_tssi =
2211 (s8) (dev->dev->bus->sprom.r1.itssi_bg);
2212 else
2213 phy->tgt_idle_tssi = 62;
2214 }
2215 dyn_tssi2dbm = kmalloc(64, GFP_KERNEL);
2216 if (dyn_tssi2dbm == NULL) {
2217 b43err(dev->wl, "Could not allocate memory"
2218 "for tssi2dbm table\n");
2219 return -ENOMEM;
2220 }
2221 for (idx = 0; idx < 64; idx++)
2222 if (b43_tssi2dbm_entry
2223 (dyn_tssi2dbm, idx, pab0, pab1, pab2)) {
2224 phy->tssi2dbm = NULL;
2225 b43err(dev->wl, "Could not generate "
2226 "tssi2dBm table\n");
2227 kfree(dyn_tssi2dbm);
2228 return -ENODEV;
2229 }
2230 phy->tssi2dbm = dyn_tssi2dbm;
2231 phy->dyn_tssi_tbl = 1;
2232 } else {
2233 /* pabX values not set in SPROM. */
2234 switch (phy->type) {
2235 case B43_PHYTYPE_A:
2236 /* APHY needs a generated table. */
2237 phy->tssi2dbm = NULL;
2238 b43err(dev->wl, "Could not generate tssi2dBm "
2239 "table (wrong SPROM info)!\n");
2240 return -ENODEV;
2241 case B43_PHYTYPE_B:
2242 phy->tgt_idle_tssi = 0x34;
2243 phy->tssi2dbm = b43_tssi2dbm_b_table;
2244 break;
2245 case B43_PHYTYPE_G:
2246 phy->tgt_idle_tssi = 0x34;
2247 phy->tssi2dbm = b43_tssi2dbm_g_table;
2248 break;
2249 }
2250 }
2251
2252 return 0;
2253 }
2254
2255 int b43_phy_init(struct b43_wldev *dev)
2256 {
2257 struct b43_phy *phy = &dev->phy;
2258 int err = -ENODEV;
2259
2260 switch (phy->type) {
2261 case B43_PHYTYPE_A:
2262 if (phy->rev == 2 || phy->rev == 3) {
2263 b43_phy_inita(dev);
2264 err = 0;
2265 }
2266 break;
2267 case B43_PHYTYPE_B:
2268 switch (phy->rev) {
2269 case 2:
2270 b43_phy_initb2(dev);
2271 err = 0;
2272 break;
2273 case 4:
2274 b43_phy_initb4(dev);
2275 err = 0;
2276 break;
2277 case 5:
2278 b43_phy_initb5(dev);
2279 err = 0;
2280 break;
2281 case 6:
2282 b43_phy_initb6(dev);
2283 err = 0;
2284 break;
2285 }
2286 break;
2287 case B43_PHYTYPE_G:
2288 b43_phy_initg(dev);
2289 err = 0;
2290 break;
2291 }
2292 if (err)
2293 b43err(dev->wl, "Unknown PHYTYPE found\n");
2294
2295 return err;
2296 }
2297
2298 void b43_set_rx_antenna(struct b43_wldev *dev, int antenna)
2299 {
2300 struct b43_phy *phy = &dev->phy;
2301 u32 hf;
2302 u16 tmp;
2303 int autodiv = 0;
2304
2305 if (antenna == B43_ANTENNA_AUTO0 || antenna == B43_ANTENNA_AUTO1)
2306 autodiv = 1;
2307
2308 hf = b43_hf_read(dev);
2309 hf &= ~B43_HF_ANTDIVHELP;
2310 b43_hf_write(dev, hf);
2311
2312 switch (phy->type) {
2313 case B43_PHYTYPE_A:
2314 case B43_PHYTYPE_G:
2315 tmp = b43_phy_read(dev, B43_PHY_BBANDCFG);
2316 tmp &= ~B43_PHY_BBANDCFG_RXANT;
2317 tmp |= (autodiv ? B43_ANTENNA_AUTO0 : antenna)
2318 << B43_PHY_BBANDCFG_RXANT_SHIFT;
2319 b43_phy_write(dev, B43_PHY_BBANDCFG, tmp);
2320
2321 if (autodiv) {
2322 tmp = b43_phy_read(dev, B43_PHY_ANTDWELL);
2323 if (antenna == B43_ANTENNA_AUTO0)
2324 tmp &= ~B43_PHY_ANTDWELL_AUTODIV1;
2325 else
2326 tmp |= B43_PHY_ANTDWELL_AUTODIV1;
2327 b43_phy_write(dev, B43_PHY_ANTDWELL, tmp);
2328 }
2329 if (phy->type == B43_PHYTYPE_G) {
2330 tmp = b43_phy_read(dev, B43_PHY_ANTWRSETT);
2331 if (autodiv)
2332 tmp |= B43_PHY_ANTWRSETT_ARXDIV;
2333 else
2334 tmp &= ~B43_PHY_ANTWRSETT_ARXDIV;
2335 b43_phy_write(dev, B43_PHY_ANTWRSETT, tmp);
2336 if (phy->rev >= 2) {
2337 tmp = b43_phy_read(dev, B43_PHY_OFDM61);
2338 tmp |= B43_PHY_OFDM61_10;
2339 b43_phy_write(dev, B43_PHY_OFDM61, tmp);
2340
2341 tmp =
2342 b43_phy_read(dev, B43_PHY_DIVSRCHGAINBACK);
2343 tmp = (tmp & 0xFF00) | 0x15;
2344 b43_phy_write(dev, B43_PHY_DIVSRCHGAINBACK,
2345 tmp);
2346
2347 if (phy->rev == 2) {
2348 b43_phy_write(dev, B43_PHY_ADIVRELATED,
2349 8);
2350 } else {
2351 tmp =
2352 b43_phy_read(dev,
2353 B43_PHY_ADIVRELATED);
2354 tmp = (tmp & 0xFF00) | 8;
2355 b43_phy_write(dev, B43_PHY_ADIVRELATED,
2356 tmp);
2357 }
2358 }
2359 if (phy->rev >= 6)
2360 b43_phy_write(dev, B43_PHY_OFDM9B, 0xDC);
2361 } else {
2362 if (phy->rev < 3) {
2363 tmp = b43_phy_read(dev, B43_PHY_ANTDWELL);
2364 tmp = (tmp & 0xFF00) | 0x24;
2365 b43_phy_write(dev, B43_PHY_ANTDWELL, tmp);
2366 } else {
2367 tmp = b43_phy_read(dev, B43_PHY_OFDM61);
2368 tmp |= 0x10;
2369 b43_phy_write(dev, B43_PHY_OFDM61, tmp);
2370 if (phy->analog == 3) {
2371 b43_phy_write(dev, B43_PHY_CLIPPWRDOWNT,
2372 0x1D);
2373 b43_phy_write(dev, B43_PHY_ADIVRELATED,
2374 8);
2375 } else {
2376 b43_phy_write(dev, B43_PHY_CLIPPWRDOWNT,
2377 0x3A);
2378 tmp =
2379 b43_phy_read(dev,
2380 B43_PHY_ADIVRELATED);
2381 tmp = (tmp & 0xFF00) | 8;
2382 b43_phy_write(dev, B43_PHY_ADIVRELATED,
2383 tmp);
2384 }
2385 }
2386 }
2387 break;
2388 case B43_PHYTYPE_B:
2389 tmp = b43_phy_read(dev, B43_PHY_CCKBBANDCFG);
2390 tmp &= ~B43_PHY_BBANDCFG_RXANT;
2391 tmp |= (autodiv ? B43_ANTENNA_AUTO0 : antenna)
2392 << B43_PHY_BBANDCFG_RXANT_SHIFT;
2393 b43_phy_write(dev, B43_PHY_CCKBBANDCFG, tmp);
2394 break;
2395 default:
2396 B43_WARN_ON(1);
2397 }
2398
2399 hf |= B43_HF_ANTDIVHELP;
2400 b43_hf_write(dev, hf);
2401 }
2402
2403 /* Get the freq, as it has to be written to the device. */
2404 static inline u16 channel2freq_bg(u8 channel)
2405 {
2406 B43_WARN_ON(!(channel >= 1 && channel <= 14));
2407
2408 return b43_radio_channel_codes_bg[channel - 1];
2409 }
2410
2411 /* Get the freq, as it has to be written to the device. */
2412 static inline u16 channel2freq_a(u8 channel)
2413 {
2414 B43_WARN_ON(channel > 200);
2415
2416 return (5000 + 5 * channel);
2417 }
2418
2419 void b43_radio_lock(struct b43_wldev *dev)
2420 {
2421 u32 macctl;
2422
2423 macctl = b43_read32(dev, B43_MMIO_MACCTL);
2424 macctl |= B43_MACCTL_RADIOLOCK;
2425 b43_write32(dev, B43_MMIO_MACCTL, macctl);
2426 /* Commit the write and wait for the device
2427 * to exit any radio register access. */
2428 b43_read32(dev, B43_MMIO_MACCTL);
2429 udelay(10);
2430 }
2431
2432 void b43_radio_unlock(struct b43_wldev *dev)
2433 {
2434 u32 macctl;
2435
2436 /* Commit any write */
2437 b43_read16(dev, B43_MMIO_PHY_VER);
2438 /* unlock */
2439 macctl = b43_read32(dev, B43_MMIO_MACCTL);
2440 macctl &= ~B43_MACCTL_RADIOLOCK;
2441 b43_write32(dev, B43_MMIO_MACCTL, macctl);
2442 }
2443
2444 u16 b43_radio_read16(struct b43_wldev *dev, u16 offset)
2445 {
2446 struct b43_phy *phy = &dev->phy;
2447
2448 switch (phy->type) {
2449 case B43_PHYTYPE_A:
2450 offset |= 0x0040;
2451 break;
2452 case B43_PHYTYPE_B:
2453 if (phy->radio_ver == 0x2053) {
2454 if (offset < 0x70)
2455 offset += 0x80;
2456 else if (offset < 0x80)
2457 offset += 0x70;
2458 } else if (phy->radio_ver == 0x2050) {
2459 offset |= 0x80;
2460 } else
2461 B43_WARN_ON(1);
2462 break;
2463 case B43_PHYTYPE_G:
2464 offset |= 0x80;
2465 break;
2466 }
2467
2468 b43_write16(dev, B43_MMIO_RADIO_CONTROL, offset);
2469 return b43_read16(dev, B43_MMIO_RADIO_DATA_LOW);
2470 }
2471
2472 void b43_radio_write16(struct b43_wldev *dev, u16 offset, u16 val)
2473 {
2474 b43_write16(dev, B43_MMIO_RADIO_CONTROL, offset);
2475 mmiowb();
2476 b43_write16(dev, B43_MMIO_RADIO_DATA_LOW, val);
2477 }
2478
2479 static void b43_set_all_gains(struct b43_wldev *dev,
2480 s16 first, s16 second, s16 third)
2481 {
2482 struct b43_phy *phy = &dev->phy;
2483 u16 i;
2484 u16 start = 0x08, end = 0x18;
2485 u16 tmp;
2486 u16 table;
2487
2488 if (phy->rev <= 1) {
2489 start = 0x10;
2490 end = 0x20;
2491 }
2492
2493 table = B43_OFDMTAB_GAINX;
2494 if (phy->rev <= 1)
2495 table = B43_OFDMTAB_GAINX_R1;
2496 for (i = 0; i < 4; i++)
2497 b43_ofdmtab_write16(dev, table, i, first);
2498
2499 for (i = start; i < end; i++)
2500 b43_ofdmtab_write16(dev, table, i, second);
2501
2502 if (third != -1) {
2503 tmp = ((u16) third << 14) | ((u16) third << 6);
2504 b43_phy_write(dev, 0x04A0,
2505 (b43_phy_read(dev, 0x04A0) & 0xBFBF) | tmp);
2506 b43_phy_write(dev, 0x04A1,
2507 (b43_phy_read(dev, 0x04A1) & 0xBFBF) | tmp);
2508 b43_phy_write(dev, 0x04A2,
2509 (b43_phy_read(dev, 0x04A2) & 0xBFBF) | tmp);
2510 }
2511 b43_dummy_transmission(dev);
2512 }
2513
2514 static void b43_set_original_gains(struct b43_wldev *dev)
2515 {
2516 struct b43_phy *phy = &dev->phy;
2517 u16 i, tmp;
2518 u16 table;
2519 u16 start = 0x0008, end = 0x0018;
2520
2521 if (phy->rev <= 1) {
2522 start = 0x0010;
2523 end = 0x0020;
2524 }
2525
2526 table = B43_OFDMTAB_GAINX;
2527 if (phy->rev <= 1)
2528 table = B43_OFDMTAB_GAINX_R1;
2529 for (i = 0; i < 4; i++) {
2530 tmp = (i & 0xFFFC);
2531 tmp |= (i & 0x0001) << 1;
2532 tmp |= (i & 0x0002) >> 1;
2533
2534 b43_ofdmtab_write16(dev, table, i, tmp);
2535 }
2536
2537 for (i = start; i < end; i++)
2538 b43_ofdmtab_write16(dev, table, i, i - start);
2539
2540 b43_phy_write(dev, 0x04A0,
2541 (b43_phy_read(dev, 0x04A0) & 0xBFBF) | 0x4040);
2542 b43_phy_write(dev, 0x04A1,
2543 (b43_phy_read(dev, 0x04A1) & 0xBFBF) | 0x4040);
2544 b43_phy_write(dev, 0x04A2,
2545 (b43_phy_read(dev, 0x04A2) & 0xBFBF) | 0x4000);
2546 b43_dummy_transmission(dev);
2547 }
2548
2549 /* Synthetic PU workaround */
2550 static void b43_synth_pu_workaround(struct b43_wldev *dev, u8 channel)
2551 {
2552 struct b43_phy *phy = &dev->phy;
2553
2554 might_sleep();
2555
2556 if (phy->radio_ver != 0x2050 || phy->radio_rev >= 6) {
2557 /* We do not need the workaround. */
2558 return;
2559 }
2560
2561 if (channel <= 10) {
2562 b43_write16(dev, B43_MMIO_CHANNEL,
2563 channel2freq_bg(channel + 4));
2564 } else {
2565 b43_write16(dev, B43_MMIO_CHANNEL, channel2freq_bg(1));
2566 }
2567 msleep(1);
2568 b43_write16(dev, B43_MMIO_CHANNEL, channel2freq_bg(channel));
2569 }
2570
2571 u8 b43_radio_aci_detect(struct b43_wldev *dev, u8 channel)
2572 {
2573 struct b43_phy *phy = &dev->phy;
2574 u8 ret = 0;
2575 u16 saved, rssi, temp;
2576 int i, j = 0;
2577
2578 saved = b43_phy_read(dev, 0x0403);
2579 b43_radio_selectchannel(dev, channel, 0);
2580 b43_phy_write(dev, 0x0403, (saved & 0xFFF8) | 5);
2581 if (phy->aci_hw_rssi)
2582 rssi = b43_phy_read(dev, 0x048A) & 0x3F;
2583 else
2584 rssi = saved & 0x3F;
2585 /* clamp temp to signed 5bit */
2586 if (rssi > 32)
2587 rssi -= 64;
2588 for (i = 0; i < 100; i++) {
2589 temp = (b43_phy_read(dev, 0x047F) >> 8) & 0x3F;
2590 if (temp > 32)
2591 temp -= 64;
2592 if (temp < rssi)
2593 j++;
2594 if (j >= 20)
2595 ret = 1;
2596 }
2597 b43_phy_write(dev, 0x0403, saved);
2598
2599 return ret;
2600 }
2601
2602 u8 b43_radio_aci_scan(struct b43_wldev * dev)
2603 {
2604 struct b43_phy *phy = &dev->phy;
2605 u8 ret[13];
2606 unsigned int channel = phy->channel;
2607 unsigned int i, j, start, end;
2608 unsigned long phylock_flags;
2609
2610 if (!((phy->type == B43_PHYTYPE_G) && (phy->rev > 0)))
2611 return 0;
2612
2613 b43_phy_lock(dev, phylock_flags);
2614 b43_radio_lock(dev);
2615 b43_phy_write(dev, 0x0802, b43_phy_read(dev, 0x0802) & 0xFFFC);
2616 b43_phy_write(dev, B43_PHY_G_CRS,
2617 b43_phy_read(dev, B43_PHY_G_CRS) & 0x7FFF);
2618 b43_set_all_gains(dev, 3, 8, 1);
2619
2620 start = (channel - 5 > 0) ? channel - 5 : 1;
2621 end = (channel + 5 < 14) ? channel + 5 : 13;
2622
2623 for (i = start; i <= end; i++) {
2624 if (abs(channel - i) > 2)
2625 ret[i - 1] = b43_radio_aci_detect(dev, i);
2626 }
2627 b43_radio_selectchannel(dev, channel, 0);
2628 b43_phy_write(dev, 0x0802,
2629 (b43_phy_read(dev, 0x0802) & 0xFFFC) | 0x0003);
2630 b43_phy_write(dev, 0x0403, b43_phy_read(dev, 0x0403) & 0xFFF8);
2631 b43_phy_write(dev, B43_PHY_G_CRS,
2632 b43_phy_read(dev, B43_PHY_G_CRS) | 0x8000);
2633 b43_set_original_gains(dev);
2634 for (i = 0; i < 13; i++) {
2635 if (!ret[i])
2636 continue;
2637 end = (i + 5 < 13) ? i + 5 : 13;
2638 for (j = i; j < end; j++)
2639 ret[j] = 1;
2640 }
2641 b43_radio_unlock(dev);
2642 b43_phy_unlock(dev, phylock_flags);
2643
2644 return ret[channel - 1];
2645 }
2646
2647 /* http://bcm-specs.sipsolutions.net/NRSSILookupTable */
2648 void b43_nrssi_hw_write(struct b43_wldev *dev, u16 offset, s16 val)
2649 {
2650 b43_phy_write(dev, B43_PHY_NRSSILT_CTRL, offset);
2651 mmiowb();
2652 b43_phy_write(dev, B43_PHY_NRSSILT_DATA, (u16) val);
2653 }
2654
2655 /* http://bcm-specs.sipsolutions.net/NRSSILookupTable */
2656 s16 b43_nrssi_hw_read(struct b43_wldev *dev, u16 offset)
2657 {
2658 u16 val;
2659
2660 b43_phy_write(dev, B43_PHY_NRSSILT_CTRL, offset);
2661 val = b43_phy_read(dev, B43_PHY_NRSSILT_DATA);
2662
2663 return (s16) val;
2664 }
2665
2666 /* http://bcm-specs.sipsolutions.net/NRSSILookupTable */
2667 void b43_nrssi_hw_update(struct b43_wldev *dev, u16 val)
2668 {
2669 u16 i;
2670 s16 tmp;
2671
2672 for (i = 0; i < 64; i++) {
2673 tmp = b43_nrssi_hw_read(dev, i);
2674 tmp -= val;
2675 tmp = limit_value(tmp, -32, 31);
2676 b43_nrssi_hw_write(dev, i, tmp);
2677 }
2678 }
2679
2680 /* http://bcm-specs.sipsolutions.net/NRSSILookupTable */
2681 void b43_nrssi_mem_update(struct b43_wldev *dev)
2682 {
2683 struct b43_phy *phy = &dev->phy;
2684 s16 i, delta;
2685 s32 tmp;
2686
2687 delta = 0x1F - phy->nrssi[0];
2688 for (i = 0; i < 64; i++) {
2689 tmp = (i - delta) * phy->nrssislope;
2690 tmp /= 0x10000;
2691 tmp += 0x3A;
2692 tmp = limit_value(tmp, 0, 0x3F);
2693 phy->nrssi_lt[i] = tmp;
2694 }
2695 }
2696
2697 static void b43_calc_nrssi_offset(struct b43_wldev *dev)
2698 {
2699 struct b43_phy *phy = &dev->phy;
2700 u16 backup[20] = { 0 };
2701 s16 v47F;
2702 u16 i;
2703 u16 saved = 0xFFFF;
2704
2705 backup[0] = b43_phy_read(dev, 0x0001);
2706 backup[1] = b43_phy_read(dev, 0x0811);
2707 backup[2] = b43_phy_read(dev, 0x0812);
2708 if (phy->rev != 1) { /* Not in specs, but needed to prevent PPC machine check */
2709 backup[3] = b43_phy_read(dev, 0x0814);
2710 backup[4] = b43_phy_read(dev, 0x0815);
2711 }
2712 backup[5] = b43_phy_read(dev, 0x005A);
2713 backup[6] = b43_phy_read(dev, 0x0059);
2714 backup[7] = b43_phy_read(dev, 0x0058);
2715 backup[8] = b43_phy_read(dev, 0x000A);
2716 backup[9] = b43_phy_read(dev, 0x0003);
2717 backup[10] = b43_radio_read16(dev, 0x007A);
2718 backup[11] = b43_radio_read16(dev, 0x0043);
2719
2720 b43_phy_write(dev, 0x0429, b43_phy_read(dev, 0x0429) & 0x7FFF);
2721 b43_phy_write(dev, 0x0001,
2722 (b43_phy_read(dev, 0x0001) & 0x3FFF) | 0x4000);
2723 b43_phy_write(dev, 0x0811, b43_phy_read(dev, 0x0811) | 0x000C);
2724 b43_phy_write(dev, 0x0812,
2725 (b43_phy_read(dev, 0x0812) & 0xFFF3) | 0x0004);
2726 b43_phy_write(dev, 0x0802, b43_phy_read(dev, 0x0802) & ~(0x1 | 0x2));
2727 if (phy->rev >= 6) {
2728 backup[12] = b43_phy_read(dev, 0x002E);
2729 backup[13] = b43_phy_read(dev, 0x002F);
2730 backup[14] = b43_phy_read(dev, 0x080F);
2731 backup[15] = b43_phy_read(dev, 0x0810);
2732 backup[16] = b43_phy_read(dev, 0x0801);
2733 backup[17] = b43_phy_read(dev, 0x0060);
2734 backup[18] = b43_phy_read(dev, 0x0014);
2735 backup[19] = b43_phy_read(dev, 0x0478);
2736
2737 b43_phy_write(dev, 0x002E, 0);
2738 b43_phy_write(dev, 0x002F, 0);
2739 b43_phy_write(dev, 0x080F, 0);
2740 b43_phy_write(dev, 0x0810, 0);
2741 b43_phy_write(dev, 0x0478, b43_phy_read(dev, 0x0478) | 0x0100);
2742 b43_phy_write(dev, 0x0801, b43_phy_read(dev, 0x0801) | 0x0040);
2743 b43_phy_write(dev, 0x0060, b43_phy_read(dev, 0x0060) | 0x0040);
2744 b43_phy_write(dev, 0x0014, b43_phy_read(dev, 0x0014) | 0x0200);
2745 }
2746 b43_radio_write16(dev, 0x007A, b43_radio_read16(dev, 0x007A) | 0x0070);
2747 b43_radio_write16(dev, 0x007A, b43_radio_read16(dev, 0x007A) | 0x0080);
2748 udelay(30);
2749
2750 v47F = (s16) ((b43_phy_read(dev, 0x047F) >> 8) & 0x003F);
2751 if (v47F >= 0x20)
2752 v47F -= 0x40;
2753 if (v47F == 31) {
2754 for (i = 7; i >= 4; i--) {
2755 b43_radio_write16(dev, 0x007B, i);
2756 udelay(20);
2757 v47F =
2758 (s16) ((b43_phy_read(dev, 0x047F) >> 8) & 0x003F);
2759 if (v47F >= 0x20)
2760 v47F -= 0x40;
2761 if (v47F < 31 && saved == 0xFFFF)
2762 saved = i;
2763 }
2764 if (saved == 0xFFFF)
2765 saved = 4;
2766 } else {
2767 b43_radio_write16(dev, 0x007A,
2768 b43_radio_read16(dev, 0x007A) & 0x007F);
2769 if (phy->rev != 1) { /* Not in specs, but needed to prevent PPC machine check */
2770 b43_phy_write(dev, 0x0814,
2771 b43_phy_read(dev, 0x0814) | 0x0001);
2772 b43_phy_write(dev, 0x0815,
2773 b43_phy_read(dev, 0x0815) & 0xFFFE);
2774 }
2775 b43_phy_write(dev, 0x0811, b43_phy_read(dev, 0x0811) | 0x000C);
2776 b43_phy_write(dev, 0x0812, b43_phy_read(dev, 0x0812) | 0x000C);
2777 b43_phy_write(dev, 0x0811, b43_phy_read(dev, 0x0811) | 0x0030);
2778 b43_phy_write(dev, 0x0812, b43_phy_read(dev, 0x0812) | 0x0030);
2779 b43_phy_write(dev, 0x005A, 0x0480);
2780 b43_phy_write(dev, 0x0059, 0x0810);
2781 b43_phy_write(dev, 0x0058, 0x000D);
2782 if (phy->rev == 0) {
2783 b43_phy_write(dev, 0x0003, 0x0122);
2784 } else {
2785 b43_phy_write(dev, 0x000A, b43_phy_read(dev, 0x000A)
2786 | 0x2000);
2787 }
2788 if (phy->rev != 1) { /* Not in specs, but needed to prevent PPC machine check */
2789 b43_phy_write(dev, 0x0814,
2790 b43_phy_read(dev, 0x0814) | 0x0004);
2791 b43_phy_write(dev, 0x0815,
2792 b43_phy_read(dev, 0x0815) & 0xFFFB);
2793 }
2794 b43_phy_write(dev, 0x0003, (b43_phy_read(dev, 0x0003) & 0xFF9F)
2795 | 0x0040);
2796 b43_radio_write16(dev, 0x007A,
2797 b43_radio_read16(dev, 0x007A) | 0x000F);
2798 b43_set_all_gains(dev, 3, 0, 1);
2799 b43_radio_write16(dev, 0x0043, (b43_radio_read16(dev, 0x0043)
2800 & 0x00F0) | 0x000F);
2801 udelay(30);
2802 v47F = (s16) ((b43_phy_read(dev, 0x047F) >> 8) & 0x003F);
2803 if (v47F >= 0x20)
2804 v47F -= 0x40;
2805 if (v47F == -32) {
2806 for (i = 0; i < 4; i++) {
2807 b43_radio_write16(dev, 0x007B, i);
2808 udelay(20);
2809 v47F =
2810 (s16) ((b43_phy_read(dev, 0x047F) >> 8) &
2811 0x003F);
2812 if (v47F >= 0x20)
2813 v47F -= 0x40;
2814 if (v47F > -31 && saved == 0xFFFF)
2815 saved = i;
2816 }
2817 if (saved == 0xFFFF)
2818 saved = 3;
2819 } else
2820 saved = 0;
2821 }
2822 b43_radio_write16(dev, 0x007B, saved);
2823
2824 if (phy->rev >= 6) {
2825 b43_phy_write(dev, 0x002E, backup[12]);
2826 b43_phy_write(dev, 0x002F, backup[13]);
2827 b43_phy_write(dev, 0x080F, backup[14]);
2828 b43_phy_write(dev, 0x0810, backup[15]);
2829 }
2830 if (phy->rev != 1) { /* Not in specs, but needed to prevent PPC machine check */
2831 b43_phy_write(dev, 0x0814, backup[3]);
2832 b43_phy_write(dev, 0x0815, backup[4]);
2833 }
2834 b43_phy_write(dev, 0x005A, backup[5]);
2835 b43_phy_write(dev, 0x0059, backup[6]);
2836 b43_phy_write(dev, 0x0058, backup[7]);
2837 b43_phy_write(dev, 0x000A, backup[8]);
2838 b43_phy_write(dev, 0x0003, backup[9]);
2839 b43_radio_write16(dev, 0x0043, backup[11]);
2840 b43_radio_write16(dev, 0x007A, backup[10]);
2841 b43_phy_write(dev, 0x0802, b43_phy_read(dev, 0x0802) | 0x1 | 0x2);
2842 b43_phy_write(dev, 0x0429, b43_phy_read(dev, 0x0429) | 0x8000);
2843 b43_set_original_gains(dev);
2844 if (phy->rev >= 6) {
2845 b43_phy_write(dev, 0x0801, backup[16]);
2846 b43_phy_write(dev, 0x0060, backup[17]);
2847 b43_phy_write(dev, 0x0014, backup[18]);
2848 b43_phy_write(dev, 0x0478, backup[19]);
2849 }
2850 b43_phy_write(dev, 0x0001, backup[0]);
2851 b43_phy_write(dev, 0x0812, backup[2]);
2852 b43_phy_write(dev, 0x0811, backup[1]);
2853 }
2854
2855 void b43_calc_nrssi_slope(struct b43_wldev *dev)
2856 {
2857 struct b43_phy *phy = &dev->phy;
2858 u16 backup[18] = { 0 };
2859 u16 tmp;
2860 s16 nrssi0, nrssi1;
2861
2862 switch (phy->type) {
2863 case B43_PHYTYPE_B:
2864 backup[0] = b43_radio_read16(dev, 0x007A);
2865 backup[1] = b43_radio_read16(dev, 0x0052);
2866 backup[2] = b43_radio_read16(dev, 0x0043);
2867 backup[3] = b43_phy_read(dev, 0x0030);
2868 backup[4] = b43_phy_read(dev, 0x0026);
2869 backup[5] = b43_phy_read(dev, 0x0015);
2870 backup[6] = b43_phy_read(dev, 0x002A);
2871 backup[7] = b43_phy_read(dev, 0x0020);
2872 backup[8] = b43_phy_read(dev, 0x005A);
2873 backup[9] = b43_phy_read(dev, 0x0059);
2874 backup[10] = b43_phy_read(dev, 0x0058);
2875 backup[11] = b43_read16(dev, 0x03E2);
2876 backup[12] = b43_read16(dev, 0x03E6);
2877 backup[13] = b43_read16(dev, B43_MMIO_CHANNEL_EXT);
2878
2879 tmp = b43_radio_read16(dev, 0x007A);
2880 tmp &= (phy->rev >= 5) ? 0x007F : 0x000F;
2881 b43_radio_write16(dev, 0x007A, tmp);
2882 b43_phy_write(dev, 0x0030, 0x00FF);
2883 b43_write16(dev, 0x03EC, 0x7F7F);
2884 b43_phy_write(dev, 0x0026, 0x0000);
2885 b43_phy_write(dev, 0x0015, b43_phy_read(dev, 0x0015) | 0x0020);
2886 b43_phy_write(dev, 0x002A, 0x08A3);
2887 b43_radio_write16(dev, 0x007A,
2888 b43_radio_read16(dev, 0x007A) | 0x0080);
2889
2890 nrssi0 = (s16) b43_phy_read(dev, 0x0027);
2891 b43_radio_write16(dev, 0x007A,
2892 b43_radio_read16(dev, 0x007A) & 0x007F);
2893 if (phy->rev >= 2) {
2894 b43_write16(dev, 0x03E6, 0x0040);
2895 } else if (phy->rev == 0) {
2896 b43_write16(dev, 0x03E6, 0x0122);
2897 } else {
2898 b43_write16(dev, B43_MMIO_CHANNEL_EXT,
2899 b43_read16(dev,
2900 B43_MMIO_CHANNEL_EXT) & 0x2000);
2901 }
2902 b43_phy_write(dev, 0x0020, 0x3F3F);
2903 b43_phy_write(dev, 0x0015, 0xF330);
2904 b43_radio_write16(dev, 0x005A, 0x0060);
2905 b43_radio_write16(dev, 0x0043,
2906 b43_radio_read16(dev, 0x0043) & 0x00F0);
2907 b43_phy_write(dev, 0x005A, 0x0480);
2908 b43_phy_write(dev, 0x0059, 0x0810);
2909 b43_phy_write(dev, 0x0058, 0x000D);
2910 udelay(20);
2911
2912 nrssi1 = (s16) b43_phy_read(dev, 0x0027);
2913 b43_phy_write(dev, 0x0030, backup[3]);
2914 b43_radio_write16(dev, 0x007A, backup[0]);
2915 b43_write16(dev, 0x03E2, backup[11]);
2916 b43_phy_write(dev, 0x0026, backup[4]);
2917 b43_phy_write(dev, 0x0015, backup[5]);
2918 b43_phy_write(dev, 0x002A, backup[6]);
2919 b43_synth_pu_workaround(dev, phy->channel);
2920 if (phy->rev != 0)
2921 b43_write16(dev, 0x03F4, backup[13]);
2922
2923 b43_phy_write(dev, 0x0020, backup[7]);
2924 b43_phy_write(dev, 0x005A, backup[8]);
2925 b43_phy_write(dev, 0x0059, backup[9]);
2926 b43_phy_write(dev, 0x0058, backup[10]);
2927 b43_radio_write16(dev, 0x0052, backup[1]);
2928 b43_radio_write16(dev, 0x0043, backup[2]);
2929
2930 if (nrssi0 == nrssi1)
2931 phy->nrssislope = 0x00010000;
2932 else
2933 phy->nrssislope = 0x00400000 / (nrssi0 - nrssi1);
2934
2935 if (nrssi0 <= -4) {
2936 phy->nrssi[0] = nrssi0;
2937 phy->nrssi[1] = nrssi1;
2938 }
2939 break;
2940 case B43_PHYTYPE_G:
2941 if (phy->radio_rev >= 9)
2942 return;
2943 if (phy->radio_rev == 8)
2944 b43_calc_nrssi_offset(dev);
2945
2946 b43_phy_write(dev, B43_PHY_G_CRS,
2947 b43_phy_read(dev, B43_PHY_G_CRS) & 0x7FFF);
2948 b43_phy_write(dev, 0x0802, b43_phy_read(dev, 0x0802) & 0xFFFC);
2949 backup[7] = b43_read16(dev, 0x03E2);
2950 b43_write16(dev, 0x03E2, b43_read16(dev, 0x03E2) | 0x8000);
2951 backup[0] = b43_radio_read16(dev, 0x007A);
2952 backup[1] = b43_radio_read16(dev, 0x0052);
2953 backup[2] = b43_radio_read16(dev, 0x0043);
2954 backup[3] = b43_phy_read(dev, 0x0015);
2955 backup[4] = b43_phy_read(dev, 0x005A);
2956 backup[5] = b43_phy_read(dev, 0x0059);
2957 backup[6] = b43_phy_read(dev, 0x0058);
2958 backup[8] = b43_read16(dev, 0x03E6);
2959 backup[9] = b43_read16(dev, B43_MMIO_CHANNEL_EXT);
2960 if (phy->rev >= 3) {
2961 backup[10] = b43_phy_read(dev, 0x002E);
2962 backup[11] = b43_phy_read(dev, 0x002F);
2963 backup[12] = b43_phy_read(dev, 0x080F);
2964 backup[13] = b43_phy_read(dev, B43_PHY_G_LO_CONTROL);
2965 backup[14] = b43_phy_read(dev, 0x0801);
2966 backup[15] = b43_phy_read(dev, 0x0060);
2967 backup[16] = b43_phy_read(dev, 0x0014);
2968 backup[17] = b43_phy_read(dev, 0x0478);
2969 b43_phy_write(dev, 0x002E, 0);
2970 b43_phy_write(dev, B43_PHY_G_LO_CONTROL, 0);
2971 switch (phy->rev) {
2972 case 4:
2973 case 6:
2974 case 7:
2975 b43_phy_write(dev, 0x0478,
2976 b43_phy_read(dev, 0x0478)
2977 | 0x0100);
2978 b43_phy_write(dev, 0x0801,
2979 b43_phy_read(dev, 0x0801)
2980 | 0x0040);
2981 break;
2982 case 3:
2983 case 5:
2984 b43_phy_write(dev, 0x0801,
2985 b43_phy_read(dev, 0x0801)
2986 & 0xFFBF);
2987 break;
2988 }
2989 b43_phy_write(dev, 0x0060, b43_phy_read(dev, 0x0060)
2990 | 0x0040);
2991 b43_phy_write(dev, 0x0014, b43_phy_read(dev, 0x0014)
2992 | 0x0200);
2993 }
2994 b43_radio_write16(dev, 0x007A,
2995 b43_radio_read16(dev, 0x007A) | 0x0070);
2996 b43_set_all_gains(dev, 0, 8, 0);
2997 b43_radio_write16(dev, 0x007A,
2998 b43_radio_read16(dev, 0x007A) & 0x00F7);
2999 if (phy->rev >= 2) {
3000 b43_phy_write(dev, 0x0811,
3001 (b43_phy_read(dev, 0x0811) & 0xFFCF) |
3002 0x0030);
3003 b43_phy_write(dev, 0x0812,
3004 (b43_phy_read(dev, 0x0812) & 0xFFCF) |
3005 0x0010);
3006 }
3007 b43_radio_write16(dev, 0x007A,
3008 b43_radio_read16(dev, 0x007A) | 0x0080);
3009 udelay(20);
3010
3011 nrssi0 = (s16) ((b43_phy_read(dev, 0x047F) >> 8) & 0x003F);
3012 if (nrssi0 >= 0x0020)
3013 nrssi0 -= 0x0040;
3014
3015 b43_radio_write16(dev, 0x007A,
3016 b43_radio_read16(dev, 0x007A) & 0x007F);
3017 if (phy->rev >= 2) {
3018 b43_phy_write(dev, 0x0003, (b43_phy_read(dev, 0x0003)
3019 & 0xFF9F) | 0x0040);
3020 }
3021
3022 b43_write16(dev, B43_MMIO_CHANNEL_EXT,
3023 b43_read16(dev, B43_MMIO_CHANNEL_EXT)
3024 | 0x2000);
3025 b43_radio_write16(dev, 0x007A,
3026 b43_radio_read16(dev, 0x007A) | 0x000F);
3027 b43_phy_write(dev, 0x0015, 0xF330);
3028 if (phy->rev >= 2) {
3029 b43_phy_write(dev, 0x0812,
3030 (b43_phy_read(dev, 0x0812) & 0xFFCF) |
3031 0x0020);
3032 b43_phy_write(dev, 0x0811,
3033 (b43_phy_read(dev, 0x0811) & 0xFFCF) |
3034 0x0020);
3035 }
3036
3037 b43_set_all_gains(dev, 3, 0, 1);
3038 if (phy->radio_rev == 8) {
3039 b43_radio_write16(dev, 0x0043, 0x001F);
3040 } else {
3041 tmp = b43_radio_read16(dev, 0x0052) & 0xFF0F;
3042 b43_radio_write16(dev, 0x0052, tmp | 0x0060);
3043 tmp = b43_radio_read16(dev, 0x0043) & 0xFFF0;
3044 b43_radio_write16(dev, 0x0043, tmp | 0x0009);
3045 }
3046 b43_phy_write(dev, 0x005A, 0x0480);
3047 b43_phy_write(dev, 0x0059, 0x0810);
3048 b43_phy_write(dev, 0x0058, 0x000D);
3049 udelay(20);
3050 nrssi1 = (s16) ((b43_phy_read(dev, 0x047F) >> 8) & 0x003F);
3051 if (nrssi1 >= 0x0020)
3052 nrssi1 -= 0x0040;
3053 if (nrssi0 == nrssi1)
3054 phy->nrssislope = 0x00010000;
3055 else
3056 phy->nrssislope = 0x00400000 / (nrssi0 - nrssi1);
3057 if (nrssi0 >= -4) {
3058 phy->nrssi[0] = nrssi1;
3059 phy->nrssi[1] = nrssi0;
3060 }
3061 if (phy->rev >= 3) {
3062 b43_phy_write(dev, 0x002E, backup[10]);
3063 b43_phy_write(dev, 0x002F, backup[11]);
3064 b43_phy_write(dev, 0x080F, backup[12]);
3065 b43_phy_write(dev, B43_PHY_G_LO_CONTROL, backup[13]);
3066 }
3067 if (phy->rev >= 2) {
3068 b43_phy_write(dev, 0x0812,
3069 b43_phy_read(dev, 0x0812) & 0xFFCF);
3070 b43_phy_write(dev, 0x0811,
3071 b43_phy_read(dev, 0x0811) & 0xFFCF);
3072 }
3073
3074 b43_radio_write16(dev, 0x007A, backup[0]);
3075 b43_radio_write16(dev, 0x0052, backup[1]);
3076 b43_radio_write16(dev, 0x0043, backup[2]);
3077 b43_write16(dev, 0x03E2, backup[7]);
3078 b43_write16(dev, 0x03E6, backup[8]);
3079 b43_write16(dev, B43_MMIO_CHANNEL_EXT, backup[9]);
3080 b43_phy_write(dev, 0x0015, backup[3]);
3081 b43_phy_write(dev, 0x005A, backup[4]);
3082 b43_phy_write(dev, 0x0059, backup[5]);
3083 b43_phy_write(dev, 0x0058, backup[6]);
3084 b43_synth_pu_workaround(dev, phy->channel);
3085 b43_phy_write(dev, 0x0802,
3086 b43_phy_read(dev, 0x0802) | (0x0001 | 0x0002));
3087 b43_set_original_gains(dev);
3088 b43_phy_write(dev, B43_PHY_G_CRS,
3089 b43_phy_read(dev, B43_PHY_G_CRS) | 0x8000);
3090 if (phy->rev >= 3) {
3091 b43_phy_write(dev, 0x0801, backup[14]);
3092 b43_phy_write(dev, 0x0060, backup[15]);
3093 b43_phy_write(dev, 0x0014, backup[16]);
3094 b43_phy_write(dev, 0x0478, backup[17]);
3095 }
3096 b43_nrssi_mem_update(dev);
3097 b43_calc_nrssi_threshold(dev);
3098 break;
3099 default:
3100 B43_WARN_ON(1);
3101 }
3102 }
3103
3104 void b43_calc_nrssi_threshold(struct b43_wldev *dev)
3105 {
3106 struct b43_phy *phy = &dev->phy;
3107 s32 threshold;
3108 s32 a, b;
3109 s16 tmp16;
3110 u16 tmp_u16;
3111
3112 switch (phy->type) {
3113 case B43_PHYTYPE_B:{
3114 if (phy->radio_ver != 0x2050)
3115 return;
3116 if (!
3117 (dev->dev->bus->sprom.r1.
3118 boardflags_lo & B43_BFL_RSSI))
3119 return;
3120
3121 if (phy->radio_rev >= 6) {
3122 threshold =
3123 (phy->nrssi[1] - phy->nrssi[0]) * 32;
3124 threshold += 20 * (phy->nrssi[0] + 1);
3125 threshold /= 40;
3126 } else
3127 threshold = phy->nrssi[1] - 5;
3128
3129 threshold = limit_value(threshold, 0, 0x3E);
3130 b43_phy_read(dev, 0x0020); /* dummy read */
3131 b43_phy_write(dev, 0x0020,
3132 (((u16) threshold) << 8) | 0x001C);
3133
3134 if (phy->radio_rev >= 6) {
3135 b43_phy_write(dev, 0x0087, 0x0E0D);
3136 b43_phy_write(dev, 0x0086, 0x0C0B);
3137 b43_phy_write(dev, 0x0085, 0x0A09);
3138 b43_phy_write(dev, 0x0084, 0x0808);
3139 b43_phy_write(dev, 0x0083, 0x0808);
3140 b43_phy_write(dev, 0x0082, 0x0604);
3141 b43_phy_write(dev, 0x0081, 0x0302);
3142 b43_phy_write(dev, 0x0080, 0x0100);
3143 }
3144 break;
3145 }
3146 case B43_PHYTYPE_G:
3147 if (!phy->gmode ||
3148 !(dev->dev->bus->sprom.r1.boardflags_lo & B43_BFL_RSSI)) {
3149 tmp16 = b43_nrssi_hw_read(dev, 0x20);
3150 if (tmp16 >= 0x20)
3151 tmp16 -= 0x40;
3152 if (tmp16 < 3) {
3153 b43_phy_write(dev, 0x048A,
3154 (b43_phy_read(dev, 0x048A)
3155 & 0xF000) | 0x09EB);
3156 } else {
3157 b43_phy_write(dev, 0x048A,
3158 (b43_phy_read(dev, 0x048A)
3159 & 0xF000) | 0x0AED);
3160 }
3161 } else {
3162 if (phy->interfmode == B43_INTERFMODE_NONWLAN) {
3163 a = 0xE;
3164 b = 0xA;
3165 } else if (!phy->aci_wlan_automatic && phy->aci_enable) {
3166 a = 0x13;
3167 b = 0x12;
3168 } else {
3169 a = 0xE;
3170 b = 0x11;
3171 }
3172
3173 a = a * (phy->nrssi[1] - phy->nrssi[0]);
3174 a += (phy->nrssi[0] << 6);
3175 if (a < 32)
3176 a += 31;
3177 else
3178 a += 32;
3179 a = a >> 6;
3180 a = limit_value(a, -31, 31);
3181
3182 b = b * (phy->nrssi[1] - phy->nrssi[0]);
3183 b += (phy->nrssi[0] << 6);
3184 if (b < 32)
3185 b += 31;
3186 else
3187 b += 32;
3188 b = b >> 6;
3189 b = limit_value(b, -31, 31);
3190
3191 tmp_u16 = b43_phy_read(dev, 0x048A) & 0xF000;
3192 tmp_u16 |= ((u32) b & 0x0000003F);
3193 tmp_u16 |= (((u32) a & 0x0000003F) << 6);
3194 b43_phy_write(dev, 0x048A, tmp_u16);
3195 }
3196 break;
3197 default:
3198 B43_WARN_ON(1);
3199 }
3200 }
3201
3202 /* Stack implementation to save/restore values from the
3203 * interference mitigation code.
3204 * It is save to restore values in random order.
3205 */
3206 static void _stack_save(u32 * _stackptr, size_t * stackidx,
3207 u8 id, u16 offset, u16 value)
3208 {
3209 u32 *stackptr = &(_stackptr[*stackidx]);
3210
3211 B43_WARN_ON(offset & 0xF000);
3212 B43_WARN_ON(id & 0xF0);
3213 *stackptr = offset;
3214 *stackptr |= ((u32) id) << 12;
3215 *stackptr |= ((u32) value) << 16;
3216 (*stackidx)++;
3217 B43_WARN_ON(*stackidx >= B43_INTERFSTACK_SIZE);
3218 }
3219
3220 static u16 _stack_restore(u32 * stackptr, u8 id, u16 offset)
3221 {
3222 size_t i;
3223
3224 B43_WARN_ON(offset & 0xF000);
3225 B43_WARN_ON(id & 0xF0);
3226 for (i = 0; i < B43_INTERFSTACK_SIZE; i++, stackptr++) {
3227 if ((*stackptr & 0x00000FFF) != offset)
3228 continue;
3229 if (((*stackptr & 0x0000F000) >> 12) != id)
3230 continue;
3231 return ((*stackptr & 0xFFFF0000) >> 16);
3232 }
3233 B43_WARN_ON(1);
3234
3235 return 0;
3236 }
3237
3238 #define phy_stacksave(offset) \
3239 do { \
3240 _stack_save(stack, &stackidx, 0x1, (offset), \
3241 b43_phy_read(dev, (offset))); \
3242 } while (0)
3243 #define phy_stackrestore(offset) \
3244 do { \
3245 b43_phy_write(dev, (offset), \
3246 _stack_restore(stack, 0x1, \
3247 (offset))); \
3248 } while (0)
3249 #define radio_stacksave(offset) \
3250 do { \
3251 _stack_save(stack, &stackidx, 0x2, (offset), \
3252 b43_radio_read16(dev, (offset))); \
3253 } while (0)
3254 #define radio_stackrestore(offset) \
3255 do { \
3256 b43_radio_write16(dev, (offset), \
3257 _stack_restore(stack, 0x2, \
3258 (offset))); \
3259 } while (0)
3260 #define ofdmtab_stacksave(table, offset) \
3261 do { \
3262 _stack_save(stack, &stackidx, 0x3, (offset)|(table), \
3263 b43_ofdmtab_read16(dev, (table), (offset))); \
3264 } while (0)
3265 #define ofdmtab_stackrestore(table, offset) \
3266 do { \
3267 b43_ofdmtab_write16(dev, (table), (offset), \
3268 _stack_restore(stack, 0x3, \
3269 (offset)|(table))); \
3270 } while (0)
3271
3272 static void
3273 b43_radio_interference_mitigation_enable(struct b43_wldev *dev, int mode)
3274 {
3275 struct b43_phy *phy = &dev->phy;
3276 u16 tmp, flipped;
3277 size_t stackidx = 0;
3278 u32 *stack = phy->interfstack;
3279
3280 switch (mode) {
3281 case B43_INTERFMODE_NONWLAN:
3282 if (phy->rev != 1) {
3283 b43_phy_write(dev, 0x042B,
3284 b43_phy_read(dev, 0x042B) | 0x0800);
3285 b43_phy_write(dev, B43_PHY_G_CRS,
3286 b43_phy_read(dev,
3287 B43_PHY_G_CRS) & ~0x4000);
3288 break;
3289 }
3290 radio_stacksave(0x0078);
3291 tmp = (b43_radio_read16(dev, 0x0078) & 0x001E);
3292 flipped = flip_4bit(tmp);
3293 if (flipped < 10 && flipped >= 8)
3294 flipped = 7;
3295 else if (flipped >= 10)
3296 flipped -= 3;
3297 flipped = flip_4bit(flipped);
3298 flipped = (flipped << 1) | 0x0020;
3299 b43_radio_write16(dev, 0x0078, flipped);
3300
3301 b43_calc_nrssi_threshold(dev);
3302
3303 phy_stacksave(0x0406);
3304 b43_phy_write(dev, 0x0406, 0x7E28);
3305
3306 b43_phy_write(dev, 0x042B, b43_phy_read(dev, 0x042B) | 0x0800);
3307 b43_phy_write(dev, B43_PHY_RADIO_BITFIELD,
3308 b43_phy_read(dev,
3309 B43_PHY_RADIO_BITFIELD) | 0x1000);
3310
3311 phy_stacksave(0x04A0);
3312 b43_phy_write(dev, 0x04A0,
3313 (b43_phy_read(dev, 0x04A0) & 0xC0C0) | 0x0008);
3314 phy_stacksave(0x04A1);
3315 b43_phy_write(dev, 0x04A1,
3316 (b43_phy_read(dev, 0x04A1) & 0xC0C0) | 0x0605);
3317 phy_stacksave(0x04A2);
3318 b43_phy_write(dev, 0x04A2,
3319 (b43_phy_read(dev, 0x04A2) & 0xC0C0) | 0x0204);
3320 phy_stacksave(0x04A8);
3321 b43_phy_write(dev, 0x04A8,
3322 (b43_phy_read(dev, 0x04A8) & 0xC0C0) | 0x0803);
3323 phy_stacksave(0x04AB);
3324 b43_phy_write(dev, 0x04AB,
3325 (b43_phy_read(dev, 0x04AB) & 0xC0C0) | 0x0605);
3326
3327 phy_stacksave(0x04A7);
3328 b43_phy_write(dev, 0x04A7, 0x0002);
3329 phy_stacksave(0x04A3);
3330 b43_phy_write(dev, 0x04A3, 0x287A);
3331 phy_stacksave(0x04A9);
3332 b43_phy_write(dev, 0x04A9, 0x2027);
3333 phy_stacksave(0x0493);
3334 b43_phy_write(dev, 0x0493, 0x32F5);
3335 phy_stacksave(0x04AA);
3336 b43_phy_write(dev, 0x04AA, 0x2027);
3337 phy_stacksave(0x04AC);
3338 b43_phy_write(dev, 0x04AC, 0x32F5);
3339 break;
3340 case B43_INTERFMODE_MANUALWLAN:
3341 if (b43_phy_read(dev, 0x0033) & 0x0800)
3342 break;
3343
3344 phy->aci_enable = 1;
3345
3346 phy_stacksave(B43_PHY_RADIO_BITFIELD);
3347 phy_stacksave(B43_PHY_G_CRS);
3348 if (phy->rev < 2) {
3349 phy_stacksave(0x0406);
3350 } else {
3351 phy_stacksave(0x04C0);
3352 phy_stacksave(0x04C1);
3353 }
3354 phy_stacksave(0x0033);
3355 phy_stacksave(0x04A7);
3356 phy_stacksave(0x04A3);
3357 phy_stacksave(0x04A9);
3358 phy_stacksave(0x04AA);
3359 phy_stacksave(0x04AC);
3360 phy_stacksave(0x0493);
3361 phy_stacksave(0x04A1);
3362 phy_stacksave(0x04A0);
3363 phy_stacksave(0x04A2);
3364 phy_stacksave(0x048A);
3365 phy_stacksave(0x04A8);
3366 phy_stacksave(0x04AB);
3367 if (phy->rev == 2) {
3368 phy_stacksave(0x04AD);
3369 phy_stacksave(0x04AE);
3370 } else if (phy->rev >= 3) {
3371 phy_stacksave(0x04AD);
3372 phy_stacksave(0x0415);
3373 phy_stacksave(0x0416);
3374 phy_stacksave(0x0417);
3375 ofdmtab_stacksave(0x1A00, 0x2);
3376 ofdmtab_stacksave(0x1A00, 0x3);
3377 }
3378 phy_stacksave(0x042B);
3379 phy_stacksave(0x048C);
3380
3381 b43_phy_write(dev, B43_PHY_RADIO_BITFIELD,
3382 b43_phy_read(dev, B43_PHY_RADIO_BITFIELD)
3383 & ~0x1000);
3384 b43_phy_write(dev, B43_PHY_G_CRS,
3385 (b43_phy_read(dev, B43_PHY_G_CRS)
3386 & 0xFFFC) | 0x0002);
3387
3388 b43_phy_write(dev, 0x0033, 0x0800);
3389 b43_phy_write(dev, 0x04A3, 0x2027);
3390 b43_phy_write(dev, 0x04A9, 0x1CA8);
3391 b43_phy_write(dev, 0x0493, 0x287A);
3392 b43_phy_write(dev, 0x04AA, 0x1CA8);
3393 b43_phy_write(dev, 0x04AC, 0x287A);
3394
3395 b43_phy_write(dev, 0x04A0, (b43_phy_read(dev, 0x04A0)
3396 & 0xFFC0) | 0x001A);
3397 b43_phy_write(dev, 0x04A7, 0x000D);
3398
3399 if (phy->rev < 2) {
3400 b43_phy_write(dev, 0x0406, 0xFF0D);
3401 } else if (phy->rev == 2) {
3402 b43_phy_write(dev, 0x04C0, 0xFFFF);
3403 b43_phy_write(dev, 0x04C1, 0x00A9);
3404 } else {
3405 b43_phy_write(dev, 0x04C0, 0x00C1);
3406 b43_phy_write(dev, 0x04C1, 0x0059);
3407 }
3408
3409 b43_phy_write(dev, 0x04A1, (b43_phy_read(dev, 0x04A1)
3410 & 0xC0FF) | 0x1800);
3411 b43_phy_write(dev, 0x04A1, (b43_phy_read(dev, 0x04A1)
3412 & 0xFFC0) | 0x0015);
3413 b43_phy_write(dev, 0x04A8, (b43_phy_read(dev, 0x04A8)
3414 & 0xCFFF) | 0x1000);
3415 b43_phy_write(dev, 0x04A8, (b43_phy_read(dev, 0x04A8)
3416 & 0xF0FF) | 0x0A00);
3417 b43_phy_write(dev, 0x04AB, (b43_phy_read(dev, 0x04AB)
3418 & 0xCFFF) | 0x1000);
3419 b43_phy_write(dev, 0x04AB, (b43_phy_read(dev, 0x04AB)
3420 & 0xF0FF) | 0x0800);
3421 b43_phy_write(dev, 0x04AB, (b43_phy_read(dev, 0x04AB)
3422 & 0xFFCF) | 0x0010);
3423 b43_phy_write(dev, 0x04AB, (b43_phy_read(dev, 0x04AB)
3424 & 0xFFF0) | 0x0005);
3425 b43_phy_write(dev, 0x04A8, (b43_phy_read(dev, 0x04A8)
3426 & 0xFFCF) | 0x0010);
3427 b43_phy_write(dev, 0x04A8, (b43_phy_read(dev, 0x04A8)
3428 & 0xFFF0) | 0x0006);
3429 b43_phy_write(dev, 0x04A2, (b43_phy_read(dev, 0x04A2)
3430 & 0xF0FF) | 0x0800);
3431 b43_phy_write(dev, 0x04A0, (b43_phy_read(dev, 0x04A0)
3432 & 0xF0FF) | 0x0500);
3433 b43_phy_write(dev, 0x04A2, (b43_phy_read(dev, 0x04A2)
3434 & 0xFFF0) | 0x000B);
3435
3436 if (phy->rev >= 3) {
3437 b43_phy_write(dev, 0x048A, b43_phy_read(dev, 0x048A)
3438 & ~0x8000);
3439 b43_phy_write(dev, 0x0415, (b43_phy_read(dev, 0x0415)
3440 & 0x8000) | 0x36D8);
3441 b43_phy_write(dev, 0x0416, (b43_phy_read(dev, 0x0416)
3442 & 0x8000) | 0x36D8);
3443 b43_phy_write(dev, 0x0417, (b43_phy_read(dev, 0x0417)
3444 & 0xFE00) | 0x016D);
3445 } else {
3446 b43_phy_write(dev, 0x048A, b43_phy_read(dev, 0x048A)
3447 | 0x1000);
3448 b43_phy_write(dev, 0x048A, (b43_phy_read(dev, 0x048A)
3449 & 0x9FFF) | 0x2000);
3450 b43_hf_write(dev, b43_hf_read(dev) | B43_HF_ACIW);
3451 }
3452 if (phy->rev >= 2) {
3453 b43_phy_write(dev, 0x042B, b43_phy_read(dev, 0x042B)
3454 | 0x0800);
3455 }
3456 b43_phy_write(dev, 0x048C, (b43_phy_read(dev, 0x048C)
3457 & 0xF0FF) | 0x0200);
3458 if (phy->rev == 2) {
3459 b43_phy_write(dev, 0x04AE, (b43_phy_read(dev, 0x04AE)
3460 & 0xFF00) | 0x007F);
3461 b43_phy_write(dev, 0x04AD, (b43_phy_read(dev, 0x04AD)
3462 & 0x00FF) | 0x1300);
3463 } else if (phy->rev >= 6) {
3464 b43_ofdmtab_write16(dev, 0x1A00, 0x3, 0x007F);
3465 b43_ofdmtab_write16(dev, 0x1A00, 0x2, 0x007F);
3466 b43_phy_write(dev, 0x04AD, b43_phy_read(dev, 0x04AD)
3467 & 0x00FF);
3468 }
3469 b43_calc_nrssi_slope(dev);
3470 break;
3471 default:
3472 B43_WARN_ON(1);
3473 }
3474 }
3475
3476 static void
3477 b43_radio_interference_mitigation_disable(struct b43_wldev *dev, int mode)
3478 {
3479 struct b43_phy *phy = &dev->phy;
3480 u32 *stack = phy->interfstack;
3481
3482 switch (mode) {
3483 case B43_INTERFMODE_NONWLAN:
3484 if (phy->rev != 1) {
3485 b43_phy_write(dev, 0x042B,
3486 b43_phy_read(dev, 0x042B) & ~0x0800);
3487 b43_phy_write(dev, B43_PHY_G_CRS,
3488 b43_phy_read(dev,
3489 B43_PHY_G_CRS) | 0x4000);
3490 break;
3491 }
3492 radio_stackrestore(0x0078);
3493 b43_calc_nrssi_threshold(dev);
3494 phy_stackrestore(0x0406);
3495 b43_phy_write(dev, 0x042B, b43_phy_read(dev, 0x042B) & ~0x0800);
3496 if (!dev->bad_frames_preempt) {
3497 b43_phy_write(dev, B43_PHY_RADIO_BITFIELD,
3498 b43_phy_read(dev, B43_PHY_RADIO_BITFIELD)
3499 & ~(1 << 11));
3500 }
3501 b43_phy_write(dev, B43_PHY_G_CRS,
3502 b43_phy_read(dev, B43_PHY_G_CRS) | 0x4000);
3503 phy_stackrestore(0x04A0);
3504 phy_stackrestore(0x04A1);
3505 phy_stackrestore(0x04A2);
3506 phy_stackrestore(0x04A8);
3507 phy_stackrestore(0x04AB);
3508 phy_stackrestore(0x04A7);
3509 phy_stackrestore(0x04A3);
3510 phy_stackrestore(0x04A9);
3511 phy_stackrestore(0x0493);
3512 phy_stackrestore(0x04AA);
3513 phy_stackrestore(0x04AC);
3514 break;
3515 case B43_INTERFMODE_MANUALWLAN:
3516 if (!(b43_phy_read(dev, 0x0033) & 0x0800))
3517 break;
3518
3519 phy->aci_enable = 0;
3520
3521 phy_stackrestore(B43_PHY_RADIO_BITFIELD);
3522 phy_stackrestore(B43_PHY_G_CRS);
3523 phy_stackrestore(0x0033);
3524 phy_stackrestore(0x04A3);
3525 phy_stackrestore(0x04A9);
3526 phy_stackrestore(0x0493);
3527 phy_stackrestore(0x04AA);
3528 phy_stackrestore(0x04AC);
3529 phy_stackrestore(0x04A0);
3530 phy_stackrestore(0x04A7);
3531 if (phy->rev >= 2) {
3532 phy_stackrestore(0x04C0);
3533 phy_stackrestore(0x04C1);
3534 } else
3535 phy_stackrestore(0x0406);
3536 phy_stackrestore(0x04A1);
3537 phy_stackrestore(0x04AB);
3538 phy_stackrestore(0x04A8);
3539 if (phy->rev == 2) {
3540 phy_stackrestore(0x04AD);
3541 phy_stackrestore(0x04AE);
3542 } else if (phy->rev >= 3) {
3543 phy_stackrestore(0x04AD);
3544 phy_stackrestore(0x0415);
3545 phy_stackrestore(0x0416);
3546 phy_stackrestore(0x0417);
3547 ofdmtab_stackrestore(0x1A00, 0x2);
3548 ofdmtab_stackrestore(0x1A00, 0x3);
3549 }
3550 phy_stackrestore(0x04A2);
3551 phy_stackrestore(0x048A);
3552 phy_stackrestore(0x042B);
3553 phy_stackrestore(0x048C);
3554 b43_hf_write(dev, b43_hf_read(dev) & ~B43_HF_ACIW);
3555 b43_calc_nrssi_slope(dev);
3556 break;
3557 default:
3558 B43_WARN_ON(1);
3559 }
3560 }
3561
3562 #undef phy_stacksave
3563 #undef phy_stackrestore
3564 #undef radio_stacksave
3565 #undef radio_stackrestore
3566 #undef ofdmtab_stacksave
3567 #undef ofdmtab_stackrestore
3568
3569 int b43_radio_set_interference_mitigation(struct b43_wldev *dev, int mode)
3570 {
3571 struct b43_phy *phy = &dev->phy;
3572 int currentmode;
3573
3574 if ((phy->type != B43_PHYTYPE_G) || (phy->rev == 0) || (!phy->gmode))
3575 return -ENODEV;
3576
3577 phy->aci_wlan_automatic = 0;
3578 switch (mode) {
3579 case B43_INTERFMODE_AUTOWLAN:
3580 phy->aci_wlan_automatic = 1;
3581 if (phy->aci_enable)
3582 mode = B43_INTERFMODE_MANUALWLAN;
3583 else
3584 mode = B43_INTERFMODE_NONE;
3585 break;
3586 case B43_INTERFMODE_NONE:
3587 case B43_INTERFMODE_NONWLAN:
3588 case B43_INTERFMODE_MANUALWLAN:
3589 break;
3590 default:
3591 return -EINVAL;
3592 }
3593
3594 currentmode = phy->interfmode;
3595 if (currentmode == mode)
3596 return 0;
3597 if (currentmode != B43_INTERFMODE_NONE)
3598 b43_radio_interference_mitigation_disable(dev, currentmode);
3599
3600 if (mode == B43_INTERFMODE_NONE) {
3601 phy->aci_enable = 0;
3602 phy->aci_hw_rssi = 0;
3603 } else
3604 b43_radio_interference_mitigation_enable(dev, mode);
3605 phy->interfmode = mode;
3606
3607 return 0;
3608 }
3609
3610 static u16 b43_radio_core_calibration_value(struct b43_wldev *dev)
3611 {
3612 u16 reg, index, ret;
3613
3614 static const u8 rcc_table[] = {
3615 0x02, 0x03, 0x01, 0x0F,
3616 0x06, 0x07, 0x05, 0x0F,
3617 0x0A, 0x0B, 0x09, 0x0F,
3618 0x0E, 0x0F, 0x0D, 0x0F,
3619 };
3620
3621 reg = b43_radio_read16(dev, 0x60);
3622 index = (reg & 0x001E) >> 1;
3623 ret = rcc_table[index] << 1;
3624 ret |= (reg & 0x0001);
3625 ret |= 0x0020;
3626
3627 return ret;
3628 }
3629
3630 #define LPD(L, P, D) (((L) << 2) | ((P) << 1) | ((D) << 0))
3631 static u16 radio2050_rfover_val(struct b43_wldev *dev,
3632 u16 phy_register, unsigned int lpd)
3633 {
3634 struct b43_phy *phy = &dev->phy;
3635 struct ssb_sprom *sprom = &(dev->dev->bus->sprom);
3636
3637 if (!phy->gmode)
3638 return 0;
3639
3640 if (has_loopback_gain(phy)) {
3641 int max_lb_gain = phy->max_lb_gain;
3642 u16 extlna;
3643 u16 i;
3644
3645 if (phy->radio_rev == 8)
3646 max_lb_gain += 0x3E;
3647 else
3648 max_lb_gain += 0x26;
3649 if (max_lb_gain >= 0x46) {
3650 extlna = 0x3000;
3651 max_lb_gain -= 0x46;
3652 } else if (max_lb_gain >= 0x3A) {
3653 extlna = 0x1000;
3654 max_lb_gain -= 0x3A;
3655 } else if (max_lb_gain >= 0x2E) {
3656 extlna = 0x2000;
3657 max_lb_gain -= 0x2E;
3658 } else {
3659 extlna = 0;
3660 max_lb_gain -= 0x10;
3661 }
3662
3663 for (i = 0; i < 16; i++) {
3664 max_lb_gain -= (i * 6);
3665 if (max_lb_gain < 6)
3666 break;
3667 }
3668
3669 if ((phy->rev < 7) ||
3670 !(sprom->r1.boardflags_lo & B43_BFL_EXTLNA)) {
3671 if (phy_register == B43_PHY_RFOVER) {
3672 return 0x1B3;
3673 } else if (phy_register == B43_PHY_RFOVERVAL) {
3674 extlna |= (i << 8);
3675 switch (lpd) {
3676 case LPD(0, 1, 1):
3677 return 0x0F92;
3678 case LPD(0, 0, 1):
3679 case LPD(1, 0, 1):
3680 return (0x0092 | extlna);
3681 case LPD(1, 0, 0):
3682 return (0x0093 | extlna);
3683 }
3684 B43_WARN_ON(1);
3685 }
3686 B43_WARN_ON(1);
3687 } else {
3688 if (phy_register == B43_PHY_RFOVER) {
3689 return 0x9B3;
3690 } else if (phy_register == B43_PHY_RFOVERVAL) {
3691 if (extlna)
3692 extlna |= 0x8000;
3693 extlna |= (i << 8);
3694 switch (lpd) {
3695 case LPD(0, 1, 1):
3696 return 0x8F92;
3697 case LPD(0, 0, 1):
3698 return (0x8092 | extlna);
3699 case LPD(1, 0, 1):
3700 return (0x2092 | extlna);
3701 case LPD(1, 0, 0):
3702 return (0x2093 | extlna);
3703 }
3704 B43_WARN_ON(1);
3705 }
3706 B43_WARN_ON(1);
3707 }
3708 } else {
3709 if ((phy->rev < 7) ||
3710 !(sprom->r1.boardflags_lo & B43_BFL_EXTLNA)) {
3711 if (phy_register == B43_PHY_RFOVER) {
3712 return 0x1B3;
3713 } else if (phy_register == B43_PHY_RFOVERVAL) {
3714 switch (lpd) {
3715 case LPD(0, 1, 1):
3716 return 0x0FB2;
3717 case LPD(0, 0, 1):
3718 return 0x00B2;
3719 case LPD(1, 0, 1):
3720 return 0x30B2;
3721 case LPD(1, 0, 0):
3722 return 0x30B3;
3723 }
3724 B43_WARN_ON(1);
3725 }
3726 B43_WARN_ON(1);
3727 } else {
3728 if (phy_register == B43_PHY_RFOVER) {
3729 return 0x9B3;
3730 } else if (phy_register == B43_PHY_RFOVERVAL) {
3731 switch (lpd) {
3732 case LPD(0, 1, 1):
3733 return 0x8FB2;
3734 case LPD(0, 0, 1):
3735 return 0x80B2;
3736 case LPD(1, 0, 1):
3737 return 0x20B2;
3738 case LPD(1, 0, 0):
3739 return 0x20B3;
3740 }
3741 B43_WARN_ON(1);
3742 }
3743 B43_WARN_ON(1);
3744 }
3745 }
3746 return 0;
3747 }
3748
3749 struct init2050_saved_values {
3750 /* Core registers */
3751 u16 reg_3EC;
3752 u16 reg_3E6;
3753 u16 reg_3F4;
3754 /* Radio registers */
3755 u16 radio_43;
3756 u16 radio_51;
3757 u16 radio_52;
3758 /* PHY registers */
3759 u16 phy_pgactl;
3760 u16 phy_base_5A;
3761 u16 phy_base_59;
3762 u16 phy_base_58;
3763 u16 phy_base_30;
3764 u16 phy_rfover;
3765 u16 phy_rfoverval;
3766 u16 phy_analogover;
3767 u16 phy_analogoverval;
3768 u16 phy_crs0;
3769 u16 phy_classctl;
3770 u16 phy_lo_mask;
3771 u16 phy_lo_ctl;
3772 u16 phy_syncctl;
3773 };
3774
3775 u16 b43_radio_init2050(struct b43_wldev *dev)
3776 {
3777 struct b43_phy *phy = &dev->phy;
3778 struct init2050_saved_values sav;
3779 u16 rcc;
3780 u16 radio78;
3781 u16 ret;
3782 u16 i, j;
3783 u32 tmp1 = 0, tmp2 = 0;
3784
3785 memset(&sav, 0, sizeof(sav)); /* get rid of "may be used uninitialized..." */
3786
3787 sav.radio_43 = b43_radio_read16(dev, 0x43);
3788 sav.radio_51 = b43_radio_read16(dev, 0x51);
3789 sav.radio_52 = b43_radio_read16(dev, 0x52);
3790 sav.phy_pgactl = b43_phy_read(dev, B43_PHY_PGACTL);
3791 sav.phy_base_5A = b43_phy_read(dev, B43_PHY_BASE(0x5A));
3792 sav.phy_base_59 = b43_phy_read(dev, B43_PHY_BASE(0x59));
3793 sav.phy_base_58 = b43_phy_read(dev, B43_PHY_BASE(0x58));
3794
3795 if (phy->type == B43_PHYTYPE_B) {
3796 sav.phy_base_30 = b43_phy_read(dev, B43_PHY_BASE(0x30));
3797 sav.reg_3EC = b43_read16(dev, 0x3EC);
3798
3799 b43_phy_write(dev, B43_PHY_BASE(0x30), 0xFF);
3800 b43_write16(dev, 0x3EC, 0x3F3F);
3801 } else if (phy->gmode || phy->rev >= 2) {
3802 sav.phy_rfover = b43_phy_read(dev, B43_PHY_RFOVER);
3803 sav.phy_rfoverval = b43_phy_read(dev, B43_PHY_RFOVERVAL);
3804 sav.phy_analogover = b43_phy_read(dev, B43_PHY_ANALOGOVER);
3805 sav.phy_analogoverval =
3806 b43_phy_read(dev, B43_PHY_ANALOGOVERVAL);
3807 sav.phy_crs0 = b43_phy_read(dev, B43_PHY_CRS0);
3808 sav.phy_classctl = b43_phy_read(dev, B43_PHY_CLASSCTL);
3809
3810 b43_phy_write(dev, B43_PHY_ANALOGOVER,
3811 b43_phy_read(dev, B43_PHY_ANALOGOVER)
3812 | 0x0003);
3813 b43_phy_write(dev, B43_PHY_ANALOGOVERVAL,
3814 b43_phy_read(dev, B43_PHY_ANALOGOVERVAL)
3815 & 0xFFFC);
3816 b43_phy_write(dev, B43_PHY_CRS0, b43_phy_read(dev, B43_PHY_CRS0)
3817 & 0x7FFF);
3818 b43_phy_write(dev, B43_PHY_CLASSCTL,
3819 b43_phy_read(dev, B43_PHY_CLASSCTL)
3820 & 0xFFFC);
3821 if (has_loopback_gain(phy)) {
3822 sav.phy_lo_mask = b43_phy_read(dev, B43_PHY_LO_MASK);
3823 sav.phy_lo_ctl = b43_phy_read(dev, B43_PHY_LO_CTL);
3824
3825 if (phy->rev >= 3)
3826 b43_phy_write(dev, B43_PHY_LO_MASK, 0xC020);
3827 else
3828 b43_phy_write(dev, B43_PHY_LO_MASK, 0x8020);
3829 b43_phy_write(dev, B43_PHY_LO_CTL, 0);
3830 }
3831
3832 b43_phy_write(dev, B43_PHY_RFOVERVAL,
3833 radio2050_rfover_val(dev, B43_PHY_RFOVERVAL,
3834 LPD(0, 1, 1)));
3835 b43_phy_write(dev, B43_PHY_RFOVER,
3836 radio2050_rfover_val(dev, B43_PHY_RFOVER, 0));
3837 }
3838 b43_write16(dev, 0x3E2, b43_read16(dev, 0x3E2) | 0x8000);
3839
3840 sav.phy_syncctl = b43_phy_read(dev, B43_PHY_SYNCCTL);
3841 b43_phy_write(dev, B43_PHY_SYNCCTL, b43_phy_read(dev, B43_PHY_SYNCCTL)
3842 & 0xFF7F);
3843 sav.reg_3E6 = b43_read16(dev, 0x3E6);
3844 sav.reg_3F4 = b43_read16(dev, 0x3F4);
3845
3846 if (phy->analog == 0) {
3847 b43_write16(dev, 0x03E6, 0x0122);
3848 } else {
3849 if (phy->analog >= 2) {
3850 b43_phy_write(dev, B43_PHY_BASE(0x03),
3851 (b43_phy_read(dev, B43_PHY_BASE(0x03))
3852 & 0xFFBF) | 0x40);
3853 }
3854 b43_write16(dev, B43_MMIO_CHANNEL_EXT,
3855 (b43_read16(dev, B43_MMIO_CHANNEL_EXT) | 0x2000));
3856 }
3857
3858 rcc = b43_radio_core_calibration_value(dev);
3859
3860 if (phy->type == B43_PHYTYPE_B)
3861 b43_radio_write16(dev, 0x78, 0x26);
3862 if (phy->gmode || phy->rev >= 2) {
3863 b43_phy_write(dev, B43_PHY_RFOVERVAL,
3864 radio2050_rfover_val(dev, B43_PHY_RFOVERVAL,
3865 LPD(0, 1, 1)));
3866 }
3867 b43_phy_write(dev, B43_PHY_PGACTL, 0xBFAF);
3868 b43_phy_write(dev, B43_PHY_BASE(0x2B), 0x1403);
3869 if (phy->gmode || phy->rev >= 2) {
3870 b43_phy_write(dev, B43_PHY_RFOVERVAL,
3871 radio2050_rfover_val(dev, B43_PHY_RFOVERVAL,
3872 LPD(0, 0, 1)));
3873 }
3874 b43_phy_write(dev, B43_PHY_PGACTL, 0xBFA0);
3875 b43_radio_write16(dev, 0x51, b43_radio_read16(dev, 0x51)
3876 | 0x0004);
3877 if (phy->radio_rev == 8) {
3878 b43_radio_write16(dev, 0x43, 0x1F);
3879 } else {
3880 b43_radio_write16(dev, 0x52, 0);
3881 b43_radio_write16(dev, 0x43, (b43_radio_read16(dev, 0x43)
3882 & 0xFFF0) | 0x0009);
3883 }
3884 b43_phy_write(dev, B43_PHY_BASE(0x58), 0);
3885
3886 for (i = 0; i < 16; i++) {
3887 b43_phy_write(dev, B43_PHY_BASE(0x5A), 0x0480);
3888 b43_phy_write(dev, B43_PHY_BASE(0x59), 0xC810);
3889 b43_phy_write(dev, B43_PHY_BASE(0x58), 0x000D);
3890 if (phy->gmode || phy->rev >= 2) {
3891 b43_phy_write(dev, B43_PHY_RFOVERVAL,
3892 radio2050_rfover_val(dev,
3893 B43_PHY_RFOVERVAL,
3894 LPD(1, 0, 1)));
3895 }
3896 b43_phy_write(dev, B43_PHY_PGACTL, 0xAFB0);
3897 udelay(10);
3898 if (phy->gmode || phy->rev >= 2) {
3899 b43_phy_write(dev, B43_PHY_RFOVERVAL,
3900 radio2050_rfover_val(dev,
3901 B43_PHY_RFOVERVAL,
3902 LPD(1, 0, 1)));
3903 }
3904 b43_phy_write(dev, B43_PHY_PGACTL, 0xEFB0);
3905 udelay(10);
3906 if (phy->gmode || phy->rev >= 2) {
3907 b43_phy_write(dev, B43_PHY_RFOVERVAL,
3908 radio2050_rfover_val(dev,
3909 B43_PHY_RFOVERVAL,
3910 LPD(1, 0, 0)));
3911 }
3912 b43_phy_write(dev, B43_PHY_PGACTL, 0xFFF0);
3913 udelay(20);
3914 tmp1 += b43_phy_read(dev, B43_PHY_LO_LEAKAGE);
3915 b43_phy_write(dev, B43_PHY_BASE(0x58), 0);
3916 if (phy->gmode || phy->rev >= 2) {
3917 b43_phy_write(dev, B43_PHY_RFOVERVAL,
3918 radio2050_rfover_val(dev,
3919 B43_PHY_RFOVERVAL,
3920 LPD(1, 0, 1)));
3921 }
3922 b43_phy_write(dev, B43_PHY_PGACTL, 0xAFB0);
3923 }
3924 udelay(10);
3925
3926 b43_phy_write(dev, B43_PHY_BASE(0x58), 0);
3927 tmp1++;
3928 tmp1 >>= 9;
3929
3930 for (i = 0; i < 16; i++) {
3931 radio78 = ((flip_4bit(i) << 1) | 0x20);
3932 b43_radio_write16(dev, 0x78, radio78);
3933 udelay(10);
3934 for (j = 0; j < 16; j++) {
3935 b43_phy_write(dev, B43_PHY_BASE(0x5A), 0x0D80);
3936 b43_phy_write(dev, B43_PHY_BASE(0x59), 0xC810);
3937 b43_phy_write(dev, B43_PHY_BASE(0x58), 0x000D);
3938 if (phy->gmode || phy->rev >= 2) {
3939 b43_phy_write(dev, B43_PHY_RFOVERVAL,
3940 radio2050_rfover_val(dev,
3941 B43_PHY_RFOVERVAL,
3942 LPD(1, 0,
3943 1)));
3944 }
3945 b43_phy_write(dev, B43_PHY_PGACTL, 0xAFB0);
3946 udelay(10);
3947 if (phy->gmode || phy->rev >= 2) {
3948 b43_phy_write(dev, B43_PHY_RFOVERVAL,
3949 radio2050_rfover_val(dev,
3950 B43_PHY_RFOVERVAL,
3951 LPD(1, 0,
3952 1)));
3953 }
3954 b43_phy_write(dev, B43_PHY_PGACTL, 0xEFB0);
3955 udelay(10);
3956 if (phy->gmode || phy->rev >= 2) {
3957 b43_phy_write(dev, B43_PHY_RFOVERVAL,
3958 radio2050_rfover_val(dev,
3959 B43_PHY_RFOVERVAL,
3960 LPD(1, 0,
3961 0)));
3962 }
3963 b43_phy_write(dev, B43_PHY_PGACTL, 0xFFF0);
3964 udelay(10);
3965 tmp2 += b43_phy_read(dev, B43_PHY_LO_LEAKAGE);
3966 b43_phy_write(dev, B43_PHY_BASE(0x58), 0);
3967 if (phy->gmode || phy->rev >= 2) {
3968 b43_phy_write(dev, B43_PHY_RFOVERVAL,
3969 radio2050_rfover_val(dev,
3970 B43_PHY_RFOVERVAL,
3971 LPD(1, 0,
3972 1)));
3973 }
3974 b43_phy_write(dev, B43_PHY_PGACTL, 0xAFB0);
3975 }
3976 tmp2++;
3977 tmp2 >>= 8;
3978 if (tmp1 < tmp2)
3979 break;
3980 }
3981
3982 /* Restore the registers */
3983 b43_phy_write(dev, B43_PHY_PGACTL, sav.phy_pgactl);
3984 b43_radio_write16(dev, 0x51, sav.radio_51);
3985 b43_radio_write16(dev, 0x52, sav.radio_52);
3986 b43_radio_write16(dev, 0x43, sav.radio_43);
3987 b43_phy_write(dev, B43_PHY_BASE(0x5A), sav.phy_base_5A);
3988 b43_phy_write(dev, B43_PHY_BASE(0x59), sav.phy_base_59);
3989 b43_phy_write(dev, B43_PHY_BASE(0x58), sav.phy_base_58);
3990 b43_write16(dev, 0x3E6, sav.reg_3E6);
3991 if (phy->analog != 0)
3992 b43_write16(dev, 0x3F4, sav.reg_3F4);
3993 b43_phy_write(dev, B43_PHY_SYNCCTL, sav.phy_syncctl);
3994 b43_synth_pu_workaround(dev, phy->channel);
3995 if (phy->type == B43_PHYTYPE_B) {
3996 b43_phy_write(dev, B43_PHY_BASE(0x30), sav.phy_base_30);
3997 b43_write16(dev, 0x3EC, sav.reg_3EC);
3998 } else if (phy->gmode) {
3999 b43_write16(dev, B43_MMIO_PHY_RADIO,
4000 b43_read16(dev, B43_MMIO_PHY_RADIO)
4001 & 0x7FFF);
4002 b43_phy_write(dev, B43_PHY_RFOVER, sav.phy_rfover);
4003 b43_phy_write(dev, B43_PHY_RFOVERVAL, sav.phy_rfoverval);
4004 b43_phy_write(dev, B43_PHY_ANALOGOVER, sav.phy_analogover);
4005 b43_phy_write(dev, B43_PHY_ANALOGOVERVAL,
4006 sav.phy_analogoverval);
4007 b43_phy_write(dev, B43_PHY_CRS0, sav.phy_crs0);
4008 b43_phy_write(dev, B43_PHY_CLASSCTL, sav.phy_classctl);
4009 if (has_loopback_gain(phy)) {
4010 b43_phy_write(dev, B43_PHY_LO_MASK, sav.phy_lo_mask);
4011 b43_phy_write(dev, B43_PHY_LO_CTL, sav.phy_lo_ctl);
4012 }
4013 }
4014 if (i > 15)
4015 ret = radio78;
4016 else
4017 ret = rcc;
4018
4019 return ret;
4020 }
4021
4022 void b43_radio_init2060(struct b43_wldev *dev)
4023 {
4024 int err;
4025
4026 b43_radio_write16(dev, 0x0004, 0x00C0);
4027 b43_radio_write16(dev, 0x0005, 0x0008);
4028 b43_radio_write16(dev, 0x0009, 0x0040);
4029 b43_radio_write16(dev, 0x0005, 0x00AA);
4030 b43_radio_write16(dev, 0x0032, 0x008F);
4031 b43_radio_write16(dev, 0x0006, 0x008F);
4032 b43_radio_write16(dev, 0x0034, 0x008F);
4033 b43_radio_write16(dev, 0x002C, 0x0007);
4034 b43_radio_write16(dev, 0x0082, 0x0080);
4035 b43_radio_write16(dev, 0x0080, 0x0000);
4036 b43_radio_write16(dev, 0x003F, 0x00DA);
4037 b43_radio_write16(dev, 0x0005, b43_radio_read16(dev, 0x0005) & ~0x0008);
4038 b43_radio_write16(dev, 0x0081, b43_radio_read16(dev, 0x0081) & ~0x0010);
4039 b43_radio_write16(dev, 0x0081, b43_radio_read16(dev, 0x0081) & ~0x0020);
4040 b43_radio_write16(dev, 0x0081, b43_radio_read16(dev, 0x0081) & ~0x0020);
4041 msleep(1); /* delay 400usec */
4042
4043 b43_radio_write16(dev, 0x0081,
4044 (b43_radio_read16(dev, 0x0081) & ~0x0020) | 0x0010);
4045 msleep(1); /* delay 400usec */
4046
4047 b43_radio_write16(dev, 0x0005,
4048 (b43_radio_read16(dev, 0x0005) & ~0x0008) | 0x0008);
4049 b43_radio_write16(dev, 0x0085, b43_radio_read16(dev, 0x0085) & ~0x0010);
4050 b43_radio_write16(dev, 0x0005, b43_radio_read16(dev, 0x0005) & ~0x0008);
4051 b43_radio_write16(dev, 0x0081, b43_radio_read16(dev, 0x0081) & ~0x0040);
4052 b43_radio_write16(dev, 0x0081,
4053 (b43_radio_read16(dev, 0x0081) & ~0x0040) | 0x0040);
4054 b43_radio_write16(dev, 0x0005,
4055 (b43_radio_read16(dev, 0x0081) & ~0x0008) | 0x0008);
4056 b43_phy_write(dev, 0x0063, 0xDDC6);
4057 b43_phy_write(dev, 0x0069, 0x07BE);
4058 b43_phy_write(dev, 0x006A, 0x0000);
4059
4060 err = b43_radio_selectchannel(dev, B43_DEFAULT_CHANNEL_A, 0);
4061 B43_WARN_ON(err);
4062
4063 msleep(1);
4064 }
4065
4066 static inline u16 freq_r3A_value(u16 frequency)
4067 {
4068 u16 value;
4069
4070 if (frequency < 5091)
4071 value = 0x0040;
4072 else if (frequency < 5321)
4073 value = 0x0000;
4074 else if (frequency < 5806)
4075 value = 0x0080;
4076 else
4077 value = 0x0040;
4078
4079 return value;
4080 }
4081
4082 void b43_radio_set_tx_iq(struct b43_wldev *dev)
4083 {
4084 static const u8 data_high[5] = { 0x00, 0x40, 0x80, 0x90, 0xD0 };
4085 static const u8 data_low[5] = { 0x00, 0x01, 0x05, 0x06, 0x0A };
4086 u16 tmp = b43_radio_read16(dev, 0x001E);
4087 int i, j;
4088
4089 for (i = 0; i < 5; i++) {
4090 for (j = 0; j < 5; j++) {
4091 if (tmp == (data_high[i] << 4 | data_low[j])) {
4092 b43_phy_write(dev, 0x0069,
4093 (i - j) << 8 | 0x00C0);
4094 return;
4095 }
4096 }
4097 }
4098 }
4099
4100 int b43_radio_selectchannel(struct b43_wldev *dev,
4101 u8 channel, int synthetic_pu_workaround)
4102 {
4103 struct b43_phy *phy = &dev->phy;
4104 u16 r8, tmp;
4105 u16 freq;
4106 u16 channelcookie;
4107
4108 if (channel == 0xFF) {
4109 switch (phy->type) {
4110 case B43_PHYTYPE_A:
4111 channel = B43_DEFAULT_CHANNEL_A;
4112 break;
4113 case B43_PHYTYPE_B:
4114 case B43_PHYTYPE_G:
4115 channel = B43_DEFAULT_CHANNEL_BG;
4116 break;
4117 default:
4118 B43_WARN_ON(1);
4119 }
4120 }
4121
4122 /* First we set the channel radio code to prevent the
4123 * firmware from sending ghost packets.
4124 */
4125 channelcookie = channel;
4126 if (phy->type == B43_PHYTYPE_A)
4127 channelcookie |= 0x100;
4128 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_CHAN, channelcookie);
4129
4130 if (phy->type == B43_PHYTYPE_A) {
4131 if (channel > 200)
4132 return -EINVAL;
4133 freq = channel2freq_a(channel);
4134
4135 r8 = b43_radio_read16(dev, 0x0008);
4136 b43_write16(dev, 0x03F0, freq);
4137 b43_radio_write16(dev, 0x0008, r8);
4138
4139 //TODO: write max channel TX power? to Radio 0x2D
4140 tmp = b43_radio_read16(dev, 0x002E);
4141 tmp &= 0x0080;
4142 //TODO: OR tmp with the Power out estimation for this channel?
4143 b43_radio_write16(dev, 0x002E, tmp);
4144
4145 if (freq >= 4920 && freq <= 5500) {
4146 /*
4147 * r8 = (((freq * 15 * 0xE1FC780F) >> 32) / 29) & 0x0F;
4148 * = (freq * 0.025862069
4149 */
4150 r8 = 3 * freq / 116; /* is equal to r8 = freq * 0.025862 */
4151 }
4152 b43_radio_write16(dev, 0x0007, (r8 << 4) | r8);
4153 b43_radio_write16(dev, 0x0020, (r8 << 4) | r8);
4154 b43_radio_write16(dev, 0x0021, (r8 << 4) | r8);
4155 b43_radio_write16(dev, 0x0022, (b43_radio_read16(dev, 0x0022)
4156 & 0x000F) | (r8 << 4));
4157 b43_radio_write16(dev, 0x002A, (r8 << 4));
4158 b43_radio_write16(dev, 0x002B, (r8 << 4));
4159 b43_radio_write16(dev, 0x0008, (b43_radio_read16(dev, 0x0008)
4160 & 0x00F0) | (r8 << 4));
4161 b43_radio_write16(dev, 0x0029, (b43_radio_read16(dev, 0x0029)
4162 & 0xFF0F) | 0x00B0);
4163 b43_radio_write16(dev, 0x0035, 0x00AA);
4164 b43_radio_write16(dev, 0x0036, 0x0085);
4165 b43_radio_write16(dev, 0x003A, (b43_radio_read16(dev, 0x003A)
4166 & 0xFF20) |
4167 freq_r3A_value(freq));
4168 b43_radio_write16(dev, 0x003D,
4169 b43_radio_read16(dev, 0x003D) & 0x00FF);
4170 b43_radio_write16(dev, 0x0081, (b43_radio_read16(dev, 0x0081)
4171 & 0xFF7F) | 0x0080);
4172 b43_radio_write16(dev, 0x0035,
4173 b43_radio_read16(dev, 0x0035) & 0xFFEF);
4174 b43_radio_write16(dev, 0x0035, (b43_radio_read16(dev, 0x0035)
4175 & 0xFFEF) | 0x0010);
4176 b43_radio_set_tx_iq(dev);
4177 //TODO: TSSI2dbm workaround
4178 b43_phy_xmitpower(dev); //FIXME correct?
4179 } else {
4180 if ((channel < 1) || (channel > 14))
4181 return -EINVAL;
4182
4183 if (synthetic_pu_workaround)
4184 b43_synth_pu_workaround(dev, channel);
4185
4186 b43_write16(dev, B43_MMIO_CHANNEL, channel2freq_bg(channel));
4187
4188 if (channel == 14) {
4189 if (dev->dev->bus->sprom.r1.country_code ==
4190 SSB_SPROM1CCODE_JAPAN)
4191 b43_hf_write(dev,
4192 b43_hf_read(dev) & ~B43_HF_ACPR);
4193 else
4194 b43_hf_write(dev,
4195 b43_hf_read(dev) | B43_HF_ACPR);
4196 b43_write16(dev, B43_MMIO_CHANNEL_EXT,
4197 b43_read16(dev, B43_MMIO_CHANNEL_EXT)
4198 | (1 << 11));
4199 } else {
4200 b43_write16(dev, B43_MMIO_CHANNEL_EXT,
4201 b43_read16(dev, B43_MMIO_CHANNEL_EXT)
4202 & 0xF7BF);
4203 }
4204 }
4205
4206 phy->channel = channel;
4207 /* Wait for the radio to tune to the channel and stabilize. */
4208 msleep(8);
4209
4210 return 0;
4211 }
4212
4213 /* http://bcm-specs.sipsolutions.net/TX_Gain_Base_Band */
4214 static u16 b43_get_txgain_base_band(u16 txpower)
4215 {
4216 u16 ret;
4217
4218 B43_WARN_ON(txpower > 63);
4219
4220 if (txpower >= 54)
4221 ret = 2;
4222 else if (txpower >= 49)
4223 ret = 4;
4224 else if (txpower >= 44)
4225 ret = 5;
4226 else
4227 ret = 6;
4228
4229 return ret;
4230 }
4231
4232 /* http://bcm-specs.sipsolutions.net/TX_Gain_Radio_Frequency_Power_Amplifier */
4233 static u16 b43_get_txgain_freq_power_amp(u16 txpower)
4234 {
4235 u16 ret;
4236
4237 B43_WARN_ON(txpower > 63);
4238
4239 if (txpower >= 32)
4240 ret = 0;
4241 else if (txpower >= 25)
4242 ret = 1;
4243 else if (txpower >= 20)
4244 ret = 2;
4245 else if (txpower >= 12)
4246 ret = 3;
4247 else
4248 ret = 4;
4249
4250 return ret;
4251 }
4252
4253 /* http://bcm-specs.sipsolutions.net/TX_Gain_Digital_Analog_Converter */
4254 static u16 b43_get_txgain_dac(u16 txpower)
4255 {
4256 u16 ret;
4257
4258 B43_WARN_ON(txpower > 63);
4259
4260 if (txpower >= 54)
4261 ret = txpower - 53;
4262 else if (txpower >= 49)
4263 ret = txpower - 42;
4264 else if (txpower >= 44)
4265 ret = txpower - 37;
4266 else if (txpower >= 32)
4267 ret = txpower - 32;
4268 else if (txpower >= 25)
4269 ret = txpower - 20;
4270 else if (txpower >= 20)
4271 ret = txpower - 13;
4272 else if (txpower >= 12)
4273 ret = txpower - 8;
4274 else
4275 ret = txpower;
4276
4277 return ret;
4278 }
4279
4280 static void b43_radio_set_txpower_a(struct b43_wldev *dev, u16 txpower)
4281 {
4282 struct b43_phy *phy = &dev->phy;
4283 u16 pamp, base, dac, t;
4284
4285 txpower = limit_value(txpower, 0, 63);
4286
4287 pamp = b43_get_txgain_freq_power_amp(txpower);
4288 pamp <<= 5;
4289 pamp &= 0x00E0;
4290 b43_phy_write(dev, 0x0019, pamp);
4291
4292 base = b43_get_txgain_base_band(txpower);
4293 base &= 0x000F;
4294 b43_phy_write(dev, 0x0017, base | 0x0020);
4295
4296 t = b43_ofdmtab_read16(dev, 0x3000, 1);
4297 t &= 0x0007;
4298
4299 dac = b43_get_txgain_dac(txpower);
4300 dac <<= 3;
4301 dac |= t;
4302
4303 b43_ofdmtab_write16(dev, 0x3000, 1, dac);
4304
4305 phy->txpwr_offset = txpower;
4306
4307 //TODO: FuncPlaceholder (Adjust BB loft cancel)
4308 }
4309
4310 void b43_radio_turn_on(struct b43_wldev *dev)
4311 {
4312 struct b43_phy *phy = &dev->phy;
4313 int err;
4314 u8 channel;
4315
4316 might_sleep();
4317
4318 if (phy->radio_on)
4319 return;
4320
4321 switch (phy->type) {
4322 case B43_PHYTYPE_A:
4323 b43_radio_write16(dev, 0x0004, 0x00C0);
4324 b43_radio_write16(dev, 0x0005, 0x0008);
4325 b43_phy_write(dev, 0x0010, b43_phy_read(dev, 0x0010) & 0xFFF7);
4326 b43_phy_write(dev, 0x0011, b43_phy_read(dev, 0x0011) & 0xFFF7);
4327 b43_radio_init2060(dev);
4328 break;
4329 case B43_PHYTYPE_B:
4330 case B43_PHYTYPE_G:
4331 b43_phy_write(dev, 0x0015, 0x8000);
4332 b43_phy_write(dev, 0x0015, 0xCC00);
4333 b43_phy_write(dev, 0x0015, (phy->gmode ? 0x00C0 : 0x0000));
4334 if (phy->radio_off_context.valid) {
4335 /* Restore the RFover values. */
4336 b43_phy_write(dev, B43_PHY_RFOVER,
4337 phy->radio_off_context.rfover);
4338 b43_phy_write(dev, B43_PHY_RFOVERVAL,
4339 phy->radio_off_context.rfoverval);
4340 phy->radio_off_context.valid = 0;
4341 }
4342 channel = phy->channel;
4343 err = b43_radio_selectchannel(dev, B43_DEFAULT_CHANNEL_BG, 1);
4344 err |= b43_radio_selectchannel(dev, channel, 0);
4345 B43_WARN_ON(err);
4346 break;
4347 default:
4348 B43_WARN_ON(1);
4349 }
4350 phy->radio_on = 1;
4351 }
4352
4353 void b43_radio_turn_off(struct b43_wldev *dev, bool force)
4354 {
4355 struct b43_phy *phy = &dev->phy;
4356
4357 if (!phy->radio_on && !force)
4358 return;
4359
4360 if (phy->type == B43_PHYTYPE_A) {
4361 b43_radio_write16(dev, 0x0004, 0x00FF);
4362 b43_radio_write16(dev, 0x0005, 0x00FB);
4363 b43_phy_write(dev, 0x0010, b43_phy_read(dev, 0x0010) | 0x0008);
4364 b43_phy_write(dev, 0x0011, b43_phy_read(dev, 0x0011) | 0x0008);
4365 }
4366 if (phy->type == B43_PHYTYPE_G && dev->dev->id.revision >= 5) {
4367 u16 rfover, rfoverval;
4368
4369 rfover = b43_phy_read(dev, B43_PHY_RFOVER);
4370 rfoverval = b43_phy_read(dev, B43_PHY_RFOVERVAL);
4371 if (!force) {
4372 phy->radio_off_context.rfover = rfover;
4373 phy->radio_off_context.rfoverval = rfoverval;
4374 phy->radio_off_context.valid = 1;
4375 }
4376 b43_phy_write(dev, B43_PHY_RFOVER, rfover | 0x008C);
4377 b43_phy_write(dev, B43_PHY_RFOVERVAL, rfoverval & 0xFF73);
4378 } else
4379 b43_phy_write(dev, 0x0015, 0xAA00);
4380 phy->radio_on = 0;
4381 }
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