drivers/net/wireless/b43/phy.h

   1 #ifndef B43_PHY_H_
   2 #define B43_PHY_H_
   3
   4 #include <linux/types.h>
   5
   6 struct b43_wldev;
   7 struct b43_phy;
   8
   9 /*** PHY Registers ***/
  10
  11 /* Routing */
  12 #define B43_PHYROUTE_OFDM_GPHY          0x400
  13 #define B43_PHYROUTE_EXT_GPHY           0x800
  14
  15 /* Base registers. */
  16 #define B43_PHY_BASE(reg)               (reg)
  17 /* OFDM (A) registers of a G-PHY */
  18 #define B43_PHY_OFDM(reg)               ((reg) | B43_PHYROUTE_OFDM_GPHY)
  19 /* Extended G-PHY registers */
  20 #define B43_PHY_EXTG(reg)               ((reg) | B43_PHYROUTE_EXT_GPHY)
  21
  22 /* OFDM (A) PHY Registers */
  23 #define B43_PHY_VERSION_OFDM            B43_PHY_OFDM(0x00)      /* Versioning register for A-PHY */
  24 #define B43_PHY_BBANDCFG                B43_PHY_OFDM(0x01)      /* Baseband config */
  25 #define  B43_PHY_BBANDCFG_RXANT         0x180   /* RX Antenna selection */
  26 #define  B43_PHY_BBANDCFG_RXANT_SHIFT   7
  27 #define B43_PHY_PWRDOWN                 B43_PHY_OFDM(0x03)      /* Powerdown */
  28 #define B43_PHY_CRSTHRES1               B43_PHY_OFDM(0x06)      /* CRS Threshold 1 */
  29 #define B43_PHY_LNAHPFCTL               B43_PHY_OFDM(0x1C)      /* LNA/HPF control */
  30 #define B43_PHY_ADIVRELATED             B43_PHY_OFDM(0x27)      /* FIXME rename */
  31 #define B43_PHY_CRS0                    B43_PHY_OFDM(0x29)
  32 #define B43_PHY_ANTDWELL                B43_PHY_OFDM(0x2B)      /* Antenna dwell */
  33 #define  B43_PHY_ANTDWELL_AUTODIV1      0x0100  /* Automatic RX diversity start antenna */
  34 #define B43_PHY_ENCORE                  B43_PHY_OFDM(0x49)      /* "Encore" (RangeMax / BroadRange) */
  35 #define  B43_PHY_ENCORE_EN              0x0200  /* Encore enable */
  36 #define B43_PHY_LMS                     B43_PHY_OFDM(0x55)
  37 #define B43_PHY_OFDM61                  B43_PHY_OFDM(0x61)      /* FIXME rename */
  38 #define  B43_PHY_OFDM61_10              0x0010  /* FIXME rename */
  39 #define B43_PHY_IQBAL                   B43_PHY_OFDM(0x69)      /* I/Q balance */
  40 #define B43_PHY_OTABLECTL               B43_PHY_OFDM(0x72)      /* OFDM table control (see below) */
  41 #define  B43_PHY_OTABLEOFF              0x03FF  /* OFDM table offset (see below) */
  42 #define  B43_PHY_OTABLENR               0xFC00  /* OFDM table number (see below) */
  43 #define  B43_PHY_OTABLENR_SHIFT         10
  44 #define B43_PHY_OTABLEI                 B43_PHY_OFDM(0x73)      /* OFDM table data I */
  45 #define B43_PHY_OTABLEQ                 B43_PHY_OFDM(0x74)      /* OFDM table data Q */
  46 #define B43_PHY_HPWR_TSSICTL            B43_PHY_OFDM(0x78)      /* Hardware power TSSI control */
  47 #define B43_PHY_NRSSITHRES              B43_PHY_OFDM(0x8A)      /* NRSSI threshold */
  48 #define B43_PHY_ANTWRSETT               B43_PHY_OFDM(0x8C)      /* Antenna WR settle */
  49 #define  B43_PHY_ANTWRSETT_ARXDIV       0x2000  /* Automatic RX diversity enabled */
  50 #define B43_PHY_CLIPPWRDOWNT            B43_PHY_OFDM(0x93)      /* Clip powerdown threshold */
  51 #define B43_PHY_OFDM9B                  B43_PHY_OFDM(0x9B)      /* FIXME rename */
  52 #define B43_PHY_N1P1GAIN                B43_PHY_OFDM(0xA0)
  53 #define B43_PHY_P1P2GAIN                B43_PHY_OFDM(0xA1)
  54 #define B43_PHY_N1N2GAIN                B43_PHY_OFDM(0xA2)
  55 #define B43_PHY_CLIPTHRES               B43_PHY_OFDM(0xA3)
  56 #define B43_PHY_CLIPN1P2THRES           B43_PHY_OFDM(0xA4)
  57 #define B43_PHY_DIVSRCHIDX              B43_PHY_OFDM(0xA8)      /* Divider search gain/index */
  58 #define B43_PHY_CLIPP2THRES             B43_PHY_OFDM(0xA9)
  59 #define B43_PHY_CLIPP3THRES             B43_PHY_OFDM(0xAA)
  60 #define B43_PHY_DIVP1P2GAIN             B43_PHY_OFDM(0xAB)
  61 #define B43_PHY_DIVSRCHGAINBACK         B43_PHY_OFDM(0xAD)      /* Divider search gain back */
  62 #define B43_PHY_DIVSRCHGAINCHNG         B43_PHY_OFDM(0xAE)      /* Divider search gain change */
  63 #define B43_PHY_CRSTHRES1_R1            B43_PHY_OFDM(0xC0)      /* CRS Threshold 1 (rev 1 only) */
  64 #define B43_PHY_CRSTHRES2_R1            B43_PHY_OFDM(0xC1)      /* CRS Threshold 2 (rev 1 only) */
  65 #define B43_PHY_TSSIP_LTBASE            B43_PHY_OFDM(0x380)     /* TSSI power lookup table base */
  66 #define B43_PHY_DC_LTBASE               B43_PHY_OFDM(0x3A0)     /* DC lookup table base */
  67 #define B43_PHY_GAIN_LTBASE             B43_PHY_OFDM(0x3C0)     /* Gain lookup table base */
  68
  69 /* CCK (B) PHY Registers */
  70 #define B43_PHY_VERSION_CCK             B43_PHY_BASE(0x00)      /* Versioning register for B-PHY */
  71 #define B43_PHY_CCKBBANDCFG             B43_PHY_BASE(0x01)      /* Contains antenna 0/1 control bit */
  72 #define B43_PHY_PGACTL                  B43_PHY_BASE(0x15)      /* PGA control */
  73 #define  B43_PHY_PGACTL_LPF             0x1000  /* Low pass filter (?) */
  74 #define  B43_PHY_PGACTL_LOWBANDW        0x0040  /* Low bandwidth flag */
  75 #define  B43_PHY_PGACTL_UNKNOWN         0xEFA0
  76 #define B43_PHY_FBCTL1                  B43_PHY_BASE(0x18)      /* Frequency bandwidth control 1 */
  77 #define B43_PHY_ITSSI                   B43_PHY_BASE(0x29)      /* Idle TSSI */
  78 #define B43_PHY_LO_LEAKAGE              B43_PHY_BASE(0x2D)      /* Measured LO leakage */
  79 #define B43_PHY_ENERGY                  B43_PHY_BASE(0x33)      /* Energy */
  80 #define B43_PHY_SYNCCTL                 B43_PHY_BASE(0x35)
  81 #define B43_PHY_FBCTL2                  B43_PHY_BASE(0x38)      /* Frequency bandwidth control 2 */
  82 #define B43_PHY_DACCTL                  B43_PHY_BASE(0x60)      /* DAC control */
  83 #define B43_PHY_RCCALOVER               B43_PHY_BASE(0x78)      /* RC calibration override */
  84
  85 /* Extended G-PHY Registers */
  86 #define B43_PHY_CLASSCTL                B43_PHY_EXTG(0x02)      /* Classify control */
  87 #define B43_PHY_GTABCTL                 B43_PHY_EXTG(0x03)      /* G-PHY table control (see below) */
  88 #define  B43_PHY_GTABOFF                0x03FF  /* G-PHY table offset (see below) */
  89 #define  B43_PHY_GTABNR                 0xFC00  /* G-PHY table number (see below) */
  90 #define  B43_PHY_GTABNR_SHIFT           10
  91 #define B43_PHY_GTABDATA                B43_PHY_EXTG(0x04)      /* G-PHY table data */
  92 #define B43_PHY_LO_MASK                 B43_PHY_EXTG(0x0F)      /* Local Oscillator control mask */
  93 #define B43_PHY_LO_CTL                  B43_PHY_EXTG(0x10)      /* Local Oscillator control */
  94 #define B43_PHY_RFOVER                  B43_PHY_EXTG(0x11)      /* RF override */
  95 #define B43_PHY_RFOVERVAL               B43_PHY_EXTG(0x12)      /* RF override value */
  96 #define  B43_PHY_RFOVERVAL_EXTLNA       0x8000
  97 #define  B43_PHY_RFOVERVAL_LNA          0x7000
  98 #define  B43_PHY_RFOVERVAL_LNA_SHIFT    12
  99 #define  B43_PHY_RFOVERVAL_PGA          0x0F00
 100 #define  B43_PHY_RFOVERVAL_PGA_SHIFT    8
 101 #define  B43_PHY_RFOVERVAL_UNK          0x0010  /* Unknown, always set. */
 102 #define  B43_PHY_RFOVERVAL_TRSWRX       0x00E0
 103 #define  B43_PHY_RFOVERVAL_BW           0x0003  /* Bandwidth flags */
 104 #define   B43_PHY_RFOVERVAL_BW_LPF      0x0001  /* Low Pass Filter */
 105 #define   B43_PHY_RFOVERVAL_BW_LBW      0x0002  /* Low Bandwidth (when set), high when unset */
 106 #define B43_PHY_ANALOGOVER              B43_PHY_EXTG(0x14)      /* Analog override */
 107 #define B43_PHY_ANALOGOVERVAL           B43_PHY_EXTG(0x15)      /* Analog override value */
 108
 109 /*** OFDM table numbers ***/
 110 #define B43_OFDMTAB(number, offset)     (((number) << B43_PHY_OTABLENR_SHIFT) | (offset))
 111 #define B43_OFDMTAB_AGC1                B43_OFDMTAB(0x00, 0)
 112 #define B43_OFDMTAB_GAIN0               B43_OFDMTAB(0x00, 0)
 113 #define B43_OFDMTAB_GAINX               B43_OFDMTAB(0x01, 0)    //TODO rename
 114 #define B43_OFDMTAB_GAIN1               B43_OFDMTAB(0x01, 4)
 115 #define B43_OFDMTAB_AGC3                B43_OFDMTAB(0x02, 0)
 116 #define B43_OFDMTAB_GAIN2               B43_OFDMTAB(0x02, 3)
 117 #define B43_OFDMTAB_LNAHPFGAIN1         B43_OFDMTAB(0x03, 0)
 118 #define B43_OFDMTAB_WRSSI               B43_OFDMTAB(0x04, 0)
 119 #define B43_OFDMTAB_LNAHPFGAIN2         B43_OFDMTAB(0x04, 0)
 120 #define B43_OFDMTAB_NOISESCALE          B43_OFDMTAB(0x05, 0)
 121 #define B43_OFDMTAB_AGC2                B43_OFDMTAB(0x06, 0)
 122 #define B43_OFDMTAB_ROTOR               B43_OFDMTAB(0x08, 0)
 123 #define B43_OFDMTAB_ADVRETARD           B43_OFDMTAB(0x09, 0)
 124 #define B43_OFDMTAB_DAC                 B43_OFDMTAB(0x0C, 0)
 125 #define B43_OFDMTAB_DC                  B43_OFDMTAB(0x0E, 7)
 126 #define B43_OFDMTAB_PWRDYN2             B43_OFDMTAB(0x0E, 12)
 127 #define B43_OFDMTAB_LNAGAIN             B43_OFDMTAB(0x0E, 13)
 128 //TODO
 129 #define B43_OFDMTAB_LPFGAIN             B43_OFDMTAB(0x0F, 12)
 130 #define B43_OFDMTAB_RSSI                B43_OFDMTAB(0x10, 0)
 131 //TODO
 132 #define B43_OFDMTAB_AGC1_R1             B43_OFDMTAB(0x13, 0)
 133 #define B43_OFDMTAB_GAINX_R1            B43_OFDMTAB(0x14, 0)    //TODO rename
 134 #define B43_OFDMTAB_MINSIGSQ            B43_OFDMTAB(0x14, 1)
 135 #define B43_OFDMTAB_AGC3_R1             B43_OFDMTAB(0x15, 0)
 136 #define B43_OFDMTAB_WRSSI_R1            B43_OFDMTAB(0x15, 4)
 137 #define B43_OFDMTAB_TSSI                B43_OFDMTAB(0x15, 0)
 138 #define B43_OFDMTAB_DACRFPABB           B43_OFDMTAB(0x16, 0)
 139 #define B43_OFDMTAB_DACOFF              B43_OFDMTAB(0x17, 0)
 140 #define B43_OFDMTAB_DCBIAS              B43_OFDMTAB(0x18, 0)
 141
 142 u16 b43_ofdmtab_read16(struct b43_wldev *dev, u16 table, u16 offset);
 143 void b43_ofdmtab_write16(struct b43_wldev *dev, u16 table,
 144                          u16 offset, u16 value);
 145 u32 b43_ofdmtab_read32(struct b43_wldev *dev, u16 table, u16 offset);
 146 void b43_ofdmtab_write32(struct b43_wldev *dev, u16 table,
 147                          u16 offset, u32 value);
 148
 149 /*** G-PHY table numbers */
 150 #define B43_GTAB(number, offset)        (((number) << B43_PHY_GTABNR_SHIFT) | (offset))
 151 #define B43_GTAB_NRSSI                  B43_GTAB(0x00, 0)
 152 #define B43_GTAB_TRFEMW                 B43_GTAB(0x0C, 0x120)
 153 #define B43_GTAB_ORIGTR                 B43_GTAB(0x2E, 0x298)
 154
 155 u16 b43_gtab_read(struct b43_wldev *dev, u16 table, u16 offset);        //TODO implement
 156 void b43_gtab_write(struct b43_wldev *dev, u16 table, u16 offset, u16 value);   //TODO implement
 157
 158 #define B43_DEFAULT_CHANNEL_A   36
 159 #define B43_DEFAULT_CHANNEL_BG  6
 160
 161 enum {
 162         B43_ANTENNA0,           /* Antenna 0 */
 163         B43_ANTENNA1,           /* Antenna 0 */
 164         B43_ANTENNA_AUTO1,      /* Automatic, starting with antenna 1 */
 165         B43_ANTENNA_AUTO0,      /* Automatic, starting with antenna 0 */
 166
 167         B43_ANTENNA_AUTO = B43_ANTENNA_AUTO0,
 168         B43_ANTENNA_DEFAULT = B43_ANTENNA_AUTO,
 169 };
 170
 171 enum {
 172         B43_INTERFMODE_NONE,
 173         B43_INTERFMODE_NONWLAN,
 174         B43_INTERFMODE_MANUALWLAN,
 175         B43_INTERFMODE_AUTOWLAN,
 176 };
 177
 178 /* Masks for the different PHY versioning registers. */
 179 #define B43_PHYVER_ANALOG               0xF000
 180 #define B43_PHYVER_ANALOG_SHIFT         12
 181 #define B43_PHYVER_TYPE                 0x0F00
 182 #define B43_PHYVER_TYPE_SHIFT           8
 183 #define B43_PHYVER_VERSION              0x00FF
 184
 185 void b43_raw_phy_lock(struct b43_wldev *dev);
 186 #define b43_phy_lock(dev, flags) \
 187         do {                                    \
 188                 local_irq_save(flags);          \
 189                 b43_raw_phy_lock(dev);  \
 190         } while (0)
 191 void b43_raw_phy_unlock(struct b43_wldev *dev);
 192 #define b43_phy_unlock(dev, flags) \
 193         do {                                    \
 194                 b43_raw_phy_unlock(dev);        \
 195                 local_irq_restore(flags);       \
 196         } while (0)
 197
 198 u16 b43_phy_read(struct b43_wldev *dev, u16 offset);
 199 void b43_phy_write(struct b43_wldev *dev, u16 offset, u16 val);
 200
 201 int b43_phy_init_tssi2dbm_table(struct b43_wldev *dev);
 202
 203 void b43_phy_early_init(struct b43_wldev *dev);
 204 int b43_phy_init(struct b43_wldev *dev);
 205
 206 void b43_set_rx_antenna(struct b43_wldev *dev, int antenna);
 207
 208 void b43_phy_xmitpower(struct b43_wldev *dev);
 209 void b43_gphy_dc_lt_init(struct b43_wldev *dev);
 210
 211 /* Returns the boolean whether the board has HardwarePowerControl */
 212 bool b43_has_hardware_pctl(struct b43_phy *phy);
 213 /* Returns the boolean whether "TX Magnification" is enabled. */
 214 #define has_tx_magnification(phy) \
 215         (((phy)->rev >= 2) &&                   \
 216          ((phy)->radio_ver == 0x2050) &&        \
 217          ((phy)->radio_rev == 8))
 218 /* Card uses the loopback gain stuff */
 219 #define has_loopback_gain(phy) \
 220         (((phy)->rev > 1) || ((phy)->gmode))
 221
 222 /* Radio Attenuation (RF Attenuation) */
 223 struct b43_rfatt {
 224         u8 att;                 /* Attenuation value */
 225         bool with_padmix;       /* Flag, PAD Mixer enabled. */
 226 };
 227 struct b43_rfatt_list {
 228         /* Attenuation values list */
 229         const struct b43_rfatt *list;
 230         u8 len;
 231         /* Minimum/Maximum attenuation values */
 232         u8 min_val;
 233         u8 max_val;
 234 };
 235
 236 /* Baseband Attenuation */
 237 struct b43_bbatt {
 238         u8 att;                 /* Attenuation value */
 239 };
 240 struct b43_bbatt_list {
 241         /* Attenuation values list */
 242         const struct b43_bbatt *list;
 243         u8 len;
 244         /* Minimum/Maximum attenuation values */
 245         u8 min_val;
 246         u8 max_val;
 247 };
 248
 249 /* tx_control bits. */
 250 #define B43_TXCTL_PA3DB         0x40    /* PA Gain 3dB */
 251 #define B43_TXCTL_PA2DB         0x20    /* PA Gain 2dB */
 252 #define B43_TXCTL_TXMIX         0x10    /* TX Mixer Gain */
 253
 254 /* Write BasebandAttenuation value to the device. */
 255 void b43_phy_set_baseband_attenuation(struct b43_wldev *dev,
 256                                       u16 baseband_attenuation);
 257
 258 extern const u8 b43_radio_channel_codes_bg[];
 259
 260 void b43_radio_lock(struct b43_wldev *dev);
 261 void b43_radio_unlock(struct b43_wldev *dev);
 262
 263 u16 b43_radio_read16(struct b43_wldev *dev, u16 offset);
 264 void b43_radio_write16(struct b43_wldev *dev, u16 offset, u16 val);
 265
 266 u16 b43_radio_init2050(struct b43_wldev *dev);
 267 void b43_radio_init2060(struct b43_wldev *dev);
 268
 269 void b43_radio_turn_on(struct b43_wldev *dev);
 270 void b43_radio_turn_off(struct b43_wldev *dev, bool force);
 271
 272 int b43_radio_selectchannel(struct b43_wldev *dev, u8 channel,
 273                             int synthetic_pu_workaround);
 274
 275 u8 b43_radio_aci_detect(struct b43_wldev *dev, u8 channel);
 276 u8 b43_radio_aci_scan(struct b43_wldev *dev);
 277
 278 int b43_radio_set_interference_mitigation(struct b43_wldev *dev, int mode);
 279
 280 void b43_calc_nrssi_slope(struct b43_wldev *dev);
 281 void b43_calc_nrssi_threshold(struct b43_wldev *dev);
 282 s16 b43_nrssi_hw_read(struct b43_wldev *dev, u16 offset);
 283 void b43_nrssi_hw_write(struct b43_wldev *dev, u16 offset, s16 val);
 284 void b43_nrssi_hw_update(struct b43_wldev *dev, u16 val);
 285 void b43_nrssi_mem_update(struct b43_wldev *dev);
 286
 287 void b43_radio_set_tx_iq(struct b43_wldev *dev);
 288 u16 b43_radio_calibrationvalue(struct b43_wldev *dev);
 289
 290 void b43_put_attenuation_into_ranges(struct b43_wldev *dev,
 291                                      int *_bbatt, int *_rfatt);
 292
 293 void b43_set_txpower_g(struct b43_wldev *dev,
 294                        const struct b43_bbatt *bbatt,
 295                        const struct b43_rfatt *rfatt, u8 tx_control);
 296
 297 #endif /* B43_PHY_H_ */