arch/mips/jmr3927/rbhma3100/setup.c

   1 /***********************************************************************
   2  *
   3  * Copyright 2001 MontaVista Software Inc.
   4  * Author: MontaVista Software, Inc.
   5  *              ahennessy@mvista.com
   6  *
   7  * Based on arch/mips/ddb5xxx/ddb5477/setup.c
   8  *
   9  *     Setup file for JMR3927.
  10  *
  11  * Copyright (C) 2000-2001 Toshiba Corporation
  12  *
  13  *  This program is free software; you can redistribute  it and/or modify it
  14  *  under  the terms of  the GNU General  Public License as published by the
  15  *  Free Software Foundation;  either version 2 of the  License, or (at your
  16  *  option) any later version.
  17  *
  18  *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
  19  *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
  20  *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
  21  *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
  22  *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  23  *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
  24  *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
  25  *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
  26  *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  27  *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  28  *
  29  *  You should have received a copy of the  GNU General Public License along
  30  *  with this program; if not, write  to the Free Software Foundation, Inc.,
  31  *  675 Mass Ave, Cambridge, MA 02139, USA.
  32  *
  33  ***********************************************************************
  34  */
  35
  36 #include <linux/init.h>
  37 #include <linux/kernel.h>
  38 #include <linux/kdev_t.h>
  39 #include <linux/types.h>
  40 #include <linux/sched.h>
  41 #include <linux/pci.h>
  42 #include <linux/ide.h>
  43 #include <linux/irq.h>
  44 #include <linux/ioport.h>
  45 #include <linux/param.h>        /* for HZ */
  46 #include <linux/delay.h>
  47 #include <linux/pm.h>
  48 #include <linux/platform_device.h>
  49 #ifdef CONFIG_SERIAL_TXX9
  50 #include <linux/tty.h>
  51 #include <linux/serial.h>
  52 #include <linux/serial_core.h>
  53 #endif
  54
  55 #include <asm/addrspace.h>
  56 #include <asm/time.h>
  57 #include <asm/reboot.h>
  58 #include <asm/jmr3927/jmr3927.h>
  59 #include <asm/mipsregs.h>
  60
  61 extern void puts(const char *cp);
  62
  63 /* Tick Timer divider */
  64 #define JMR3927_TIMER_CCD       0       /* 1/2 */
  65 #define JMR3927_TIMER_CLK       (JMR3927_IMCLK / (2 << JMR3927_TIMER_CCD))
  66
  67 /* don't enable - see errata */
  68 static int jmr3927_ccfg_toeon;
  69
  70 static inline void do_reset(void)
  71 {
  72 #if 1   /* Resetting PCI bus */
  73         jmr3927_ioc_reg_out(0, JMR3927_IOC_RESET_ADDR);
  74         jmr3927_ioc_reg_out(JMR3927_IOC_RESET_PCI, JMR3927_IOC_RESET_ADDR);
  75         (void)jmr3927_ioc_reg_in(JMR3927_IOC_RESET_ADDR);       /* flush WB */
  76         mdelay(1);
  77         jmr3927_ioc_reg_out(0, JMR3927_IOC_RESET_ADDR);
  78 #endif
  79         jmr3927_ioc_reg_out(JMR3927_IOC_RESET_CPU, JMR3927_IOC_RESET_ADDR);
  80 }
  81
  82 static void jmr3927_machine_restart(char *command)
  83 {
  84         local_irq_disable();
  85         puts("Rebooting...");
  86         do_reset();
  87 }
  88
  89 static void jmr3927_machine_halt(void)
  90 {
  91         puts("JMR-TX3927 halted.\n");
  92         while (1);
  93 }
  94
  95 static void jmr3927_machine_power_off(void)
  96 {
  97         puts("JMR-TX3927 halted. Please turn off the power.\n");
  98         while (1);
  99 }
 100
 101 static cycle_t jmr3927_hpt_read(void)
 102 {
 103         /* We assume this function is called xtime_lock held. */
 104         return jiffies * (JMR3927_TIMER_CLK / HZ) + jmr3927_tmrptr->trr;
 105 }
 106
 107 static void jmr3927_timer_ack(void)
 108 {
 109         jmr3927_tmrptr->tisr = 0;       /* ack interrupt */
 110 }
 111
 112 static void __init jmr3927_time_init(void)
 113 {
 114         clocksource_mips.read = jmr3927_hpt_read;
 115         mips_timer_ack = jmr3927_timer_ack;
 116         mips_hpt_frequency = JMR3927_TIMER_CLK;
 117 }
 118
 119 void __init plat_timer_setup(struct irqaction *irq)
 120 {
 121         jmr3927_tmrptr->cpra = JMR3927_TIMER_CLK / HZ;
 122         jmr3927_tmrptr->itmr = TXx927_TMTITMR_TIIE | TXx927_TMTITMR_TZCE;
 123         jmr3927_tmrptr->ccdr = JMR3927_TIMER_CCD;
 124         jmr3927_tmrptr->tcr =
 125                 TXx927_TMTCR_TCE | TXx927_TMTCR_CCDE | TXx927_TMTCR_TMODE_ITVL;
 126
 127         setup_irq(JMR3927_IRQ_TICK, irq);
 128 }
 129
 130 #define DO_WRITE_THROUGH
 131 #define DO_ENABLE_CACHE
 132
 133 extern char * __init prom_getcmdline(void);
 134 static void jmr3927_board_init(void);
 135 extern struct resource pci_io_resource;
 136 extern struct resource pci_mem_resource;
 137
 138 void __init plat_mem_setup(void)
 139 {
 140         char *argptr;
 141
 142         set_io_port_base(JMR3927_PORT_BASE + JMR3927_PCIIO);
 143
 144         board_time_init = jmr3927_time_init;
 145
 146         _machine_restart = jmr3927_machine_restart;
 147         _machine_halt = jmr3927_machine_halt;
 148         pm_power_off = jmr3927_machine_power_off;
 149
 150         /*
 151          * IO/MEM resources.
 152          */
 153         ioport_resource.start = pci_io_resource.start;
 154         ioport_resource.end = pci_io_resource.end;
 155         iomem_resource.start = 0;
 156         iomem_resource.end = 0xffffffff;
 157
 158         /* Reboot on panic */
 159         panic_timeout = 180;
 160
 161         /* cache setup */
 162         {
 163                 unsigned int conf;
 164 #ifdef DO_ENABLE_CACHE
 165                 int mips_ic_disable = 0, mips_dc_disable = 0;
 166 #else
 167                 int mips_ic_disable = 1, mips_dc_disable = 1;
 168 #endif
 169 #ifdef DO_WRITE_THROUGH
 170                 int mips_config_cwfon = 0;
 171                 int mips_config_wbon = 0;
 172 #else
 173                 int mips_config_cwfon = 1;
 174                 int mips_config_wbon = 1;
 175 #endif
 176
 177                 conf = read_c0_conf();
 178                 conf &= ~(TX39_CONF_ICE | TX39_CONF_DCE | TX39_CONF_WBON | TX39_CONF_CWFON);
 179                 conf |= mips_ic_disable ? 0 : TX39_CONF_ICE;
 180                 conf |= mips_dc_disable ? 0 : TX39_CONF_DCE;
 181                 conf |= mips_config_wbon ? TX39_CONF_WBON : 0;
 182                 conf |= mips_config_cwfon ? TX39_CONF_CWFON : 0;
 183
 184                 write_c0_conf(conf);
 185                 write_c0_cache(0);
 186         }
 187
 188         /* initialize board */
 189         jmr3927_board_init();
 190
 191         argptr = prom_getcmdline();
 192
 193         if ((argptr = strstr(argptr, "toeon")) != NULL)
 194                 jmr3927_ccfg_toeon = 1;
 195         argptr = prom_getcmdline();
 196         if ((argptr = strstr(argptr, "ip=")) == NULL) {
 197                 argptr = prom_getcmdline();
 198                 strcat(argptr, " ip=bootp");
 199         }
 200
 201 #ifdef CONFIG_SERIAL_TXX9
 202         {
 203                 extern int early_serial_txx9_setup(struct uart_port *port);
 204                 int i;
 205                 struct uart_port req;
 206                 for(i = 0; i < 2; i++) {
 207                         memset(&req, 0, sizeof(req));
 208                         req.line = i;
 209                         req.iotype = UPIO_MEM;
 210                         req.membase = (unsigned char __iomem *)TX3927_SIO_REG(i);
 211                         req.mapbase = TX3927_SIO_REG(i);
 212                         req.irq = i == 0 ?
 213                                 JMR3927_IRQ_IRC_SIO0 : JMR3927_IRQ_IRC_SIO1;
 214                         if (i == 0)
 215                                 req.flags |= UPF_BUGGY_UART /*HAVE_CTS_LINE*/;
 216                         req.uartclk = JMR3927_IMCLK;
 217                         early_serial_txx9_setup(&req);
 218                 }
 219         }
 220 #ifdef CONFIG_SERIAL_TXX9_CONSOLE
 221         argptr = prom_getcmdline();
 222         if ((argptr = strstr(argptr, "console=")) == NULL) {
 223                 argptr = prom_getcmdline();
 224                 strcat(argptr, " console=ttyS1,115200");
 225         }
 226 #endif
 227 #endif
 228 }
 229
 230 static void tx3927_setup(void);
 231
 232 static void __init jmr3927_board_init(void)
 233 {
 234         tx3927_setup();
 235
 236         /* SIO0 DTR on */
 237         jmr3927_ioc_reg_out(0, JMR3927_IOC_DTR_ADDR);
 238
 239         jmr3927_led_set(0);
 240
 241         printk("JMR-TX3927 (Rev %d) --- IOC(Rev %d) DIPSW:%d,%d,%d,%d\n",
 242                jmr3927_ioc_reg_in(JMR3927_IOC_BREV_ADDR) & JMR3927_REV_MASK,
 243                jmr3927_ioc_reg_in(JMR3927_IOC_REV_ADDR) & JMR3927_REV_MASK,
 244                jmr3927_dipsw1(), jmr3927_dipsw2(),
 245                jmr3927_dipsw3(), jmr3927_dipsw4());
 246 }
 247
 248 static void __init tx3927_setup(void)
 249 {
 250         int i;
 251 #ifdef CONFIG_PCI
 252         unsigned long mips_pci_io_base = JMR3927_PCIIO;
 253         unsigned long mips_pci_io_size = JMR3927_PCIIO_SIZE;
 254         unsigned long mips_pci_mem_base = JMR3927_PCIMEM;
 255         unsigned long mips_pci_mem_size = JMR3927_PCIMEM_SIZE;
 256         /* for legacy I/O, PCI I/O PCI Bus address must be 0 */
 257         unsigned long mips_pci_io_pciaddr = 0;
 258 #endif
 259
 260         /* SDRAMC are configured by PROM */
 261
 262         /* ROMC */
 263         tx3927_romcptr->cr[1] = JMR3927_ROMCE1 | 0x00030048;
 264         tx3927_romcptr->cr[2] = JMR3927_ROMCE2 | 0x000064c8;
 265         tx3927_romcptr->cr[3] = JMR3927_ROMCE3 | 0x0003f698;
 266         tx3927_romcptr->cr[5] = JMR3927_ROMCE5 | 0x0000f218;
 267
 268         /* CCFG */
 269         /* enable Timeout BusError */
 270         if (jmr3927_ccfg_toeon)
 271                 tx3927_ccfgptr->ccfg |= TX3927_CCFG_TOE;
 272
 273         /* clear BusErrorOnWrite flag */
 274         tx3927_ccfgptr->ccfg &= ~TX3927_CCFG_BEOW;
 275         /* Disable PCI snoop */
 276         tx3927_ccfgptr->ccfg &= ~TX3927_CCFG_PSNP;
 277
 278 #ifdef DO_WRITE_THROUGH
 279         /* Enable PCI SNOOP - with write through only */
 280         tx3927_ccfgptr->ccfg |= TX3927_CCFG_PSNP;
 281 #endif
 282
 283         /* Pin selection */
 284         tx3927_ccfgptr->pcfg &= ~TX3927_PCFG_SELALL;
 285         tx3927_ccfgptr->pcfg |=
 286                 TX3927_PCFG_SELSIOC(0) | TX3927_PCFG_SELSIO_ALL |
 287                 (TX3927_PCFG_SELDMA_ALL & ~TX3927_PCFG_SELDMA(1));
 288
 289         printk("TX3927 -- CRIR:%08lx CCFG:%08lx PCFG:%08lx\n",
 290                tx3927_ccfgptr->crir,
 291                tx3927_ccfgptr->ccfg, tx3927_ccfgptr->pcfg);
 292
 293         /* IRC */
 294         /* disable interrupt control */
 295         tx3927_ircptr->cer = 0;
 296         /* mask all IRC interrupts */
 297         tx3927_ircptr->imr = 0;
 298         for (i = 0; i < TX3927_NUM_IR / 2; i++) {
 299                 tx3927_ircptr->ilr[i] = 0;
 300         }
 301         /* setup IRC interrupt mode (Low Active) */
 302         for (i = 0; i < TX3927_NUM_IR / 8; i++) {
 303                 tx3927_ircptr->cr[i] = 0;
 304         }
 305
 306         /* TMR */
 307         /* disable all timers */
 308         for (i = 0; i < TX3927_NR_TMR; i++) {
 309                 tx3927_tmrptr(i)->tcr = TXx927_TMTCR_CRE;
 310                 tx3927_tmrptr(i)->tisr = 0;
 311                 tx3927_tmrptr(i)->cpra = 0xffffffff;
 312                 tx3927_tmrptr(i)->itmr = 0;
 313                 tx3927_tmrptr(i)->ccdr = 0;
 314                 tx3927_tmrptr(i)->pgmr = 0;
 315         }
 316
 317         /* DMA */
 318         tx3927_dmaptr->mcr = 0;
 319         for (i = 0; i < ARRAY_SIZE(tx3927_dmaptr->ch); i++) {
 320                 /* reset channel */
 321                 tx3927_dmaptr->ch[i].ccr = TX3927_DMA_CCR_CHRST;
 322                 tx3927_dmaptr->ch[i].ccr = 0;
 323         }
 324         /* enable DMA */
 325 #ifdef __BIG_ENDIAN
 326         tx3927_dmaptr->mcr = TX3927_DMA_MCR_MSTEN;
 327 #else
 328         tx3927_dmaptr->mcr = TX3927_DMA_MCR_MSTEN | TX3927_DMA_MCR_LE;
 329 #endif
 330
 331 #ifdef CONFIG_PCI
 332         /* PCIC */
 333         printk("TX3927 PCIC -- DID:%04x VID:%04x RID:%02x Arbiter:",
 334                tx3927_pcicptr->did, tx3927_pcicptr->vid,
 335                tx3927_pcicptr->rid);
 336         if (!(tx3927_ccfgptr->ccfg & TX3927_CCFG_PCIXARB)) {
 337                 printk("External\n");
 338                 /* XXX */
 339         } else {
 340                 printk("Internal\n");
 341
 342                 /* Reset PCI Bus */
 343                 jmr3927_ioc_reg_out(0, JMR3927_IOC_RESET_ADDR);
 344                 udelay(100);
 345                 jmr3927_ioc_reg_out(JMR3927_IOC_RESET_PCI,
 346                                     JMR3927_IOC_RESET_ADDR);
 347                 udelay(100);
 348                 jmr3927_ioc_reg_out(0, JMR3927_IOC_RESET_ADDR);
 349
 350
 351                 /* Disable External PCI Config. Access */
 352                 tx3927_pcicptr->lbc = TX3927_PCIC_LBC_EPCAD;
 353 #ifdef __BIG_ENDIAN
 354                 tx3927_pcicptr->lbc |= TX3927_PCIC_LBC_IBSE |
 355                         TX3927_PCIC_LBC_TIBSE |
 356                         TX3927_PCIC_LBC_TMFBSE | TX3927_PCIC_LBC_MSDSE;
 357 #endif
 358                 /* LB->PCI mappings */
 359                 tx3927_pcicptr->iomas = ~(mips_pci_io_size - 1);
 360                 tx3927_pcicptr->ilbioma = mips_pci_io_base;
 361                 tx3927_pcicptr->ipbioma = mips_pci_io_pciaddr;
 362                 tx3927_pcicptr->mmas = ~(mips_pci_mem_size - 1);
 363                 tx3927_pcicptr->ilbmma = mips_pci_mem_base;
 364                 tx3927_pcicptr->ipbmma = mips_pci_mem_base;
 365                 /* PCI->LB mappings */
 366                 tx3927_pcicptr->iobas = 0xffffffff;
 367                 tx3927_pcicptr->ioba = 0;
 368                 tx3927_pcicptr->tlbioma = 0;
 369                 tx3927_pcicptr->mbas = ~(mips_pci_mem_size - 1);
 370                 tx3927_pcicptr->mba = 0;
 371                 tx3927_pcicptr->tlbmma = 0;
 372                 /* Enable Direct mapping Address Space Decoder */
 373                 tx3927_pcicptr->lbc |= TX3927_PCIC_LBC_ILMDE | TX3927_PCIC_LBC_ILIDE;
 374
 375                 /* Clear All Local Bus Status */
 376                 tx3927_pcicptr->lbstat = TX3927_PCIC_LBIM_ALL;
 377                 /* Enable All Local Bus Interrupts */
 378                 tx3927_pcicptr->lbim = TX3927_PCIC_LBIM_ALL;
 379                 /* Clear All PCI Status Error */
 380                 tx3927_pcicptr->pcistat = TX3927_PCIC_PCISTATIM_ALL;
 381                 /* Enable All PCI Status Error Interrupts */
 382                 tx3927_pcicptr->pcistatim = TX3927_PCIC_PCISTATIM_ALL;
 383
 384                 /* PCIC Int => IRC IRQ10 */
 385                 tx3927_pcicptr->il = TX3927_IR_PCI;
 386                 /* Target Control (per errata) */
 387                 tx3927_pcicptr->tc = TX3927_PCIC_TC_OF8E | TX3927_PCIC_TC_IF8E;
 388
 389                 /* Enable Bus Arbiter */
 390                 tx3927_pcicptr->pbapmc = TX3927_PCIC_PBAPMC_PBAEN;
 391
 392                 tx3927_pcicptr->pcicmd = PCI_COMMAND_MASTER |
 393                         PCI_COMMAND_MEMORY |
 394                         PCI_COMMAND_IO |
 395                         PCI_COMMAND_PARITY | PCI_COMMAND_SERR;
 396         }
 397 #endif /* CONFIG_PCI */
 398
 399         /* PIO */
 400         /* PIO[15:12] connected to LEDs */
 401         tx3927_pioptr->dir = 0x0000f000;
 402         tx3927_pioptr->maskcpu = 0;
 403         tx3927_pioptr->maskext = 0;
 404         {
 405                 unsigned int conf;
 406
 407         conf = read_c0_conf();
 408                if (!(conf & TX39_CONF_ICE))
 409                        printk("TX3927 I-Cache disabled.\n");
 410                if (!(conf & TX39_CONF_DCE))
 411                        printk("TX3927 D-Cache disabled.\n");
 412                else if (!(conf & TX39_CONF_WBON))
 413                        printk("TX3927 D-Cache WriteThrough.\n");
 414                else if (!(conf & TX39_CONF_CWFON))
 415                        printk("TX3927 D-Cache WriteBack.\n");
 416                else
 417                        printk("TX3927 D-Cache WriteBack (CWF) .\n");
 418         }
 419 }
 420
 421 /* This trick makes rtc-ds1742 driver usable as is. */
 422 unsigned long __swizzle_addr_b(unsigned long port)
 423 {
 424         if ((port & 0xffff0000) != JMR3927_IOC_NVRAMB_ADDR)
 425                 return port;
 426         port = (port & 0xffff0000) | (port & 0x7fff << 1);
 427 #ifdef __BIG_ENDIAN
 428         return port;
 429 #else
 430         return port | 1;
 431 #endif
 432 }
 433 EXPORT_SYMBOL(__swizzle_addr_b);
 434
 435 static int __init jmr3927_rtc_init(void)
 436 {
 437         struct resource res = {
 438                 .start  = JMR3927_IOC_NVRAMB_ADDR - IO_BASE,
 439                 .end    = JMR3927_IOC_NVRAMB_ADDR - IO_BASE + 0x800 - 1,
 440                 .flags  = IORESOURCE_MEM,
 441         };
 442         struct platform_device *dev;
 443         dev = platform_device_register_simple("ds1742", -1, &res, 1);
 444         return IS_ERR(dev) ? PTR_ERR(dev) : 0;
 445 }
 446 device_initcall(jmr3927_rtc_init);