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e1000e: Fix typo ! &
[pv_ops_mirror.git] / sound / pci / cs4281.c
blob9a55f4a9739b671b59950ac383e15e57dd0916ca
1 /*
2 * Driver for Cirrus Logic CS4281 based PCI soundcard
3 * Copyright (c) by Jaroslav Kysela <perex@perex.cz>,
4 *
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 *
20 */
21
22 #include <sound/driver.h>
23 #include <asm/io.h>
24 #include <linux/delay.h>
25 #include <linux/interrupt.h>
26 #include <linux/init.h>
27 #include <linux/pci.h>
28 #include <linux/slab.h>
29 #include <linux/gameport.h>
30 #include <linux/moduleparam.h>
31 #include <sound/core.h>
32 #include <sound/control.h>
33 #include <sound/pcm.h>
34 #include <sound/rawmidi.h>
35 #include <sound/ac97_codec.h>
36 #include <sound/tlv.h>
37 #include <sound/opl3.h>
38 #include <sound/initval.h>
39
40
41 MODULE_AUTHOR("Jaroslav Kysela <perex@perex.cz>");
42 MODULE_DESCRIPTION("Cirrus Logic CS4281");
43 MODULE_LICENSE("GPL");
44 MODULE_SUPPORTED_DEVICE("{{Cirrus Logic,CS4281}}");
45
46 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; /* Index 0-MAX */
47 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; /* ID for this card */
48 static int enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP; /* Enable switches */
49 static int dual_codec[SNDRV_CARDS]; /* dual codec */
50
51 module_param_array(index, int, NULL, 0444);
52 MODULE_PARM_DESC(index, "Index value for CS4281 soundcard.");
53 module_param_array(id, charp, NULL, 0444);
54 MODULE_PARM_DESC(id, "ID string for CS4281 soundcard.");
55 module_param_array(enable, bool, NULL, 0444);
56 MODULE_PARM_DESC(enable, "Enable CS4281 soundcard.");
57 module_param_array(dual_codec, bool, NULL, 0444);
58 MODULE_PARM_DESC(dual_codec, "Secondary Codec ID (0 = disabled).");
59
60 /*
61 * Direct registers
62 */
63
64 #define CS4281_BA0_SIZE 0x1000
65 #define CS4281_BA1_SIZE 0x10000
66
67 /*
68 * BA0 registers
69 */
70 #define BA0_HISR 0x0000 /* Host Interrupt Status Register */
71 #define BA0_HISR_INTENA (1<<31) /* Internal Interrupt Enable Bit */
72 #define BA0_HISR_MIDI (1<<22) /* MIDI port interrupt */
73 #define BA0_HISR_FIFOI (1<<20) /* FIFO polled interrupt */
74 #define BA0_HISR_DMAI (1<<18) /* DMA interrupt (half or end) */
75 #define BA0_HISR_FIFO(c) (1<<(12+(c))) /* FIFO channel interrupt */
76 #define BA0_HISR_DMA(c) (1<<(8+(c))) /* DMA channel interrupt */
77 #define BA0_HISR_GPPI (1<<5) /* General Purpose Input (Primary chip) */
78 #define BA0_HISR_GPSI (1<<4) /* General Purpose Input (Secondary chip) */
79 #define BA0_HISR_GP3I (1<<3) /* GPIO3 pin Interrupt */
80 #define BA0_HISR_GP1I (1<<2) /* GPIO1 pin Interrupt */
81 #define BA0_HISR_VUPI (1<<1) /* VOLUP pin Interrupt */
82 #define BA0_HISR_VDNI (1<<0) /* VOLDN pin Interrupt */
83
84 #define BA0_HICR 0x0008 /* Host Interrupt Control Register */
85 #define BA0_HICR_CHGM (1<<1) /* INTENA Change Mask */
86 #define BA0_HICR_IEV (1<<0) /* INTENA Value */
87 #define BA0_HICR_EOI (3<<0) /* End of Interrupt command */
88
89 #define BA0_HIMR 0x000c /* Host Interrupt Mask Register */
90 /* Use same contants as for BA0_HISR */
91
92 #define BA0_IIER 0x0010 /* ISA Interrupt Enable Register */
93
94 #define BA0_HDSR0 0x00f0 /* Host DMA Engine 0 Status Register */
95 #define BA0_HDSR1 0x00f4 /* Host DMA Engine 1 Status Register */
96 #define BA0_HDSR2 0x00f8 /* Host DMA Engine 2 Status Register */
97 #define BA0_HDSR3 0x00fc /* Host DMA Engine 3 Status Register */
98
99 #define BA0_HDSR_CH1P (1<<25) /* Channel 1 Pending */
100 #define BA0_HDSR_CH2P (1<<24) /* Channel 2 Pending */
101 #define BA0_HDSR_DHTC (1<<17) /* DMA Half Terminal Count */
102 #define BA0_HDSR_DTC (1<<16) /* DMA Terminal Count */
103 #define BA0_HDSR_DRUN (1<<15) /* DMA Running */
104 #define BA0_HDSR_RQ (1<<7) /* Pending Request */
105
106 #define BA0_DCA0 0x0110 /* Host DMA Engine 0 Current Address */
107 #define BA0_DCC0 0x0114 /* Host DMA Engine 0 Current Count */
108 #define BA0_DBA0 0x0118 /* Host DMA Engine 0 Base Address */
109 #define BA0_DBC0 0x011c /* Host DMA Engine 0 Base Count */
110 #define BA0_DCA1 0x0120 /* Host DMA Engine 1 Current Address */
111 #define BA0_DCC1 0x0124 /* Host DMA Engine 1 Current Count */
112 #define BA0_DBA1 0x0128 /* Host DMA Engine 1 Base Address */
113 #define BA0_DBC1 0x012c /* Host DMA Engine 1 Base Count */
114 #define BA0_DCA2 0x0130 /* Host DMA Engine 2 Current Address */
115 #define BA0_DCC2 0x0134 /* Host DMA Engine 2 Current Count */
116 #define BA0_DBA2 0x0138 /* Host DMA Engine 2 Base Address */
117 #define BA0_DBC2 0x013c /* Host DMA Engine 2 Base Count */
118 #define BA0_DCA3 0x0140 /* Host DMA Engine 3 Current Address */
119 #define BA0_DCC3 0x0144 /* Host DMA Engine 3 Current Count */
120 #define BA0_DBA3 0x0148 /* Host DMA Engine 3 Base Address */
121 #define BA0_DBC3 0x014c /* Host DMA Engine 3 Base Count */
122 #define BA0_DMR0 0x0150 /* Host DMA Engine 0 Mode */
123 #define BA0_DCR0 0x0154 /* Host DMA Engine 0 Command */
124 #define BA0_DMR1 0x0158 /* Host DMA Engine 1 Mode */
125 #define BA0_DCR1 0x015c /* Host DMA Engine 1 Command */
126 #define BA0_DMR2 0x0160 /* Host DMA Engine 2 Mode */
127 #define BA0_DCR2 0x0164 /* Host DMA Engine 2 Command */
128 #define BA0_DMR3 0x0168 /* Host DMA Engine 3 Mode */
129 #define BA0_DCR3 0x016c /* Host DMA Engine 3 Command */
130
131 #define BA0_DMR_DMA (1<<29) /* Enable DMA mode */
132 #define BA0_DMR_POLL (1<<28) /* Enable poll mode */
133 #define BA0_DMR_TBC (1<<25) /* Transfer By Channel */
134 #define BA0_DMR_CBC (1<<24) /* Count By Channel (0 = frame resolution) */
135 #define BA0_DMR_SWAPC (1<<22) /* Swap Left/Right Channels */
136 #define BA0_DMR_SIZE20 (1<<20) /* Sample is 20-bit */
137 #define BA0_DMR_USIGN (1<<19) /* Unsigned */
138 #define BA0_DMR_BEND (1<<18) /* Big Endian */
139 #define BA0_DMR_MONO (1<<17) /* Mono */
140 #define BA0_DMR_SIZE8 (1<<16) /* Sample is 8-bit */
141 #define BA0_DMR_TYPE_DEMAND (0<<6)
142 #define BA0_DMR_TYPE_SINGLE (1<<6)
143 #define BA0_DMR_TYPE_BLOCK (2<<6)
144 #define BA0_DMR_TYPE_CASCADE (3<<6) /* Not supported */
145 #define BA0_DMR_DEC (1<<5) /* Access Increment (0) or Decrement (1) */
146 #define BA0_DMR_AUTO (1<<4) /* Auto-Initialize */
147 #define BA0_DMR_TR_VERIFY (0<<2) /* Verify Transfer */
148 #define BA0_DMR_TR_WRITE (1<<2) /* Write Transfer */
149 #define BA0_DMR_TR_READ (2<<2) /* Read Transfer */
150
151 #define BA0_DCR_HTCIE (1<<17) /* Half Terminal Count Interrupt */
152 #define BA0_DCR_TCIE (1<<16) /* Terminal Count Interrupt */
153 #define BA0_DCR_MSK (1<<0) /* DMA Mask bit */
154
155 #define BA0_FCR0 0x0180 /* FIFO Control 0 */
156 #define BA0_FCR1 0x0184 /* FIFO Control 1 */
157 #define BA0_FCR2 0x0188 /* FIFO Control 2 */
158 #define BA0_FCR3 0x018c /* FIFO Control 3 */
159
160 #define BA0_FCR_FEN (1<<31) /* FIFO Enable bit */
161 #define BA0_FCR_DACZ (1<<30) /* DAC Zero */
162 #define BA0_FCR_PSH (1<<29) /* Previous Sample Hold */
163 #define BA0_FCR_RS(x) (((x)&0x1f)<<24) /* Right Slot Mapping */
164 #define BA0_FCR_LS(x) (((x)&0x1f)<<16) /* Left Slot Mapping */
165 #define BA0_FCR_SZ(x) (((x)&0x7f)<<8) /* FIFO buffer size (in samples) */
166 #define BA0_FCR_OF(x) (((x)&0x7f)<<0) /* FIFO starting offset (in samples) */
167
168 #define BA0_FPDR0 0x0190 /* FIFO Polled Data 0 */
169 #define BA0_FPDR1 0x0194 /* FIFO Polled Data 1 */
170 #define BA0_FPDR2 0x0198 /* FIFO Polled Data 2 */
171 #define BA0_FPDR3 0x019c /* FIFO Polled Data 3 */
172
173 #define BA0_FCHS 0x020c /* FIFO Channel Status */
174 #define BA0_FCHS_RCO(x) (1<<(7+(((x)&3)<<3))) /* Right Channel Out */
175 #define BA0_FCHS_LCO(x) (1<<(6+(((x)&3)<<3))) /* Left Channel Out */
176 #define BA0_FCHS_MRP(x) (1<<(5+(((x)&3)<<3))) /* Move Read Pointer */
177 #define BA0_FCHS_FE(x) (1<<(4+(((x)&3)<<3))) /* FIFO Empty */
178 #define BA0_FCHS_FF(x) (1<<(3+(((x)&3)<<3))) /* FIFO Full */
179 #define BA0_FCHS_IOR(x) (1<<(2+(((x)&3)<<3))) /* Internal Overrun Flag */
180 #define BA0_FCHS_RCI(x) (1<<(1+(((x)&3)<<3))) /* Right Channel In */
181 #define BA0_FCHS_LCI(x) (1<<(0+(((x)&3)<<3))) /* Left Channel In */
182
183 #define BA0_FSIC0 0x0210 /* FIFO Status and Interrupt Control 0 */
184 #define BA0_FSIC1 0x0214 /* FIFO Status and Interrupt Control 1 */
185 #define BA0_FSIC2 0x0218 /* FIFO Status and Interrupt Control 2 */
186 #define BA0_FSIC3 0x021c /* FIFO Status and Interrupt Control 3 */
187
188 #define BA0_FSIC_FIC(x) (((x)&0x7f)<<24) /* FIFO Interrupt Count */
189 #define BA0_FSIC_FORIE (1<<23) /* FIFO OverRun Interrupt Enable */
190 #define BA0_FSIC_FURIE (1<<22) /* FIFO UnderRun Interrupt Enable */
191 #define BA0_FSIC_FSCIE (1<<16) /* FIFO Sample Count Interrupt Enable */
192 #define BA0_FSIC_FSC(x) (((x)&0x7f)<<8) /* FIFO Sample Count */
193 #define BA0_FSIC_FOR (1<<7) /* FIFO OverRun */
194 #define BA0_FSIC_FUR (1<<6) /* FIFO UnderRun */
195 #define BA0_FSIC_FSCR (1<<0) /* FIFO Sample Count Reached */
196
197 #define BA0_PMCS 0x0344 /* Power Management Control/Status */
198 #define BA0_CWPR 0x03e0 /* Configuration Write Protect */
199
200 #define BA0_EPPMC 0x03e4 /* Extended PCI Power Management Control */
201 #define BA0_EPPMC_FPDN (1<<14) /* Full Power DowN */
202
203 #define BA0_GPIOR 0x03e8 /* GPIO Pin Interface Register */
204
205 #define BA0_SPMC 0x03ec /* Serial Port Power Management Control (& ASDIN2 enable) */
206 #define BA0_SPMC_GIPPEN (1<<15) /* GP INT Primary PME# Enable */
207 #define BA0_SPMC_GISPEN (1<<14) /* GP INT Secondary PME# Enable */
208 #define BA0_SPMC_EESPD (1<<9) /* EEPROM Serial Port Disable */
209 #define BA0_SPMC_ASDI2E (1<<8) /* ASDIN2 Enable */
210 #define BA0_SPMC_ASDO (1<<7) /* Asynchronous ASDOUT Assertion */
211 #define BA0_SPMC_WUP2 (1<<3) /* Wakeup for Secondary Input */
212 #define BA0_SPMC_WUP1 (1<<2) /* Wakeup for Primary Input */
213 #define BA0_SPMC_ASYNC (1<<1) /* Asynchronous ASYNC Assertion */
214 #define BA0_SPMC_RSTN (1<<0) /* Reset Not! */
215
216 #define BA0_CFLR 0x03f0 /* Configuration Load Register (EEPROM or BIOS) */
217 #define BA0_CFLR_DEFAULT 0x00000001 /* CFLR must be in AC97 link mode */
218 #define BA0_IISR 0x03f4 /* ISA Interrupt Select */
219 #define BA0_TMS 0x03f8 /* Test Register */
220 #define BA0_SSVID 0x03fc /* Subsystem ID register */
221
222 #define BA0_CLKCR1 0x0400 /* Clock Control Register 1 */
223 #define BA0_CLKCR1_CLKON (1<<25) /* Read Only */
224 #define BA0_CLKCR1_DLLRDY (1<<24) /* DLL Ready */
225 #define BA0_CLKCR1_DLLOS (1<<6) /* DLL Output Select */
226 #define BA0_CLKCR1_SWCE (1<<5) /* Clock Enable */
227 #define BA0_CLKCR1_DLLP (1<<4) /* DLL PowerUp */
228 #define BA0_CLKCR1_DLLSS (((x)&3)<<3) /* DLL Source Select */
229
230 #define BA0_FRR 0x0410 /* Feature Reporting Register */
231 #define BA0_SLT12O 0x041c /* Slot 12 GPIO Output Register for AC-Link */
232
233 #define BA0_SERMC 0x0420 /* Serial Port Master Control */
234 #define BA0_SERMC_FCRN (1<<27) /* Force Codec Ready Not */
235 #define BA0_SERMC_ODSEN2 (1<<25) /* On-Demand Support Enable ASDIN2 */
236 #define BA0_SERMC_ODSEN1 (1<<24) /* On-Demand Support Enable ASDIN1 */
237 #define BA0_SERMC_SXLB (1<<21) /* ASDIN2 to ASDOUT Loopback */
238 #define BA0_SERMC_SLB (1<<20) /* ASDOUT to ASDIN2 Loopback */
239 #define BA0_SERMC_LOVF (1<<19) /* Loopback Output Valid Frame bit */
240 #define BA0_SERMC_TCID(x) (((x)&3)<<16) /* Target Secondary Codec ID */
241 #define BA0_SERMC_PXLB (5<<1) /* Primary Port External Loopback */
242 #define BA0_SERMC_PLB (4<<1) /* Primary Port Internal Loopback */
243 #define BA0_SERMC_PTC (7<<1) /* Port Timing Configuration */
244 #define BA0_SERMC_PTC_AC97 (1<<1) /* AC97 mode */
245 #define BA0_SERMC_MSPE (1<<0) /* Master Serial Port Enable */
246
247 #define BA0_SERC1 0x0428 /* Serial Port Configuration 1 */
248 #define BA0_SERC1_SO1F(x) (((x)&7)>>1) /* Primary Output Port Format */
249 #define BA0_SERC1_AC97 (1<<1)
250 #define BA0_SERC1_SO1EN (1<<0) /* Primary Output Port Enable */
251
252 #define BA0_SERC2 0x042c /* Serial Port Configuration 2 */
253 #define BA0_SERC2_SI1F(x) (((x)&7)>>1) /* Primary Input Port Format */
254 #define BA0_SERC2_AC97 (1<<1)
255 #define BA0_SERC2_SI1EN (1<<0) /* Primary Input Port Enable */
256
257 #define BA0_SLT12M 0x045c /* Slot 12 Monitor Register for Primary AC-Link */
258
259 #define BA0_ACCTL 0x0460 /* AC'97 Control */
260 #define BA0_ACCTL_TC (1<<6) /* Target Codec */
261 #define BA0_ACCTL_CRW (1<<4) /* 0=Write, 1=Read Command */
262 #define BA0_ACCTL_DCV (1<<3) /* Dynamic Command Valid */
263 #define BA0_ACCTL_VFRM (1<<2) /* Valid Frame */
264 #define BA0_ACCTL_ESYN (1<<1) /* Enable Sync */
265
266 #define BA0_ACSTS 0x0464 /* AC'97 Status */
267 #define BA0_ACSTS_VSTS (1<<1) /* Valid Status */
268 #define BA0_ACSTS_CRDY (1<<0) /* Codec Ready */
269
270 #define BA0_ACOSV 0x0468 /* AC'97 Output Slot Valid */
271 #define BA0_ACOSV_SLV(x) (1<<((x)-3))
272
273 #define BA0_ACCAD 0x046c /* AC'97 Command Address */
274 #define BA0_ACCDA 0x0470 /* AC'97 Command Data */
275
276 #define BA0_ACISV 0x0474 /* AC'97 Input Slot Valid */
277 #define BA0_ACISV_SLV(x) (1<<((x)-3))
278
279 #define BA0_ACSAD 0x0478 /* AC'97 Status Address */
280 #define BA0_ACSDA 0x047c /* AC'97 Status Data */
281 #define BA0_JSPT 0x0480 /* Joystick poll/trigger */
282 #define BA0_JSCTL 0x0484 /* Joystick control */
283 #define BA0_JSC1 0x0488 /* Joystick control */
284 #define BA0_JSC2 0x048c /* Joystick control */
285 #define BA0_JSIO 0x04a0
286
287 #define BA0_MIDCR 0x0490 /* MIDI Control */
288 #define BA0_MIDCR_MRST (1<<5) /* Reset MIDI Interface */
289 #define BA0_MIDCR_MLB (1<<4) /* MIDI Loop Back Enable */
290 #define BA0_MIDCR_TIE (1<<3) /* MIDI Transmuit Interrupt Enable */
291 #define BA0_MIDCR_RIE (1<<2) /* MIDI Receive Interrupt Enable */
292 #define BA0_MIDCR_RXE (1<<1) /* MIDI Receive Enable */
293 #define BA0_MIDCR_TXE (1<<0) /* MIDI Transmit Enable */
294
295 #define BA0_MIDCMD 0x0494 /* MIDI Command (wo) */
296
297 #define BA0_MIDSR 0x0494 /* MIDI Status (ro) */
298 #define BA0_MIDSR_RDA (1<<15) /* Sticky bit (RBE 1->0) */
299 #define BA0_MIDSR_TBE (1<<14) /* Sticky bit (TBF 0->1) */
300 #define BA0_MIDSR_RBE (1<<7) /* Receive Buffer Empty */
301 #define BA0_MIDSR_TBF (1<<6) /* Transmit Buffer Full */
302
303 #define BA0_MIDWP 0x0498 /* MIDI Write */
304 #define BA0_MIDRP 0x049c /* MIDI Read (ro) */
305
306 #define BA0_AODSD1 0x04a8 /* AC'97 On-Demand Slot Disable for primary link (ro) */
307 #define BA0_AODSD1_NDS(x) (1<<((x)-3))
308
309 #define BA0_AODSD2 0x04ac /* AC'97 On-Demand Slot Disable for secondary link (ro) */
310 #define BA0_AODSD2_NDS(x) (1<<((x)-3))
311
312 #define BA0_CFGI 0x04b0 /* Configure Interface (EEPROM interface) */
313 #define BA0_SLT12M2 0x04dc /* Slot 12 Monitor Register 2 for secondary AC-link */
314 #define BA0_ACSTS2 0x04e4 /* AC'97 Status Register 2 */
315 #define BA0_ACISV2 0x04f4 /* AC'97 Input Slot Valid Register 2 */
316 #define BA0_ACSAD2 0x04f8 /* AC'97 Status Address Register 2 */
317 #define BA0_ACSDA2 0x04fc /* AC'97 Status Data Register 2 */
318 #define BA0_FMSR 0x0730 /* FM Synthesis Status (ro) */
319 #define BA0_B0AP 0x0730 /* FM Bank 0 Address Port (wo) */
320 #define BA0_FMDP 0x0734 /* FM Data Port */
321 #define BA0_B1AP 0x0738 /* FM Bank 1 Address Port */
322 #define BA0_B1DP 0x073c /* FM Bank 1 Data Port */
323
324 #define BA0_SSPM 0x0740 /* Sound System Power Management */
325 #define BA0_SSPM_MIXEN (1<<6) /* Playback SRC + FM/Wavetable MIX */
326 #define BA0_SSPM_CSRCEN (1<<5) /* Capture Sample Rate Converter Enable */
327 #define BA0_SSPM_PSRCEN (1<<4) /* Playback Sample Rate Converter Enable */
328 #define BA0_SSPM_JSEN (1<<3) /* Joystick Enable */
329 #define BA0_SSPM_ACLEN (1<<2) /* Serial Port Engine and AC-Link Enable */
330 #define BA0_SSPM_FMEN (1<<1) /* FM Synthesis Block Enable */
331
332 #define BA0_DACSR 0x0744 /* DAC Sample Rate - Playback SRC */
333 #define BA0_ADCSR 0x0748 /* ADC Sample Rate - Capture SRC */
334
335 #define BA0_SSCR 0x074c /* Sound System Control Register */
336 #define BA0_SSCR_HVS1 (1<<23) /* Hardwave Volume Step (0=1,1=2) */
337 #define BA0_SSCR_MVCS (1<<19) /* Master Volume Codec Select */
338 #define BA0_SSCR_MVLD (1<<18) /* Master Volume Line Out Disable */
339 #define BA0_SSCR_MVAD (1<<17) /* Master Volume Alternate Out Disable */
340 #define BA0_SSCR_MVMD (1<<16) /* Master Volume Mono Out Disable */
341 #define BA0_SSCR_XLPSRC (1<<8) /* External SRC Loopback Mode */
342 #define BA0_SSCR_LPSRC (1<<7) /* SRC Loopback Mode */
343 #define BA0_SSCR_CDTX (1<<5) /* CD Transfer Data */
344 #define BA0_SSCR_HVC (1<<3) /* Harware Volume Control Enable */
345
346 #define BA0_FMLVC 0x0754 /* FM Synthesis Left Volume Control */
347 #define BA0_FMRVC 0x0758 /* FM Synthesis Right Volume Control */
348 #define BA0_SRCSA 0x075c /* SRC Slot Assignments */
349 #define BA0_PPLVC 0x0760 /* PCM Playback Left Volume Control */
350 #define BA0_PPRVC 0x0764 /* PCM Playback Right Volume Control */
351 #define BA0_PASR 0x0768 /* playback sample rate */
352 #define BA0_CASR 0x076C /* capture sample rate */
353
354 /* Source Slot Numbers - Playback */
355 #define SRCSLOT_LEFT_PCM_PLAYBACK 0
356 #define SRCSLOT_RIGHT_PCM_PLAYBACK 1
357 #define SRCSLOT_PHONE_LINE_1_DAC 2
358 #define SRCSLOT_CENTER_PCM_PLAYBACK 3
359 #define SRCSLOT_LEFT_SURROUND_PCM_PLAYBACK 4
360 #define SRCSLOT_RIGHT_SURROUND_PCM_PLAYBACK 5
361 #define SRCSLOT_LFE_PCM_PLAYBACK 6
362 #define SRCSLOT_PHONE_LINE_2_DAC 7
363 #define SRCSLOT_HEADSET_DAC 8
364 #define SRCSLOT_LEFT_WT 29 /* invalid for BA0_SRCSA */
365 #define SRCSLOT_RIGHT_WT 30 /* invalid for BA0_SRCSA */
366
367 /* Source Slot Numbers - Capture */
368 #define SRCSLOT_LEFT_PCM_RECORD 10
369 #define SRCSLOT_RIGHT_PCM_RECORD 11
370 #define SRCSLOT_PHONE_LINE_1_ADC 12
371 #define SRCSLOT_MIC_ADC 13
372 #define SRCSLOT_PHONE_LINE_2_ADC 17
373 #define SRCSLOT_HEADSET_ADC 18
374 #define SRCSLOT_SECONDARY_LEFT_PCM_RECORD 20
375 #define SRCSLOT_SECONDARY_RIGHT_PCM_RECORD 21
376 #define SRCSLOT_SECONDARY_PHONE_LINE_1_ADC 22
377 #define SRCSLOT_SECONDARY_MIC_ADC 23
378 #define SRCSLOT_SECONDARY_PHONE_LINE_2_ADC 27
379 #define SRCSLOT_SECONDARY_HEADSET_ADC 28
380
381 /* Source Slot Numbers - Others */
382 #define SRCSLOT_POWER_DOWN 31
383
384 /* MIDI modes */
385 #define CS4281_MODE_OUTPUT (1<<0)
386 #define CS4281_MODE_INPUT (1<<1)
387
388 /* joystick bits */
389 /* Bits for JSPT */
390 #define JSPT_CAX 0x00000001
391 #define JSPT_CAY 0x00000002
392 #define JSPT_CBX 0x00000004
393 #define JSPT_CBY 0x00000008
394 #define JSPT_BA1 0x00000010
395 #define JSPT_BA2 0x00000020
396 #define JSPT_BB1 0x00000040
397 #define JSPT_BB2 0x00000080
398
399 /* Bits for JSCTL */
400 #define JSCTL_SP_MASK 0x00000003
401 #define JSCTL_SP_SLOW 0x00000000
402 #define JSCTL_SP_MEDIUM_SLOW 0x00000001
403 #define JSCTL_SP_MEDIUM_FAST 0x00000002
404 #define JSCTL_SP_FAST 0x00000003
405 #define JSCTL_ARE 0x00000004
406
407 /* Data register pairs masks */
408 #define JSC1_Y1V_MASK 0x0000FFFF
409 #define JSC1_X1V_MASK 0xFFFF0000
410 #define JSC1_Y1V_SHIFT 0
411 #define JSC1_X1V_SHIFT 16
412 #define JSC2_Y2V_MASK 0x0000FFFF
413 #define JSC2_X2V_MASK 0xFFFF0000
414 #define JSC2_Y2V_SHIFT 0
415 #define JSC2_X2V_SHIFT 16
416
417 /* JS GPIO */
418 #define JSIO_DAX 0x00000001
419 #define JSIO_DAY 0x00000002
420 #define JSIO_DBX 0x00000004
421 #define JSIO_DBY 0x00000008
422 #define JSIO_AXOE 0x00000010
423 #define JSIO_AYOE 0x00000020
424 #define JSIO_BXOE 0x00000040
425 #define JSIO_BYOE 0x00000080
426
427 /*
428 *
429 */
430
431 struct cs4281_dma {
432 struct snd_pcm_substream *substream;
433 unsigned int regDBA; /* offset to DBA register */
434 unsigned int regDCA; /* offset to DCA register */
435 unsigned int regDBC; /* offset to DBC register */
436 unsigned int regDCC; /* offset to DCC register */
437 unsigned int regDMR; /* offset to DMR register */
438 unsigned int regDCR; /* offset to DCR register */
439 unsigned int regHDSR; /* offset to HDSR register */
440 unsigned int regFCR; /* offset to FCR register */
441 unsigned int regFSIC; /* offset to FSIC register */
442 unsigned int valDMR; /* DMA mode */
443 unsigned int valDCR; /* DMA command */
444 unsigned int valFCR; /* FIFO control */
445 unsigned int fifo_offset; /* FIFO offset within BA1 */
446 unsigned char left_slot; /* FIFO left slot */
447 unsigned char right_slot; /* FIFO right slot */
448 int frag; /* period number */
449 };
450
451 #define SUSPEND_REGISTERS 20
452
453 struct cs4281 {
454 int irq;
455
456 void __iomem *ba0; /* virtual (accessible) address */
457 void __iomem *ba1; /* virtual (accessible) address */
458 unsigned long ba0_addr;
459 unsigned long ba1_addr;
460
461 int dual_codec;
462
463 struct snd_ac97_bus *ac97_bus;
464 struct snd_ac97 *ac97;
465 struct snd_ac97 *ac97_secondary;
466
467 struct pci_dev *pci;
468 struct snd_card *card;
469 struct snd_pcm *pcm;
470 struct snd_rawmidi *rmidi;
471 struct snd_rawmidi_substream *midi_input;
472 struct snd_rawmidi_substream *midi_output;
473
474 struct cs4281_dma dma[4];
475
476 unsigned char src_left_play_slot;
477 unsigned char src_right_play_slot;
478 unsigned char src_left_rec_slot;
479 unsigned char src_right_rec_slot;
480
481 unsigned int spurious_dhtc_irq;
482 unsigned int spurious_dtc_irq;
483
484 spinlock_t reg_lock;
485 unsigned int midcr;
486 unsigned int uartm;
487
488 struct gameport *gameport;
489
490 #ifdef CONFIG_PM
491 u32 suspend_regs[SUSPEND_REGISTERS];
492 #endif
493
494 };
495
496 static irqreturn_t snd_cs4281_interrupt(int irq, void *dev_id);
497
498 static struct pci_device_id snd_cs4281_ids[] = {
499 { 0x1013, 0x6005, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0, }, /* CS4281 */
500 { 0, }
501 };
502
503 MODULE_DEVICE_TABLE(pci, snd_cs4281_ids);
504
505 /*
506 * constants
507 */
508
509 #define CS4281_FIFO_SIZE 32
510
511 /*
512 * common I/O routines
513 */
514
515 static inline void snd_cs4281_pokeBA0(struct cs4281 *chip, unsigned long offset,
516 unsigned int val)
517 {
518 writel(val, chip->ba0 + offset);
519 }
520
521 static inline unsigned int snd_cs4281_peekBA0(struct cs4281 *chip, unsigned long offset)
522 {
523 return readl(chip->ba0 + offset);
524 }
525
526 static void snd_cs4281_ac97_write(struct snd_ac97 *ac97,
527 unsigned short reg, unsigned short val)
528 {
529 /*
530 * 1. Write ACCAD = Command Address Register = 46Ch for AC97 register address
531 * 2. Write ACCDA = Command Data Register = 470h for data to write to AC97
532 * 3. Write ACCTL = Control Register = 460h for initiating the write
533 * 4. Read ACCTL = 460h, DCV should be reset by now and 460h = 07h
534 * 5. if DCV not cleared, break and return error
535 */
536 struct cs4281 *chip = ac97->private_data;
537 int count;
538
539 /*
540 * Setup the AC97 control registers on the CS461x to send the
541 * appropriate command to the AC97 to perform the read.
542 * ACCAD = Command Address Register = 46Ch
543 * ACCDA = Command Data Register = 470h
544 * ACCTL = Control Register = 460h
545 * set DCV - will clear when process completed
546 * reset CRW - Write command
547 * set VFRM - valid frame enabled
548 * set ESYN - ASYNC generation enabled
549 * set RSTN - ARST# inactive, AC97 codec not reset
550 */
551 snd_cs4281_pokeBA0(chip, BA0_ACCAD, reg);
552 snd_cs4281_pokeBA0(chip, BA0_ACCDA, val);
553 snd_cs4281_pokeBA0(chip, BA0_ACCTL, BA0_ACCTL_DCV | BA0_ACCTL_VFRM |
554 BA0_ACCTL_ESYN | (ac97->num ? BA0_ACCTL_TC : 0));
555 for (count = 0; count < 2000; count++) {
556 /*
557 * First, we want to wait for a short time.
558 */
559 udelay(10);
560 /*
561 * Now, check to see if the write has completed.
562 * ACCTL = 460h, DCV should be reset by now and 460h = 07h
563 */
564 if (!(snd_cs4281_peekBA0(chip, BA0_ACCTL) & BA0_ACCTL_DCV)) {
565 return;
566 }
567 }
568 snd_printk(KERN_ERR "AC'97 write problem, reg = 0x%x, val = 0x%x\n", reg, val);
569 }
570
571 static unsigned short snd_cs4281_ac97_read(struct snd_ac97 *ac97,
572 unsigned short reg)
573 {
574 struct cs4281 *chip = ac97->private_data;
575 int count;
576 unsigned short result;
577 // FIXME: volatile is necessary in the following due to a bug of
578 // some gcc versions
579 volatile int ac97_num = ((volatile struct snd_ac97 *)ac97)->num;
580
581 /*
582 * 1. Write ACCAD = Command Address Register = 46Ch for AC97 register address
583 * 2. Write ACCDA = Command Data Register = 470h for data to write to AC97
584 * 3. Write ACCTL = Control Register = 460h for initiating the write
585 * 4. Read ACCTL = 460h, DCV should be reset by now and 460h = 17h
586 * 5. if DCV not cleared, break and return error
587 * 6. Read ACSTS = Status Register = 464h, check VSTS bit
588 */
589
590 snd_cs4281_peekBA0(chip, ac97_num ? BA0_ACSDA2 : BA0_ACSDA);
591
592 /*
593 * Setup the AC97 control registers on the CS461x to send the
594 * appropriate command to the AC97 to perform the read.
595 * ACCAD = Command Address Register = 46Ch
596 * ACCDA = Command Data Register = 470h
597 * ACCTL = Control Register = 460h
598 * set DCV - will clear when process completed
599 * set CRW - Read command
600 * set VFRM - valid frame enabled
601 * set ESYN - ASYNC generation enabled
602 * set RSTN - ARST# inactive, AC97 codec not reset
603 */
604
605 snd_cs4281_pokeBA0(chip, BA0_ACCAD, reg);
606 snd_cs4281_pokeBA0(chip, BA0_ACCDA, 0);
607 snd_cs4281_pokeBA0(chip, BA0_ACCTL, BA0_ACCTL_DCV | BA0_ACCTL_CRW |
608 BA0_ACCTL_VFRM | BA0_ACCTL_ESYN |
609 (ac97_num ? BA0_ACCTL_TC : 0));
610
611
612 /*
613 * Wait for the read to occur.
614 */
615 for (count = 0; count < 500; count++) {
616 /*
617 * First, we want to wait for a short time.
618 */
619 udelay(10);
620 /*
621 * Now, check to see if the read has completed.
622 * ACCTL = 460h, DCV should be reset by now and 460h = 17h
623 */
624 if (!(snd_cs4281_peekBA0(chip, BA0_ACCTL) & BA0_ACCTL_DCV))
625 goto __ok1;
626 }
627
628 snd_printk(KERN_ERR "AC'97 read problem (ACCTL_DCV), reg = 0x%x\n", reg);
629 result = 0xffff;
630 goto __end;
631
632 __ok1:
633 /*
634 * Wait for the valid status bit to go active.
635 */
636 for (count = 0; count < 100; count++) {
637 /*
638 * Read the AC97 status register.
639 * ACSTS = Status Register = 464h
640 * VSTS - Valid Status
641 */
642 if (snd_cs4281_peekBA0(chip, ac97_num ? BA0_ACSTS2 : BA0_ACSTS) & BA0_ACSTS_VSTS)
643 goto __ok2;
644 udelay(10);
645 }
646
647 snd_printk(KERN_ERR "AC'97 read problem (ACSTS_VSTS), reg = 0x%x\n", reg);
648 result = 0xffff;
649 goto __end;
650
651 __ok2:
652 /*
653 * Read the data returned from the AC97 register.
654 * ACSDA = Status Data Register = 474h
655 */
656 result = snd_cs4281_peekBA0(chip, ac97_num ? BA0_ACSDA2 : BA0_ACSDA);
657
658 __end:
659 return result;
660 }
661
662 /*
663 * PCM part
664 */
665
666 static int snd_cs4281_trigger(struct snd_pcm_substream *substream, int cmd)
667 {
668 struct cs4281_dma *dma = substream->runtime->private_data;
669 struct cs4281 *chip = snd_pcm_substream_chip(substream);
670
671 spin_lock(&chip->reg_lock);
672 switch (cmd) {
673 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
674 dma->valDCR |= BA0_DCR_MSK;
675 dma->valFCR |= BA0_FCR_FEN;
676 break;
677 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
678 dma->valDCR &= ~BA0_DCR_MSK;
679 dma->valFCR &= ~BA0_FCR_FEN;
680 break;
681 case SNDRV_PCM_TRIGGER_START:
682 case SNDRV_PCM_TRIGGER_RESUME:
683 snd_cs4281_pokeBA0(chip, dma->regDMR, dma->valDMR & ~BA0_DMR_DMA);
684 dma->valDMR |= BA0_DMR_DMA;
685 dma->valDCR &= ~BA0_DCR_MSK;
686 dma->valFCR |= BA0_FCR_FEN;
687 break;
688 case SNDRV_PCM_TRIGGER_STOP:
689 case SNDRV_PCM_TRIGGER_SUSPEND:
690 dma->valDMR &= ~(BA0_DMR_DMA|BA0_DMR_POLL);
691 dma->valDCR |= BA0_DCR_MSK;
692 dma->valFCR &= ~BA0_FCR_FEN;
693 /* Leave wave playback FIFO enabled for FM */
694 if (dma->regFCR != BA0_FCR0)
695 dma->valFCR &= ~BA0_FCR_FEN;
696 break;
697 default:
698 spin_unlock(&chip->reg_lock);
699 return -EINVAL;
700 }
701 snd_cs4281_pokeBA0(chip, dma->regDMR, dma->valDMR);
702 snd_cs4281_pokeBA0(chip, dma->regFCR, dma->valFCR);
703 snd_cs4281_pokeBA0(chip, dma->regDCR, dma->valDCR);
704 spin_unlock(&chip->reg_lock);
705 return 0;
706 }
707
708 static unsigned int snd_cs4281_rate(unsigned int rate, unsigned int *real_rate)
709 {
710 unsigned int val = ~0;
711
712 if (real_rate)
713 *real_rate = rate;
714 /* special "hardcoded" rates */
715 switch (rate) {
716 case 8000: return 5;
717 case 11025: return 4;
718 case 16000: return 3;
719 case 22050: return 2;
720 case 44100: return 1;
721 case 48000: return 0;
722 default:
723 goto __variable;
724 }
725 __variable:
726 val = 1536000 / rate;
727 if (real_rate)
728 *real_rate = 1536000 / val;
729 return val;
730 }
731
732 static void snd_cs4281_mode(struct cs4281 *chip, struct cs4281_dma *dma,
733 struct snd_pcm_runtime *runtime,
734 int capture, int src)
735 {
736 int rec_mono;
737
738 dma->valDMR = BA0_DMR_TYPE_SINGLE | BA0_DMR_AUTO |
739 (capture ? BA0_DMR_TR_WRITE : BA0_DMR_TR_READ);
740 if (runtime->channels == 1)
741 dma->valDMR |= BA0_DMR_MONO;
742 if (snd_pcm_format_unsigned(runtime->format) > 0)
743 dma->valDMR |= BA0_DMR_USIGN;
744 if (snd_pcm_format_big_endian(runtime->format) > 0)
745 dma->valDMR |= BA0_DMR_BEND;
746 switch (snd_pcm_format_width(runtime->format)) {
747 case 8: dma->valDMR |= BA0_DMR_SIZE8;
748 if (runtime->channels == 1)
749 dma->valDMR |= BA0_DMR_SWAPC;
750 break;
751 case 32: dma->valDMR |= BA0_DMR_SIZE20; break;
752 }
753 dma->frag = 0; /* for workaround */
754 dma->valDCR = BA0_DCR_TCIE | BA0_DCR_MSK;
755 if (runtime->buffer_size != runtime->period_size)
756 dma->valDCR |= BA0_DCR_HTCIE;
757 /* Initialize DMA */
758 snd_cs4281_pokeBA0(chip, dma->regDBA, runtime->dma_addr);
759 snd_cs4281_pokeBA0(chip, dma->regDBC, runtime->buffer_size - 1);
760 rec_mono = (chip->dma[1].valDMR & BA0_DMR_MONO) == BA0_DMR_MONO;
761 snd_cs4281_pokeBA0(chip, BA0_SRCSA, (chip->src_left_play_slot << 0) |
762 (chip->src_right_play_slot << 8) |
763 (chip->src_left_rec_slot << 16) |
764 ((rec_mono ? 31 : chip->src_right_rec_slot) << 24));
765 if (!src)
766 goto __skip_src;
767 if (!capture) {
768 if (dma->left_slot == chip->src_left_play_slot) {
769 unsigned int val = snd_cs4281_rate(runtime->rate, NULL);
770 snd_assert(dma->right_slot == chip->src_right_play_slot, );
771 snd_cs4281_pokeBA0(chip, BA0_DACSR, val);
772 }
773 } else {
774 if (dma->left_slot == chip->src_left_rec_slot) {
775 unsigned int val = snd_cs4281_rate(runtime->rate, NULL);
776 snd_assert(dma->right_slot == chip->src_right_rec_slot, );
777 snd_cs4281_pokeBA0(chip, BA0_ADCSR, val);
778 }
779 }
780 __skip_src:
781 /* Deactivate wave playback FIFO before changing slot assignments */
782 if (dma->regFCR == BA0_FCR0)
783 snd_cs4281_pokeBA0(chip, dma->regFCR, snd_cs4281_peekBA0(chip, dma->regFCR) & ~BA0_FCR_FEN);
784 /* Initialize FIFO */
785 dma->valFCR = BA0_FCR_LS(dma->left_slot) |
786 BA0_FCR_RS(capture && (dma->valDMR & BA0_DMR_MONO) ? 31 : dma->right_slot) |
787 BA0_FCR_SZ(CS4281_FIFO_SIZE) |
788 BA0_FCR_OF(dma->fifo_offset);
789 snd_cs4281_pokeBA0(chip, dma->regFCR, dma->valFCR | (capture ? BA0_FCR_PSH : 0));
790 /* Activate FIFO again for FM playback */
791 if (dma->regFCR == BA0_FCR0)
792 snd_cs4281_pokeBA0(chip, dma->regFCR, dma->valFCR | BA0_FCR_FEN);
793 /* Clear FIFO Status and Interrupt Control Register */
794 snd_cs4281_pokeBA0(chip, dma->regFSIC, 0);
795 }
796
797 static int snd_cs4281_hw_params(struct snd_pcm_substream *substream,
798 struct snd_pcm_hw_params *hw_params)
799 {
800 return snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params));
801 }
802
803 static int snd_cs4281_hw_free(struct snd_pcm_substream *substream)
804 {
805 return snd_pcm_lib_free_pages(substream);
806 }
807
808 static int snd_cs4281_playback_prepare(struct snd_pcm_substream *substream)
809 {
810 struct snd_pcm_runtime *runtime = substream->runtime;
811 struct cs4281_dma *dma = runtime->private_data;
812 struct cs4281 *chip = snd_pcm_substream_chip(substream);
813
814 spin_lock_irq(&chip->reg_lock);
815 snd_cs4281_mode(chip, dma, runtime, 0, 1);
816 spin_unlock_irq(&chip->reg_lock);
817 return 0;
818 }
819
820 static int snd_cs4281_capture_prepare(struct snd_pcm_substream *substream)
821 {
822 struct snd_pcm_runtime *runtime = substream->runtime;
823 struct cs4281_dma *dma = runtime->private_data;
824 struct cs4281 *chip = snd_pcm_substream_chip(substream);
825
826 spin_lock_irq(&chip->reg_lock);
827 snd_cs4281_mode(chip, dma, runtime, 1, 1);
828 spin_unlock_irq(&chip->reg_lock);
829 return 0;
830 }
831
832 static snd_pcm_uframes_t snd_cs4281_pointer(struct snd_pcm_substream *substream)
833 {
834 struct snd_pcm_runtime *runtime = substream->runtime;
835 struct cs4281_dma *dma = runtime->private_data;
836 struct cs4281 *chip = snd_pcm_substream_chip(substream);
837
838 // printk("DCC = 0x%x, buffer_size = 0x%x, jiffies = %li\n", snd_cs4281_peekBA0(chip, dma->regDCC), runtime->buffer_size, jiffies);
839 return runtime->buffer_size -
840 snd_cs4281_peekBA0(chip, dma->regDCC) - 1;
841 }
842
843 static struct snd_pcm_hardware snd_cs4281_playback =
844 {
845 .info = SNDRV_PCM_INFO_MMAP |
846 SNDRV_PCM_INFO_INTERLEAVED |
847 SNDRV_PCM_INFO_MMAP_VALID |
848 SNDRV_PCM_INFO_PAUSE |
849 SNDRV_PCM_INFO_RESUME,
850 .formats = SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S8 |
851 SNDRV_PCM_FMTBIT_U16_LE | SNDRV_PCM_FMTBIT_S16_LE |
852 SNDRV_PCM_FMTBIT_U16_BE | SNDRV_PCM_FMTBIT_S16_BE |
853 SNDRV_PCM_FMTBIT_U32_LE | SNDRV_PCM_FMTBIT_S32_LE |
854 SNDRV_PCM_FMTBIT_U32_BE | SNDRV_PCM_FMTBIT_S32_BE,
855 .rates = SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000,
856 .rate_min = 4000,
857 .rate_max = 48000,
858 .channels_min = 1,
859 .channels_max = 2,
860 .buffer_bytes_max = (512*1024),
861 .period_bytes_min = 64,
862 .period_bytes_max = (512*1024),
863 .periods_min = 1,
864 .periods_max = 2,
865 .fifo_size = CS4281_FIFO_SIZE,
866 };
867
868 static struct snd_pcm_hardware snd_cs4281_capture =
869 {
870 .info = SNDRV_PCM_INFO_MMAP |
871 SNDRV_PCM_INFO_INTERLEAVED |
872 SNDRV_PCM_INFO_MMAP_VALID |
873 SNDRV_PCM_INFO_PAUSE |
874 SNDRV_PCM_INFO_RESUME,
875 .formats = SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S8 |
876 SNDRV_PCM_FMTBIT_U16_LE | SNDRV_PCM_FMTBIT_S16_LE |
877 SNDRV_PCM_FMTBIT_U16_BE | SNDRV_PCM_FMTBIT_S16_BE |
878 SNDRV_PCM_FMTBIT_U32_LE | SNDRV_PCM_FMTBIT_S32_LE |
879 SNDRV_PCM_FMTBIT_U32_BE | SNDRV_PCM_FMTBIT_S32_BE,
880 .rates = SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000,
881 .rate_min = 4000,
882 .rate_max = 48000,
883 .channels_min = 1,
884 .channels_max = 2,
885 .buffer_bytes_max = (512*1024),
886 .period_bytes_min = 64,
887 .period_bytes_max = (512*1024),
888 .periods_min = 1,
889 .periods_max = 2,
890 .fifo_size = CS4281_FIFO_SIZE,
891 };
892
893 static int snd_cs4281_playback_open(struct snd_pcm_substream *substream)
894 {
895 struct cs4281 *chip = snd_pcm_substream_chip(substream);
896 struct snd_pcm_runtime *runtime = substream->runtime;
897 struct cs4281_dma *dma;
898
899 dma = &chip->dma[0];
900 dma->substream = substream;
901 dma->left_slot = 0;
902 dma->right_slot = 1;
903 runtime->private_data = dma;
904 runtime->hw = snd_cs4281_playback;
905 /* should be detected from the AC'97 layer, but it seems
906 that although CS4297A rev B reports 18-bit ADC resolution,
907 samples are 20-bit */
908 snd_pcm_hw_constraint_msbits(runtime, 0, 32, 20);
909 return 0;
910 }
911
912 static int snd_cs4281_capture_open(struct snd_pcm_substream *substream)
913 {
914 struct cs4281 *chip = snd_pcm_substream_chip(substream);
915 struct snd_pcm_runtime *runtime = substream->runtime;
916 struct cs4281_dma *dma;
917
918 dma = &chip->dma[1];
919 dma->substream = substream;
920 dma->left_slot = 10;
921 dma->right_slot = 11;
922 runtime->private_data = dma;
923 runtime->hw = snd_cs4281_capture;
924 /* should be detected from the AC'97 layer, but it seems
925 that although CS4297A rev B reports 18-bit ADC resolution,
926 samples are 20-bit */
927 snd_pcm_hw_constraint_msbits(runtime, 0, 32, 20);
928 return 0;
929 }
930
931 static int snd_cs4281_playback_close(struct snd_pcm_substream *substream)
932 {
933 struct cs4281_dma *dma = substream->runtime->private_data;
934
935 dma->substream = NULL;
936 return 0;
937 }
938
939 static int snd_cs4281_capture_close(struct snd_pcm_substream *substream)
940 {
941 struct cs4281_dma *dma = substream->runtime->private_data;
942
943 dma->substream = NULL;
944 return 0;
945 }
946
947 static struct snd_pcm_ops snd_cs4281_playback_ops = {
948 .open = snd_cs4281_playback_open,
949 .close = snd_cs4281_playback_close,
950 .ioctl = snd_pcm_lib_ioctl,
951 .hw_params = snd_cs4281_hw_params,
952 .hw_free = snd_cs4281_hw_free,
953 .prepare = snd_cs4281_playback_prepare,
954 .trigger = snd_cs4281_trigger,
955 .pointer = snd_cs4281_pointer,
956 };
957
958 static struct snd_pcm_ops snd_cs4281_capture_ops = {
959 .open = snd_cs4281_capture_open,
960 .close = snd_cs4281_capture_close,
961 .ioctl = snd_pcm_lib_ioctl,
962 .hw_params = snd_cs4281_hw_params,
963 .hw_free = snd_cs4281_hw_free,
964 .prepare = snd_cs4281_capture_prepare,
965 .trigger = snd_cs4281_trigger,
966 .pointer = snd_cs4281_pointer,
967 };
968
969 static int __devinit snd_cs4281_pcm(struct cs4281 * chip, int device,
970 struct snd_pcm ** rpcm)
971 {
972 struct snd_pcm *pcm;
973 int err;
974
975 if (rpcm)
976 *rpcm = NULL;
977 err = snd_pcm_new(chip->card, "CS4281", device, 1, 1, &pcm);
978 if (err < 0)
979 return err;
980
981 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_cs4281_playback_ops);
982 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_cs4281_capture_ops);
983
984 pcm->private_data = chip;
985 pcm->info_flags = 0;
986 strcpy(pcm->name, "CS4281");
987 chip->pcm = pcm;
988
989 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
990 snd_dma_pci_data(chip->pci), 64*1024, 512*1024);
991
992 if (rpcm)
993 *rpcm = pcm;
994 return 0;
995 }
996
997 /*
998 * Mixer section
999 */
1000
1001 #define CS_VOL_MASK 0x1f
1002
1003 static int snd_cs4281_info_volume(struct snd_kcontrol *kcontrol,
1004 struct snd_ctl_elem_info *uinfo)
1005 {
1006 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
1007 uinfo->count = 2;
1008 uinfo->value.integer.min = 0;
1009 uinfo->value.integer.max = CS_VOL_MASK;
1010 return 0;
1011 }
1012
1013 static int snd_cs4281_get_volume(struct snd_kcontrol *kcontrol,
1014 struct snd_ctl_elem_value *ucontrol)
1015 {
1016 struct cs4281 *chip = snd_kcontrol_chip(kcontrol);
1017 int regL = (kcontrol->private_value >> 16) & 0xffff;
1018 int regR = kcontrol->private_value & 0xffff;
1019 int volL, volR;
1020
1021 volL = CS_VOL_MASK - (snd_cs4281_peekBA0(chip, regL) & CS_VOL_MASK);
1022 volR = CS_VOL_MASK - (snd_cs4281_peekBA0(chip, regR) & CS_VOL_MASK);
1023
1024 ucontrol->value.integer.value[0] = volL;
1025 ucontrol->value.integer.value[1] = volR;
1026 return 0;
1027 }
1028
1029 static int snd_cs4281_put_volume(struct snd_kcontrol *kcontrol,
1030 struct snd_ctl_elem_value *ucontrol)
1031 {
1032 struct cs4281 *chip = snd_kcontrol_chip(kcontrol);
1033 int change = 0;
1034 int regL = (kcontrol->private_value >> 16) & 0xffff;
1035 int regR = kcontrol->private_value & 0xffff;
1036 int volL, volR;
1037
1038 volL = CS_VOL_MASK - (snd_cs4281_peekBA0(chip, regL) & CS_VOL_MASK);
1039 volR = CS_VOL_MASK - (snd_cs4281_peekBA0(chip, regR) & CS_VOL_MASK);
1040
1041 if (ucontrol->value.integer.value[0] != volL) {
1042 volL = CS_VOL_MASK - (ucontrol->value.integer.value[0] & CS_VOL_MASK);
1043 snd_cs4281_pokeBA0(chip, regL, volL);
1044 change = 1;
1045 }
1046 if (ucontrol->value.integer.value[1] != volR) {
1047 volR = CS_VOL_MASK - (ucontrol->value.integer.value[1] & CS_VOL_MASK);
1048 snd_cs4281_pokeBA0(chip, regR, volR);
1049 change = 1;
1050 }
1051 return change;
1052 }
1053
1054 static const DECLARE_TLV_DB_SCALE(db_scale_dsp, -4650, 150, 0);
1055
1056 static struct snd_kcontrol_new snd_cs4281_fm_vol =
1057 {
1058 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
1059 .name = "Synth Playback Volume",
1060 .info = snd_cs4281_info_volume,
1061 .get = snd_cs4281_get_volume,
1062 .put = snd_cs4281_put_volume,
1063 .private_value = ((BA0_FMLVC << 16) | BA0_FMRVC),
1064 .tlv = { .p = db_scale_dsp },
1065 };
1066
1067 static struct snd_kcontrol_new snd_cs4281_pcm_vol =
1068 {
1069 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
1070 .name = "PCM Stream Playback Volume",
1071 .info = snd_cs4281_info_volume,
1072 .get = snd_cs4281_get_volume,
1073 .put = snd_cs4281_put_volume,
1074 .private_value = ((BA0_PPLVC << 16) | BA0_PPRVC),
1075 .tlv = { .p = db_scale_dsp },
1076 };
1077
1078 static void snd_cs4281_mixer_free_ac97_bus(struct snd_ac97_bus *bus)
1079 {
1080 struct cs4281 *chip = bus->private_data;
1081 chip->ac97_bus = NULL;
1082 }
1083
1084 static void snd_cs4281_mixer_free_ac97(struct snd_ac97 *ac97)
1085 {
1086 struct cs4281 *chip = ac97->private_data;
1087 if (ac97->num)
1088 chip->ac97_secondary = NULL;
1089 else
1090 chip->ac97 = NULL;
1091 }
1092
1093 static int __devinit snd_cs4281_mixer(struct cs4281 * chip)
1094 {
1095 struct snd_card *card = chip->card;
1096 struct snd_ac97_template ac97;
1097 int err;
1098 static struct snd_ac97_bus_ops ops = {
1099 .write = snd_cs4281_ac97_write,
1100 .read = snd_cs4281_ac97_read,
1101 };
1102
1103 if ((err = snd_ac97_bus(card, 0, &ops, chip, &chip->ac97_bus)) < 0)
1104 return err;
1105 chip->ac97_bus->private_free = snd_cs4281_mixer_free_ac97_bus;
1106
1107 memset(&ac97, 0, sizeof(ac97));
1108 ac97.private_data = chip;
1109 ac97.private_free = snd_cs4281_mixer_free_ac97;
1110 if ((err = snd_ac97_mixer(chip->ac97_bus, &ac97, &chip->ac97)) < 0)
1111 return err;
1112 if (chip->dual_codec) {
1113 ac97.num = 1;
1114 if ((err = snd_ac97_mixer(chip->ac97_bus, &ac97, &chip->ac97_secondary)) < 0)
1115 return err;
1116 }
1117 if ((err = snd_ctl_add(card, snd_ctl_new1(&snd_cs4281_fm_vol, chip))) < 0)
1118 return err;
1119 if ((err = snd_ctl_add(card, snd_ctl_new1(&snd_cs4281_pcm_vol, chip))) < 0)
1120 return err;
1121 return 0;
1122 }
1123
1124
1125 /*
1126 * proc interface
1127 */
1128
1129 static void snd_cs4281_proc_read(struct snd_info_entry *entry,
1130 struct snd_info_buffer *buffer)
1131 {
1132 struct cs4281 *chip = entry->private_data;
1133
1134 snd_iprintf(buffer, "Cirrus Logic CS4281\n\n");
1135 snd_iprintf(buffer, "Spurious half IRQs : %u\n", chip->spurious_dhtc_irq);
1136 snd_iprintf(buffer, "Spurious end IRQs : %u\n", chip->spurious_dtc_irq);
1137 }
1138
1139 static long snd_cs4281_BA0_read(struct snd_info_entry *entry,
1140 void *file_private_data,
1141 struct file *file, char __user *buf,
1142 unsigned long count, unsigned long pos)
1143 {
1144 long size;
1145 struct cs4281 *chip = entry->private_data;
1146
1147 size = count;
1148 if (pos + size > CS4281_BA0_SIZE)
1149 size = (long)CS4281_BA0_SIZE - pos;
1150 if (size > 0) {
1151 if (copy_to_user_fromio(buf, chip->ba0 + pos, size))
1152 return -EFAULT;
1153 }
1154 return size;
1155 }
1156
1157 static long snd_cs4281_BA1_read(struct snd_info_entry *entry,
1158 void *file_private_data,
1159 struct file *file, char __user *buf,
1160 unsigned long count, unsigned long pos)
1161 {
1162 long size;
1163 struct cs4281 *chip = entry->private_data;
1164
1165 size = count;
1166 if (pos + size > CS4281_BA1_SIZE)
1167 size = (long)CS4281_BA1_SIZE - pos;
1168 if (size > 0) {
1169 if (copy_to_user_fromio(buf, chip->ba1 + pos, size))
1170 return -EFAULT;
1171 }
1172 return size;
1173 }
1174
1175 static struct snd_info_entry_ops snd_cs4281_proc_ops_BA0 = {
1176 .read = snd_cs4281_BA0_read,
1177 };
1178
1179 static struct snd_info_entry_ops snd_cs4281_proc_ops_BA1 = {
1180 .read = snd_cs4281_BA1_read,
1181 };
1182
1183 static void __devinit snd_cs4281_proc_init(struct cs4281 * chip)
1184 {
1185 struct snd_info_entry *entry;
1186
1187 if (! snd_card_proc_new(chip->card, "cs4281", &entry))
1188 snd_info_set_text_ops(entry, chip, snd_cs4281_proc_read);
1189 if (! snd_card_proc_new(chip->card, "cs4281_BA0", &entry)) {
1190 entry->content = SNDRV_INFO_CONTENT_DATA;
1191 entry->private_data = chip;
1192 entry->c.ops = &snd_cs4281_proc_ops_BA0;
1193 entry->size = CS4281_BA0_SIZE;
1194 }
1195 if (! snd_card_proc_new(chip->card, "cs4281_BA1", &entry)) {
1196 entry->content = SNDRV_INFO_CONTENT_DATA;
1197 entry->private_data = chip;
1198 entry->c.ops = &snd_cs4281_proc_ops_BA1;
1199 entry->size = CS4281_BA1_SIZE;
1200 }
1201 }
1202
1203 /*
1204 * joystick support
1205 */
1206
1207 #if defined(CONFIG_GAMEPORT) || (defined(MODULE) && defined(CONFIG_GAMEPORT_MODULE))
1208
1209 static void snd_cs4281_gameport_trigger(struct gameport *gameport)
1210 {
1211 struct cs4281 *chip = gameport_get_port_data(gameport);
1212
1213 snd_assert(chip, return);
1214 snd_cs4281_pokeBA0(chip, BA0_JSPT, 0xff);
1215 }
1216
1217 static unsigned char snd_cs4281_gameport_read(struct gameport *gameport)
1218 {
1219 struct cs4281 *chip = gameport_get_port_data(gameport);
1220
1221 snd_assert(chip, return 0);
1222 return snd_cs4281_peekBA0(chip, BA0_JSPT);
1223 }
1224
1225 #ifdef COOKED_MODE
1226 static int snd_cs4281_gameport_cooked_read(struct gameport *gameport,
1227 int *axes, int *buttons)
1228 {
1229 struct cs4281 *chip = gameport_get_port_data(gameport);
1230 unsigned js1, js2, jst;
1231
1232 snd_assert(chip, return 0);
1233
1234 js1 = snd_cs4281_peekBA0(chip, BA0_JSC1);
1235 js2 = snd_cs4281_peekBA0(chip, BA0_JSC2);
1236 jst = snd_cs4281_peekBA0(chip, BA0_JSPT);
1237
1238 *buttons = (~jst >> 4) & 0x0F;
1239
1240 axes[0] = ((js1 & JSC1_Y1V_MASK) >> JSC1_Y1V_SHIFT) & 0xFFFF;
1241 axes[1] = ((js1 & JSC1_X1V_MASK) >> JSC1_X1V_SHIFT) & 0xFFFF;
1242 axes[2] = ((js2 & JSC2_Y2V_MASK) >> JSC2_Y2V_SHIFT) & 0xFFFF;
1243 axes[3] = ((js2 & JSC2_X2V_MASK) >> JSC2_X2V_SHIFT) & 0xFFFF;
1244
1245 for (jst = 0; jst < 4; ++jst)
1246 if (axes[jst] == 0xFFFF) axes[jst] = -1;
1247 return 0;
1248 }
1249 #else
1250 #define snd_cs4281_gameport_cooked_read NULL
1251 #endif
1252
1253 static int snd_cs4281_gameport_open(struct gameport *gameport, int mode)
1254 {
1255 switch (mode) {
1256 #ifdef COOKED_MODE
1257 case GAMEPORT_MODE_COOKED:
1258 return 0;
1259 #endif
1260 case GAMEPORT_MODE_RAW:
1261 return 0;
1262 default:
1263 return -1;
1264 }
1265 return 0;
1266 }
1267
1268 static int __devinit snd_cs4281_create_gameport(struct cs4281 *chip)
1269 {
1270 struct gameport *gp;
1271
1272 chip->gameport = gp = gameport_allocate_port();
1273 if (!gp) {
1274 printk(KERN_ERR "cs4281: cannot allocate memory for gameport\n");
1275 return -ENOMEM;
1276 }
1277
1278 gameport_set_name(gp, "CS4281 Gameport");
1279 gameport_set_phys(gp, "pci%s/gameport0", pci_name(chip->pci));
1280 gameport_set_dev_parent(gp, &chip->pci->dev);
1281 gp->open = snd_cs4281_gameport_open;
1282 gp->read = snd_cs4281_gameport_read;
1283 gp->trigger = snd_cs4281_gameport_trigger;
1284 gp->cooked_read = snd_cs4281_gameport_cooked_read;
1285 gameport_set_port_data(gp, chip);
1286
1287 snd_cs4281_pokeBA0(chip, BA0_JSIO, 0xFF); // ?
1288 snd_cs4281_pokeBA0(chip, BA0_JSCTL, JSCTL_SP_MEDIUM_SLOW);
1289
1290 gameport_register_port(gp);
1291
1292 return 0;
1293 }
1294
1295 static void snd_cs4281_free_gameport(struct cs4281 *chip)
1296 {
1297 if (chip->gameport) {
1298 gameport_unregister_port(chip->gameport);
1299 chip->gameport = NULL;
1300 }
1301 }
1302 #else
1303 static inline int snd_cs4281_create_gameport(struct cs4281 *chip) { return -ENOSYS; }
1304 static inline void snd_cs4281_free_gameport(struct cs4281 *chip) { }
1305 #endif /* CONFIG_GAMEPORT || (MODULE && CONFIG_GAMEPORT_MODULE) */
1306
1307 static int snd_cs4281_free(struct cs4281 *chip)
1308 {
1309 snd_cs4281_free_gameport(chip);
1310
1311 if (chip->irq >= 0)
1312 synchronize_irq(chip->irq);
1313
1314 /* Mask interrupts */
1315 snd_cs4281_pokeBA0(chip, BA0_HIMR, 0x7fffffff);
1316 /* Stop the DLL Clock logic. */
1317 snd_cs4281_pokeBA0(chip, BA0_CLKCR1, 0);
1318 /* Sound System Power Management - Turn Everything OFF */
1319 snd_cs4281_pokeBA0(chip, BA0_SSPM, 0);
1320 /* PCI interface - D3 state */
1321 pci_set_power_state(chip->pci, 3);
1322
1323 if (chip->irq >= 0)
1324 free_irq(chip->irq, chip);
1325 if (chip->ba0)
1326 iounmap(chip->ba0);
1327 if (chip->ba1)
1328 iounmap(chip->ba1);
1329 pci_release_regions(chip->pci);
1330 pci_disable_device(chip->pci);
1331
1332 kfree(chip);
1333 return 0;
1334 }
1335
1336 static int snd_cs4281_dev_free(struct snd_device *device)
1337 {
1338 struct cs4281 *chip = device->device_data;
1339 return snd_cs4281_free(chip);
1340 }
1341
1342 static int snd_cs4281_chip_init(struct cs4281 *chip); /* defined below */
1343
1344 static int __devinit snd_cs4281_create(struct snd_card *card,
1345 struct pci_dev *pci,
1346 struct cs4281 ** rchip,
1347 int dual_codec)
1348 {
1349 struct cs4281 *chip;
1350 unsigned int tmp;
1351 int err;
1352 static struct snd_device_ops ops = {
1353 .dev_free = snd_cs4281_dev_free,
1354 };
1355
1356 *rchip = NULL;
1357 if ((err = pci_enable_device(pci)) < 0)
1358 return err;
1359 chip = kzalloc(sizeof(*chip), GFP_KERNEL);
1360 if (chip == NULL) {
1361 pci_disable_device(pci);
1362 return -ENOMEM;
1363 }
1364 spin_lock_init(&chip->reg_lock);
1365 chip->card = card;
1366 chip->pci = pci;
1367 chip->irq = -1;
1368 pci_set_master(pci);
1369 if (dual_codec < 0 || dual_codec > 3) {
1370 snd_printk(KERN_ERR "invalid dual_codec option %d\n", dual_codec);
1371 dual_codec = 0;
1372 }
1373 chip->dual_codec = dual_codec;
1374
1375 if ((err = pci_request_regions(pci, "CS4281")) < 0) {
1376 kfree(chip);
1377 pci_disable_device(pci);
1378 return err;
1379 }
1380 chip->ba0_addr = pci_resource_start(pci, 0);
1381 chip->ba1_addr = pci_resource_start(pci, 1);
1382
1383 chip->ba0 = ioremap_nocache(chip->ba0_addr, pci_resource_len(pci, 0));
1384 chip->ba1 = ioremap_nocache(chip->ba1_addr, pci_resource_len(pci, 1));
1385 if (!chip->ba0 || !chip->ba1) {
1386 snd_cs4281_free(chip);
1387 return -ENOMEM;
1388 }
1389
1390 if (request_irq(pci->irq, snd_cs4281_interrupt, IRQF_SHARED,
1391 "CS4281", chip)) {
1392 snd_printk(KERN_ERR "unable to grab IRQ %d\n", pci->irq);
1393 snd_cs4281_free(chip);
1394 return -ENOMEM;
1395 }
1396 chip->irq = pci->irq;
1397
1398 tmp = snd_cs4281_chip_init(chip);
1399 if (tmp) {
1400 snd_cs4281_free(chip);
1401 return tmp;
1402 }
1403
1404 if ((err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops)) < 0) {
1405 snd_cs4281_free(chip);
1406 return err;
1407 }
1408
1409 snd_cs4281_proc_init(chip);
1410
1411 snd_card_set_dev(card, &pci->dev);
1412
1413 *rchip = chip;
1414 return 0;
1415 }
1416
1417 static int snd_cs4281_chip_init(struct cs4281 *chip)
1418 {
1419 unsigned int tmp;
1420 unsigned long end_time;
1421 int retry_count = 2;
1422
1423 /* Having EPPMC.FPDN=1 prevent proper chip initialisation */
1424 tmp = snd_cs4281_peekBA0(chip, BA0_EPPMC);
1425 if (tmp & BA0_EPPMC_FPDN)
1426 snd_cs4281_pokeBA0(chip, BA0_EPPMC, tmp & ~BA0_EPPMC_FPDN);
1427
1428 __retry:
1429 tmp = snd_cs4281_peekBA0(chip, BA0_CFLR);
1430 if (tmp != BA0_CFLR_DEFAULT) {
1431 snd_cs4281_pokeBA0(chip, BA0_CFLR, BA0_CFLR_DEFAULT);
1432 tmp = snd_cs4281_peekBA0(chip, BA0_CFLR);
1433 if (tmp != BA0_CFLR_DEFAULT) {
1434 snd_printk(KERN_ERR "CFLR setup failed (0x%x)\n", tmp);
1435 return -EIO;
1436 }
1437 }
1438
1439 /* Set the 'Configuration Write Protect' register
1440 * to 4281h. Allows vendor-defined configuration
1441 * space between 0e4h and 0ffh to be written. */
1442 snd_cs4281_pokeBA0(chip, BA0_CWPR, 0x4281);
1443
1444 if ((tmp = snd_cs4281_peekBA0(chip, BA0_SERC1)) != (BA0_SERC1_SO1EN | BA0_SERC1_AC97)) {
1445 snd_printk(KERN_ERR "SERC1 AC'97 check failed (0x%x)\n", tmp);
1446 return -EIO;
1447 }
1448 if ((tmp = snd_cs4281_peekBA0(chip, BA0_SERC2)) != (BA0_SERC2_SI1EN | BA0_SERC2_AC97)) {
1449 snd_printk(KERN_ERR "SERC2 AC'97 check failed (0x%x)\n", tmp);
1450 return -EIO;
1451 }
1452
1453 /* Sound System Power Management */
1454 snd_cs4281_pokeBA0(chip, BA0_SSPM, BA0_SSPM_MIXEN | BA0_SSPM_CSRCEN |
1455 BA0_SSPM_PSRCEN | BA0_SSPM_JSEN |
1456 BA0_SSPM_ACLEN | BA0_SSPM_FMEN);
1457
1458 /* Serial Port Power Management */
1459 /* Blast the clock control register to zero so that the
1460 * PLL starts out in a known state, and blast the master serial
1461 * port control register to zero so that the serial ports also
1462 * start out in a known state. */
1463 snd_cs4281_pokeBA0(chip, BA0_CLKCR1, 0);
1464 snd_cs4281_pokeBA0(chip, BA0_SERMC, 0);
1465
1466 /* Make ESYN go to zero to turn off
1467 * the Sync pulse on the AC97 link. */
1468 snd_cs4281_pokeBA0(chip, BA0_ACCTL, 0);
1469 udelay(50);
1470
1471 /* Drive the ARST# pin low for a minimum of 1uS (as defined in the AC97
1472 * spec) and then drive it high. This is done for non AC97 modes since
1473 * there might be logic external to the CS4281 that uses the ARST# line
1474 * for a reset. */
1475 snd_cs4281_pokeBA0(chip, BA0_SPMC, 0);
1476 udelay(50);
1477 snd_cs4281_pokeBA0(chip, BA0_SPMC, BA0_SPMC_RSTN);
1478 msleep(50);
1479
1480 if (chip->dual_codec)
1481 snd_cs4281_pokeBA0(chip, BA0_SPMC, BA0_SPMC_RSTN | BA0_SPMC_ASDI2E);
1482
1483 /*
1484 * Set the serial port timing configuration.
1485 */
1486 snd_cs4281_pokeBA0(chip, BA0_SERMC,
1487 (chip->dual_codec ? BA0_SERMC_TCID(chip->dual_codec) : BA0_SERMC_TCID(1)) |
1488 BA0_SERMC_PTC_AC97 | BA0_SERMC_MSPE);
1489
1490 /*
1491 * Start the DLL Clock logic.
1492 */
1493 snd_cs4281_pokeBA0(chip, BA0_CLKCR1, BA0_CLKCR1_DLLP);
1494 msleep(50);
1495 snd_cs4281_pokeBA0(chip, BA0_CLKCR1, BA0_CLKCR1_SWCE | BA0_CLKCR1_DLLP);
1496
1497 /*
1498 * Wait for the DLL ready signal from the clock logic.
1499 */
1500 end_time = jiffies + HZ;
1501 do {
1502 /*
1503 * Read the AC97 status register to see if we've seen a CODEC
1504 * signal from the AC97 codec.
1505 */
1506 if (snd_cs4281_peekBA0(chip, BA0_CLKCR1) & BA0_CLKCR1_DLLRDY)
1507 goto __ok0;
1508 schedule_timeout_uninterruptible(1);
1509 } while (time_after_eq(end_time, jiffies));
1510
1511 snd_printk(KERN_ERR "DLLRDY not seen\n");
1512 return -EIO;
1513
1514 __ok0:
1515
1516 /*
1517 * The first thing we do here is to enable sync generation. As soon
1518 * as we start receiving bit clock, we'll start producing the SYNC
1519 * signal.
1520 */
1521 snd_cs4281_pokeBA0(chip, BA0_ACCTL, BA0_ACCTL_ESYN);
1522
1523 /*
1524 * Wait for the codec ready signal from the AC97 codec.
1525 */
1526 end_time = jiffies + HZ;
1527 do {
1528 /*
1529 * Read the AC97 status register to see if we've seen a CODEC
1530 * signal from the AC97 codec.
1531 */
1532 if (snd_cs4281_peekBA0(chip, BA0_ACSTS) & BA0_ACSTS_CRDY)
1533 goto __ok1;
1534 schedule_timeout_uninterruptible(1);
1535 } while (time_after_eq(end_time, jiffies));
1536
1537 snd_printk(KERN_ERR "never read codec ready from AC'97 (0x%x)\n", snd_cs4281_peekBA0(chip, BA0_ACSTS));
1538 return -EIO;
1539
1540 __ok1:
1541 if (chip->dual_codec) {
1542 end_time = jiffies + HZ;
1543 do {
1544 if (snd_cs4281_peekBA0(chip, BA0_ACSTS2) & BA0_ACSTS_CRDY)
1545 goto __codec2_ok;
1546 schedule_timeout_uninterruptible(1);
1547 } while (time_after_eq(end_time, jiffies));
1548 snd_printk(KERN_INFO "secondary codec doesn't respond. disable it...\n");
1549 chip->dual_codec = 0;
1550 __codec2_ok: ;
1551 }
1552
1553 /*
1554 * Assert the valid frame signal so that we can start sending commands
1555 * to the AC97 codec.
1556 */
1557
1558 snd_cs4281_pokeBA0(chip, BA0_ACCTL, BA0_ACCTL_VFRM | BA0_ACCTL_ESYN);
1559
1560 /*
1561 * Wait until we've sampled input slots 3 and 4 as valid, meaning that
1562 * the codec is pumping ADC data across the AC-link.
1563 */
1564
1565 end_time = jiffies + HZ;
1566 do {
1567 /*
1568 * Read the input slot valid register and see if input slots 3
1569 * 4 are valid yet.
1570 */
1571 if ((snd_cs4281_peekBA0(chip, BA0_ACISV) & (BA0_ACISV_SLV(3) | BA0_ACISV_SLV(4))) == (BA0_ACISV_SLV(3) | BA0_ACISV_SLV(4)))
1572 goto __ok2;
1573 schedule_timeout_uninterruptible(1);
1574 } while (time_after_eq(end_time, jiffies));
1575
1576 if (--retry_count > 0)
1577 goto __retry;
1578 snd_printk(KERN_ERR "never read ISV3 and ISV4 from AC'97\n");
1579 return -EIO;
1580
1581 __ok2:
1582
1583 /*
1584 * Now, assert valid frame and the slot 3 and 4 valid bits. This will
1585 * commense the transfer of digital audio data to the AC97 codec.
1586 */
1587 snd_cs4281_pokeBA0(chip, BA0_ACOSV, BA0_ACOSV_SLV(3) | BA0_ACOSV_SLV(4));
1588
1589 /*
1590 * Initialize DMA structures
1591 */
1592 for (tmp = 0; tmp < 4; tmp++) {
1593 struct cs4281_dma *dma = &chip->dma[tmp];
1594 dma->regDBA = BA0_DBA0 + (tmp * 0x10);
1595 dma->regDCA = BA0_DCA0 + (tmp * 0x10);
1596 dma->regDBC = BA0_DBC0 + (tmp * 0x10);
1597 dma->regDCC = BA0_DCC0 + (tmp * 0x10);
1598 dma->regDMR = BA0_DMR0 + (tmp * 8);
1599 dma->regDCR = BA0_DCR0 + (tmp * 8);
1600 dma->regHDSR = BA0_HDSR0 + (tmp * 4);
1601 dma->regFCR = BA0_FCR0 + (tmp * 4);
1602 dma->regFSIC = BA0_FSIC0 + (tmp * 4);
1603 dma->fifo_offset = tmp * CS4281_FIFO_SIZE;
1604 snd_cs4281_pokeBA0(chip, dma->regFCR,
1605 BA0_FCR_LS(31) |
1606 BA0_FCR_RS(31) |
1607 BA0_FCR_SZ(CS4281_FIFO_SIZE) |
1608 BA0_FCR_OF(dma->fifo_offset));
1609 }
1610
1611 chip->src_left_play_slot = 0; /* AC'97 left PCM playback (3) */
1612 chip->src_right_play_slot = 1; /* AC'97 right PCM playback (4) */
1613 chip->src_left_rec_slot = 10; /* AC'97 left PCM record (3) */
1614 chip->src_right_rec_slot = 11; /* AC'97 right PCM record (4) */
1615
1616 /* Activate wave playback FIFO for FM playback */
1617 chip->dma[0].valFCR = BA0_FCR_FEN | BA0_FCR_LS(0) |
1618 BA0_FCR_RS(1) |
1619 BA0_FCR_SZ(CS4281_FIFO_SIZE) |
1620 BA0_FCR_OF(chip->dma[0].fifo_offset);
1621 snd_cs4281_pokeBA0(chip, chip->dma[0].regFCR, chip->dma[0].valFCR);
1622 snd_cs4281_pokeBA0(chip, BA0_SRCSA, (chip->src_left_play_slot << 0) |
1623 (chip->src_right_play_slot << 8) |
1624 (chip->src_left_rec_slot << 16) |
1625 (chip->src_right_rec_slot << 24));
1626
1627 /* Initialize digital volume */
1628 snd_cs4281_pokeBA0(chip, BA0_PPLVC, 0);
1629 snd_cs4281_pokeBA0(chip, BA0_PPRVC, 0);
1630
1631 /* Enable IRQs */
1632 snd_cs4281_pokeBA0(chip, BA0_HICR, BA0_HICR_EOI);
1633 /* Unmask interrupts */
1634 snd_cs4281_pokeBA0(chip, BA0_HIMR, 0x7fffffff & ~(
1635 BA0_HISR_MIDI |
1636 BA0_HISR_DMAI |
1637 BA0_HISR_DMA(0) |
1638 BA0_HISR_DMA(1) |
1639 BA0_HISR_DMA(2) |
1640 BA0_HISR_DMA(3)));
1641 synchronize_irq(chip->irq);
1642
1643 return 0;
1644 }
1645
1646 /*
1647 * MIDI section
1648 */
1649
1650 static void snd_cs4281_midi_reset(struct cs4281 *chip)
1651 {
1652 snd_cs4281_pokeBA0(chip, BA0_MIDCR, chip->midcr | BA0_MIDCR_MRST);
1653 udelay(100);
1654 snd_cs4281_pokeBA0(chip, BA0_MIDCR, chip->midcr);
1655 }
1656
1657 static int snd_cs4281_midi_input_open(struct snd_rawmidi_substream *substream)
1658 {
1659 struct cs4281 *chip = substream->rmidi->private_data;
1660
1661 spin_lock_irq(&chip->reg_lock);
1662 chip->midcr |= BA0_MIDCR_RXE;
1663 chip->midi_input = substream;
1664 if (!(chip->uartm & CS4281_MODE_OUTPUT)) {
1665 snd_cs4281_midi_reset(chip);
1666 } else {
1667 snd_cs4281_pokeBA0(chip, BA0_MIDCR, chip->midcr);
1668 }
1669 spin_unlock_irq(&chip->reg_lock);
1670 return 0;
1671 }
1672
1673 static int snd_cs4281_midi_input_close(struct snd_rawmidi_substream *substream)
1674 {
1675 struct cs4281 *chip = substream->rmidi->private_data;
1676
1677 spin_lock_irq(&chip->reg_lock);
1678 chip->midcr &= ~(BA0_MIDCR_RXE | BA0_MIDCR_RIE);
1679 chip->midi_input = NULL;
1680 if (!(chip->uartm & CS4281_MODE_OUTPUT)) {
1681 snd_cs4281_midi_reset(chip);
1682 } else {
1683 snd_cs4281_pokeBA0(chip, BA0_MIDCR, chip->midcr);
1684 }
1685 chip->uartm &= ~CS4281_MODE_INPUT;
1686 spin_unlock_irq(&chip->reg_lock);
1687 return 0;
1688 }
1689
1690 static int snd_cs4281_midi_output_open(struct snd_rawmidi_substream *substream)
1691 {
1692 struct cs4281 *chip = substream->rmidi->private_data;
1693
1694 spin_lock_irq(&chip->reg_lock);
1695 chip->uartm |= CS4281_MODE_OUTPUT;
1696 chip->midcr |= BA0_MIDCR_TXE;
1697 chip->midi_output = substream;
1698 if (!(chip->uartm & CS4281_MODE_INPUT)) {
1699 snd_cs4281_midi_reset(chip);
1700 } else {
1701 snd_cs4281_pokeBA0(chip, BA0_MIDCR, chip->midcr);
1702 }
1703 spin_unlock_irq(&chip->reg_lock);
1704 return 0;
1705 }
1706
1707 static int snd_cs4281_midi_output_close(struct snd_rawmidi_substream *substream)
1708 {
1709 struct cs4281 *chip = substream->rmidi->private_data;
1710
1711 spin_lock_irq(&chip->reg_lock);
1712 chip->midcr &= ~(BA0_MIDCR_TXE | BA0_MIDCR_TIE);
1713 chip->midi_output = NULL;
1714 if (!(chip->uartm & CS4281_MODE_INPUT)) {
1715 snd_cs4281_midi_reset(chip);
1716 } else {
1717 snd_cs4281_pokeBA0(chip, BA0_MIDCR, chip->midcr);
1718 }
1719 chip->uartm &= ~CS4281_MODE_OUTPUT;
1720 spin_unlock_irq(&chip->reg_lock);
1721 return 0;
1722 }
1723
1724 static void snd_cs4281_midi_input_trigger(struct snd_rawmidi_substream *substream, int up)
1725 {
1726 unsigned long flags;
1727 struct cs4281 *chip = substream->rmidi->private_data;
1728
1729 spin_lock_irqsave(&chip->reg_lock, flags);
1730 if (up) {
1731 if ((chip->midcr & BA0_MIDCR_RIE) == 0) {
1732 chip->midcr |= BA0_MIDCR_RIE;
1733 snd_cs4281_pokeBA0(chip, BA0_MIDCR, chip->midcr);
1734 }
1735 } else {
1736 if (chip->midcr & BA0_MIDCR_RIE) {
1737 chip->midcr &= ~BA0_MIDCR_RIE;
1738 snd_cs4281_pokeBA0(chip, BA0_MIDCR, chip->midcr);
1739 }
1740 }
1741 spin_unlock_irqrestore(&chip->reg_lock, flags);
1742 }
1743
1744 static void snd_cs4281_midi_output_trigger(struct snd_rawmidi_substream *substream, int up)
1745 {
1746 unsigned long flags;
1747 struct cs4281 *chip = substream->rmidi->private_data;
1748 unsigned char byte;
1749
1750 spin_lock_irqsave(&chip->reg_lock, flags);
1751 if (up) {
1752 if ((chip->midcr & BA0_MIDCR_TIE) == 0) {
1753 chip->midcr |= BA0_MIDCR_TIE;
1754 /* fill UART FIFO buffer at first, and turn Tx interrupts only if necessary */
1755 while ((chip->midcr & BA0_MIDCR_TIE) &&
1756 (snd_cs4281_peekBA0(chip, BA0_MIDSR) & BA0_MIDSR_TBF) == 0) {
1757 if (snd_rawmidi_transmit(substream, &byte, 1) != 1) {
1758 chip->midcr &= ~BA0_MIDCR_TIE;
1759 } else {
1760 snd_cs4281_pokeBA0(chip, BA0_MIDWP, byte);
1761 }
1762 }
1763 snd_cs4281_pokeBA0(chip, BA0_MIDCR, chip->midcr);
1764 }
1765 } else {
1766 if (chip->midcr & BA0_MIDCR_TIE) {
1767 chip->midcr &= ~BA0_MIDCR_TIE;
1768 snd_cs4281_pokeBA0(chip, BA0_MIDCR, chip->midcr);
1769 }
1770 }
1771 spin_unlock_irqrestore(&chip->reg_lock, flags);
1772 }
1773
1774 static struct snd_rawmidi_ops snd_cs4281_midi_output =
1775 {
1776 .open = snd_cs4281_midi_output_open,
1777 .close = snd_cs4281_midi_output_close,
1778 .trigger = snd_cs4281_midi_output_trigger,
1779 };
1780
1781 static struct snd_rawmidi_ops snd_cs4281_midi_input =
1782 {
1783 .open = snd_cs4281_midi_input_open,
1784 .close = snd_cs4281_midi_input_close,
1785 .trigger = snd_cs4281_midi_input_trigger,
1786 };
1787
1788 static int __devinit snd_cs4281_midi(struct cs4281 * chip, int device,
1789 struct snd_rawmidi **rrawmidi)
1790 {
1791 struct snd_rawmidi *rmidi;
1792 int err;
1793
1794 if (rrawmidi)
1795 *rrawmidi = NULL;
1796 if ((err = snd_rawmidi_new(chip->card, "CS4281", device, 1, 1, &rmidi)) < 0)
1797 return err;
1798 strcpy(rmidi->name, "CS4281");
1799 snd_rawmidi_set_ops(rmidi, SNDRV_RAWMIDI_STREAM_OUTPUT, &snd_cs4281_midi_output);
1800 snd_rawmidi_set_ops(rmidi, SNDRV_RAWMIDI_STREAM_INPUT, &snd_cs4281_midi_input);
1801 rmidi->info_flags |= SNDRV_RAWMIDI_INFO_OUTPUT | SNDRV_RAWMIDI_INFO_INPUT | SNDRV_RAWMIDI_INFO_DUPLEX;
1802 rmidi->private_data = chip;
1803 chip->rmidi = rmidi;
1804 if (rrawmidi)
1805 *rrawmidi = rmidi;
1806 return 0;
1807 }
1808
1809 /*
1810 * Interrupt handler
1811 */
1812
1813 static irqreturn_t snd_cs4281_interrupt(int irq, void *dev_id)
1814 {
1815 struct cs4281 *chip = dev_id;
1816 unsigned int status, dma, val;
1817 struct cs4281_dma *cdma;
1818
1819 if (chip == NULL)
1820 return IRQ_NONE;
1821 status = snd_cs4281_peekBA0(chip, BA0_HISR);
1822 if ((status & 0x7fffffff) == 0) {
1823 snd_cs4281_pokeBA0(chip, BA0_HICR, BA0_HICR_EOI);
1824 return IRQ_NONE;
1825 }
1826
1827 if (status & (BA0_HISR_DMA(0)|BA0_HISR_DMA(1)|BA0_HISR_DMA(2)|BA0_HISR_DMA(3))) {
1828 for (dma = 0; dma < 4; dma++)
1829 if (status & BA0_HISR_DMA(dma)) {
1830 cdma = &chip->dma[dma];
1831 spin_lock(&chip->reg_lock);
1832 /* ack DMA IRQ */
1833 val = snd_cs4281_peekBA0(chip, cdma->regHDSR);
1834 /* workaround, sometimes CS4281 acknowledges */
1835 /* end or middle transfer position twice */
1836 cdma->frag++;
1837 if ((val & BA0_HDSR_DHTC) && !(cdma->frag & 1)) {
1838 cdma->frag--;
1839 chip->spurious_dhtc_irq++;
1840 spin_unlock(&chip->reg_lock);
1841 continue;
1842 }
1843 if ((val & BA0_HDSR_DTC) && (cdma->frag & 1)) {
1844 cdma->frag--;
1845 chip->spurious_dtc_irq++;
1846 spin_unlock(&chip->reg_lock);
1847 continue;
1848 }
1849 spin_unlock(&chip->reg_lock);
1850 snd_pcm_period_elapsed(cdma->substream);
1851 }
1852 }
1853
1854 if ((status & BA0_HISR_MIDI) && chip->rmidi) {
1855 unsigned char c;
1856
1857 spin_lock(&chip->reg_lock);
1858 while ((snd_cs4281_peekBA0(chip, BA0_MIDSR) & BA0_MIDSR_RBE) == 0) {
1859 c = snd_cs4281_peekBA0(chip, BA0_MIDRP);
1860 if ((chip->midcr & BA0_MIDCR_RIE) == 0)
1861 continue;
1862 snd_rawmidi_receive(chip->midi_input, &c, 1);
1863 }
1864 while ((snd_cs4281_peekBA0(chip, BA0_MIDSR) & BA0_MIDSR_TBF) == 0) {
1865 if ((chip->midcr & BA0_MIDCR_TIE) == 0)
1866 break;
1867 if (snd_rawmidi_transmit(chip->midi_output, &c, 1) != 1) {
1868 chip->midcr &= ~BA0_MIDCR_TIE;
1869 snd_cs4281_pokeBA0(chip, BA0_MIDCR, chip->midcr);
1870 break;
1871 }
1872 snd_cs4281_pokeBA0(chip, BA0_MIDWP, c);
1873 }
1874 spin_unlock(&chip->reg_lock);
1875 }
1876
1877 /* EOI to the PCI part... reenables interrupts */
1878 snd_cs4281_pokeBA0(chip, BA0_HICR, BA0_HICR_EOI);
1879
1880 return IRQ_HANDLED;
1881 }
1882
1883
1884 /*
1885 * OPL3 command
1886 */
1887 static void snd_cs4281_opl3_command(struct snd_opl3 *opl3, unsigned short cmd,
1888 unsigned char val)
1889 {
1890 unsigned long flags;
1891 struct cs4281 *chip = opl3->private_data;
1892 void __iomem *port;
1893
1894 if (cmd & OPL3_RIGHT)
1895 port = chip->ba0 + BA0_B1AP; /* right port */
1896 else
1897 port = chip->ba0 + BA0_B0AP; /* left port */
1898
1899 spin_lock_irqsave(&opl3->reg_lock, flags);
1900
1901 writel((unsigned int)cmd, port);
1902 udelay(10);
1903
1904 writel((unsigned int)val, port + 4);
1905 udelay(30);
1906
1907 spin_unlock_irqrestore(&opl3->reg_lock, flags);
1908 }
1909
1910 static int __devinit snd_cs4281_probe(struct pci_dev *pci,
1911 const struct pci_device_id *pci_id)
1912 {
1913 static int dev;
1914 struct snd_card *card;
1915 struct cs4281 *chip;
1916 struct snd_opl3 *opl3;
1917 int err;
1918
1919 if (dev >= SNDRV_CARDS)
1920 return -ENODEV;
1921 if (!enable[dev]) {
1922 dev++;
1923 return -ENOENT;
1924 }
1925
1926 card = snd_card_new(index[dev], id[dev], THIS_MODULE, 0);
1927 if (card == NULL)
1928 return -ENOMEM;
1929
1930 if ((err = snd_cs4281_create(card, pci, &chip, dual_codec[dev])) < 0) {
1931 snd_card_free(card);
1932 return err;
1933 }
1934 card->private_data = chip;
1935
1936 if ((err = snd_cs4281_mixer(chip)) < 0) {
1937 snd_card_free(card);
1938 return err;
1939 }
1940 if ((err = snd_cs4281_pcm(chip, 0, NULL)) < 0) {
1941 snd_card_free(card);
1942 return err;
1943 }
1944 if ((err = snd_cs4281_midi(chip, 0, NULL)) < 0) {
1945 snd_card_free(card);
1946 return err;
1947 }
1948 if ((err = snd_opl3_new(card, OPL3_HW_OPL3_CS4281, &opl3)) < 0) {
1949 snd_card_free(card);
1950 return err;
1951 }
1952 opl3->private_data = chip;
1953 opl3->command = snd_cs4281_opl3_command;
1954 snd_opl3_init(opl3);
1955 if ((err = snd_opl3_hwdep_new(opl3, 0, 1, NULL)) < 0) {
1956 snd_card_free(card);
1957 return err;
1958 }
1959 snd_cs4281_create_gameport(chip);
1960 strcpy(card->driver, "CS4281");
1961 strcpy(card->shortname, "Cirrus Logic CS4281");
1962 sprintf(card->longname, "%s at 0x%lx, irq %d",
1963 card->shortname,
1964 chip->ba0_addr,
1965 chip->irq);
1966
1967 if ((err = snd_card_register(card)) < 0) {
1968 snd_card_free(card);
1969 return err;
1970 }
1971
1972 pci_set_drvdata(pci, card);
1973 dev++;
1974 return 0;
1975 }
1976
1977 static void __devexit snd_cs4281_remove(struct pci_dev *pci)
1978 {
1979 snd_card_free(pci_get_drvdata(pci));
1980 pci_set_drvdata(pci, NULL);
1981 }
1982
1983 /*
1984 * Power Management
1985 */
1986 #ifdef CONFIG_PM
1987
1988 static int saved_regs[SUSPEND_REGISTERS] = {
1989 BA0_JSCTL,
1990 BA0_GPIOR,
1991 BA0_SSCR,
1992 BA0_MIDCR,
1993 BA0_SRCSA,
1994 BA0_PASR,
1995 BA0_CASR,
1996 BA0_DACSR,
1997 BA0_ADCSR,
1998 BA0_FMLVC,
1999 BA0_FMRVC,
2000 BA0_PPLVC,
2001 BA0_PPRVC,
2002 };
2003
2004 #define CLKCR1_CKRA 0x00010000L
2005
2006 static int cs4281_suspend(struct pci_dev *pci, pm_message_t state)
2007 {
2008 struct snd_card *card = pci_get_drvdata(pci);
2009 struct cs4281 *chip = card->private_data;
2010 u32 ulCLK;
2011 unsigned int i;
2012
2013 snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
2014 snd_pcm_suspend_all(chip->pcm);
2015
2016 snd_ac97_suspend(chip->ac97);
2017 snd_ac97_suspend(chip->ac97_secondary);
2018
2019 ulCLK = snd_cs4281_peekBA0(chip, BA0_CLKCR1);
2020 ulCLK |= CLKCR1_CKRA;
2021 snd_cs4281_pokeBA0(chip, BA0_CLKCR1, ulCLK);
2022
2023 /* Disable interrupts. */
2024 snd_cs4281_pokeBA0(chip, BA0_HICR, BA0_HICR_CHGM);
2025
2026 /* remember the status registers */
2027 for (i = 0; i < ARRAY_SIZE(saved_regs); i++)
2028 if (saved_regs[i])
2029 chip->suspend_regs[i] = snd_cs4281_peekBA0(chip, saved_regs[i]);
2030
2031 /* Turn off the serial ports. */
2032 snd_cs4281_pokeBA0(chip, BA0_SERMC, 0);
2033
2034 /* Power off FM, Joystick, AC link, */
2035 snd_cs4281_pokeBA0(chip, BA0_SSPM, 0);
2036
2037 /* DLL off. */
2038 snd_cs4281_pokeBA0(chip, BA0_CLKCR1, 0);
2039
2040 /* AC link off. */
2041 snd_cs4281_pokeBA0(chip, BA0_SPMC, 0);
2042
2043 ulCLK = snd_cs4281_peekBA0(chip, BA0_CLKCR1);
2044 ulCLK &= ~CLKCR1_CKRA;
2045 snd_cs4281_pokeBA0(chip, BA0_CLKCR1, ulCLK);
2046
2047 pci_disable_device(pci);
2048 pci_save_state(pci);
2049 pci_set_power_state(pci, pci_choose_state(pci, state));
2050 return 0;
2051 }
2052
2053 static int cs4281_resume(struct pci_dev *pci)
2054 {
2055 struct snd_card *card = pci_get_drvdata(pci);
2056 struct cs4281 *chip = card->private_data;
2057 unsigned int i;
2058 u32 ulCLK;
2059
2060 pci_set_power_state(pci, PCI_D0);
2061 pci_restore_state(pci);
2062 if (pci_enable_device(pci) < 0) {
2063 printk(KERN_ERR "cs4281: pci_enable_device failed, "
2064 "disabling device\n");
2065 snd_card_disconnect(card);
2066 return -EIO;
2067 }
2068 pci_set_master(pci);
2069
2070 ulCLK = snd_cs4281_peekBA0(chip, BA0_CLKCR1);
2071 ulCLK |= CLKCR1_CKRA;
2072 snd_cs4281_pokeBA0(chip, BA0_CLKCR1, ulCLK);
2073
2074 snd_cs4281_chip_init(chip);
2075
2076 /* restore the status registers */
2077 for (i = 0; i < ARRAY_SIZE(saved_regs); i++)
2078 if (saved_regs[i])
2079 snd_cs4281_pokeBA0(chip, saved_regs[i], chip->suspend_regs[i]);
2080
2081 snd_ac97_resume(chip->ac97);
2082 snd_ac97_resume(chip->ac97_secondary);
2083
2084 ulCLK = snd_cs4281_peekBA0(chip, BA0_CLKCR1);
2085 ulCLK &= ~CLKCR1_CKRA;
2086 snd_cs4281_pokeBA0(chip, BA0_CLKCR1, ulCLK);
2087
2088 snd_power_change_state(card, SNDRV_CTL_POWER_D0);
2089 return 0;
2090 }
2091 #endif /* CONFIG_PM */
2092
2093 static struct pci_driver driver = {
2094 .name = "CS4281",
2095 .id_table = snd_cs4281_ids,
2096 .probe = snd_cs4281_probe,
2097 .remove = __devexit_p(snd_cs4281_remove),
2098 #ifdef CONFIG_PM
2099 .suspend = cs4281_suspend,
2100 .resume = cs4281_resume,
2101 #endif
2102 };
2103
2104 static int __init alsa_card_cs4281_init(void)
2105 {
2106 return pci_register_driver(&driver);
2107 }
2108
2109 static void __exit alsa_card_cs4281_exit(void)
2110 {
2111 pci_unregister_driver(&driver);
2112 }
2113
2114 module_init(alsa_card_cs4281_init)
2115 module_exit(alsa_card_cs4281_exit)
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