Blackfin arch: fix building for BF542 processors which only have 1 TWI
[pv_ops_mirror.git] / include / asm-h8300 / cachectl.h
blobc464022d8e266e360c349ab2e7effb470f45fdea
1 #ifndef _H8300_CACHECTL_H
2 #define _H8300_CACHECTL_H
4 /* Definitions for the cacheflush system call. */
6 #define FLUSH_SCOPE_LINE 0 /* Flush a cache line */
7 #define FLUSH_SCOPE_PAGE 0 /* Flush a page */
8 #define FLUSH_SCOPE_ALL 0 /* Flush the whole cache -- superuser only */
10 #define FLUSH_CACHE_DATA 0 /* Writeback and flush data cache */
11 #define FLUSH_CACHE_INSN 0 /* Flush instruction cache */
12 #define FLUSH_CACHE_BOTH 0 /* Flush both caches */
14 #endif /* _H8300_CACHECTL_H */