Blackfin arch: fix building for BF542 processors which only have 1 TWI
[pv_ops_mirror.git] / include / asm-xtensa / sigcontext.h
blobe3381cee5059ae9946f3c53044c8fcac45276651
1 /*
2 * include/asm-xtensa/sigcontext.h
4 * This file is subject to the terms and conditions of the GNU General Public
5 * License. See the file "COPYING" in the main directory of this archive
6 * for more details.
8 * Copyright (C) 2001 - 2007 Tensilica Inc.
9 */
11 #ifndef _XTENSA_SIGCONTEXT_H
12 #define _XTENSA_SIGCONTEXT_H
15 struct sigcontext {
16 unsigned long oldmask;
18 /* CPU registers */
19 unsigned long sc_pc;
20 unsigned long sc_ps;
21 unsigned long sc_lbeg;
22 unsigned long sc_lend;
23 unsigned long sc_lcount;
24 unsigned long sc_sar;
25 unsigned long sc_acclo;
26 unsigned long sc_acchi;
27 unsigned long sc_a[16];
30 #endif /* _XTENSA_SIGCONTEXT_H */