include/linux/ssb/ssb_driver_pci.h

   1 #ifndef LINUX_SSB_PCICORE_H_
   2 #define LINUX_SSB_PCICORE_H_
   3
   4 #ifdef CONFIG_SSB_DRIVER_PCICORE
   5
   6 /* PCI core registers. */
   7 #define SSB_PCICORE_CTL                 0x0000  /* PCI Control */
   8 #define  SSB_PCICORE_CTL_RST_OE         0x00000001 /* PCI_RESET Output Enable */
   9 #define  SSB_PCICORE_CTL_RST            0x00000002 /* PCI_RESET driven out to pin */
  10 #define  SSB_PCICORE_CTL_CLK_OE         0x00000004 /* Clock gate Output Enable */
  11 #define  SSB_PCICORE_CTL_CLK            0x00000008 /* Gate for clock driven out to pin */
  12 #define SSB_PCICORE_ARBCTL              0x0010  /* PCI Arbiter Control */
  13 #define  SSB_PCICORE_ARBCTL_INTERN      0x00000001 /* Use internal arbiter */
  14 #define  SSB_PCICORE_ARBCTL_EXTERN      0x00000002 /* Use external arbiter */
  15 #define  SSB_PCICORE_ARBCTL_PARKID      0x00000006 /* Mask, selects which agent is parked on an idle bus */
  16 #define   SSB_PCICORE_ARBCTL_PARKID_LAST        0x00000000 /* Last requestor */
  17 #define   SSB_PCICORE_ARBCTL_PARKID_4710        0x00000002 /* 4710 */
  18 #define   SSB_PCICORE_ARBCTL_PARKID_EXT0        0x00000004 /* External requestor 0 */
  19 #define   SSB_PCICORE_ARBCTL_PARKID_EXT1        0x00000006 /* External requestor 1 */
  20 #define SSB_PCICORE_ISTAT               0x0020  /* Interrupt status */
  21 #define  SSB_PCICORE_ISTAT_INTA         0x00000001 /* PCI INTA# */
  22 #define  SSB_PCICORE_ISTAT_INTB         0x00000002 /* PCI INTB# */
  23 #define  SSB_PCICORE_ISTAT_SERR         0x00000004 /* PCI SERR# (write to clear) */
  24 #define  SSB_PCICORE_ISTAT_PERR         0x00000008 /* PCI PERR# (write to clear) */
  25 #define  SSB_PCICORE_ISTAT_PME          0x00000010 /* PCI PME# */
  26 #define SSB_PCICORE_IMASK               0x0024  /* Interrupt mask */
  27 #define  SSB_PCICORE_IMASK_INTA         0x00000001 /* PCI INTA# */
  28 #define  SSB_PCICORE_IMASK_INTB         0x00000002 /* PCI INTB# */
  29 #define  SSB_PCICORE_IMASK_SERR         0x00000004 /* PCI SERR# */
  30 #define  SSB_PCICORE_IMASK_PERR         0x00000008 /* PCI PERR# */
  31 #define  SSB_PCICORE_IMASK_PME          0x00000010 /* PCI PME# */
  32 #define SSB_PCICORE_MBOX                0x0028  /* Backplane to PCI Mailbox */
  33 #define  SSB_PCICORE_MBOX_F0_0          0x00000100 /* PCI function 0, INT 0 */
  34 #define  SSB_PCICORE_MBOX_F0_1          0x00000200 /* PCI function 0, INT 1 */
  35 #define  SSB_PCICORE_MBOX_F1_0          0x00000400 /* PCI function 1, INT 0 */
  36 #define  SSB_PCICORE_MBOX_F1_1          0x00000800 /* PCI function 1, INT 1 */
  37 #define  SSB_PCICORE_MBOX_F2_0          0x00001000 /* PCI function 2, INT 0 */
  38 #define  SSB_PCICORE_MBOX_F2_1          0x00002000 /* PCI function 2, INT 1 */
  39 #define  SSB_PCICORE_MBOX_F3_0          0x00004000 /* PCI function 3, INT 0 */
  40 #define  SSB_PCICORE_MBOX_F3_1          0x00008000 /* PCI function 3, INT 1 */
  41 #define SSB_PCICORE_BCAST_ADDR          0x0050  /* Backplane Broadcast Address */
  42 #define  SSB_PCICORE_BCAST_ADDR_MASK    0x000000FF
  43 #define SSB_PCICORE_BCAST_DATA          0x0054  /* Backplane Broadcast Data */
  44 #define SSB_PCICORE_GPIO_IN             0x0060  /* rev >= 2 only */
  45 #define SSB_PCICORE_GPIO_OUT            0x0064  /* rev >= 2 only */
  46 #define SSB_PCICORE_GPIO_ENABLE         0x0068  /* rev >= 2 only */
  47 #define SSB_PCICORE_GPIO_CTL            0x006C  /* rev >= 2 only */
  48 #define SSB_PCICORE_SBTOPCI0            0x0100  /* Backplane to PCI translation 0 (sbtopci0) */
  49 #define  SSB_PCICORE_SBTOPCI0_MASK      0xFC000000
  50 #define SSB_PCICORE_SBTOPCI1            0x0104  /* Backplane to PCI translation 1 (sbtopci1) */
  51 #define  SSB_PCICORE_SBTOPCI1_MASK      0xFC000000
  52 #define SSB_PCICORE_SBTOPCI2            0x0108  /* Backplane to PCI translation 2 (sbtopci2) */
  53 #define  SSB_PCICORE_SBTOPCI2_MASK      0xC0000000
  54
  55 /* SBtoPCIx */
  56 #define SSB_PCICORE_SBTOPCI_MEM         0x00000000
  57 #define SSB_PCICORE_SBTOPCI_IO          0x00000001
  58 #define SSB_PCICORE_SBTOPCI_CFG0        0x00000002
  59 #define SSB_PCICORE_SBTOPCI_CFG1        0x00000003
  60 #define SSB_PCICORE_SBTOPCI_PREF        0x00000004 /* Prefetch enable */
  61 #define SSB_PCICORE_SBTOPCI_BURST       0x00000008 /* Burst enable */
  62 #define SSB_PCICORE_SBTOPCI_MRM         0x00000020 /* Memory Read Multiple */
  63 #define SSB_PCICORE_SBTOPCI_RC          0x00000030 /* Read Command mask (rev >= 11) */
  64 #define  SSB_PCICORE_SBTOPCI_RC_READ    0x00000000 /* Memory read */
  65 #define  SSB_PCICORE_SBTOPCI_RC_READL   0x00000010 /* Memory read line */
  66 #define  SSB_PCICORE_SBTOPCI_RC_READM   0x00000020 /* Memory read multiple */
  67
  68
  69 /* PCIcore specific boardflags */
  70 #define SSB_PCICORE_BFL_NOPCI           0x00000400 /* Board leaves PCI floating */
  71
  72
  73 struct ssb_pcicore {
  74         struct ssb_device *dev;
  75         u8 setup_done:1;
  76         u8 hostmode:1;
  77         u8 cardbusmode:1;
  78 };
  79
  80 extern void ssb_pcicore_init(struct ssb_pcicore *pc);
  81
  82 /* Enable IRQ routing for a specific device */
  83 extern int ssb_pcicore_dev_irqvecs_enable(struct ssb_pcicore *pc,
  84                                           struct ssb_device *dev);
  85
  86
  87 #else /* CONFIG_SSB_DRIVER_PCICORE */
  88
  89
  90 struct ssb_pcicore {
  91 };
  92
  93 static inline
  94 void ssb_pcicore_init(struct ssb_pcicore *pc)
  95 {
  96 }
  97
  98 static inline
  99 int ssb_pcicore_dev_irqvecs_enable(struct ssb_pcicore *pc,
 100                                    struct ssb_device *dev)
 101 {
 102         return 0;
 103 }
 104
 105 #endif /* CONFIG_SSB_DRIVER_PCICORE */
 106 #endif /* LINUX_SSB_PCICORE_H_ */