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eCryptfs: increment extent_offset once per loop interation
[pv_ops_mirror.git] / drivers / kvm / lapic.c
blob238fcad3ceceee4fc32f8ebc2396ed455b4107ae
1
2 /*
3 * Local APIC virtualization
4 *
5 * Copyright (C) 2006 Qumranet, Inc.
6 * Copyright (C) 2007 Novell
7 * Copyright (C) 2007 Intel
8 *
9 * Authors:
10 * Dor Laor <dor.laor@qumranet.com>
11 * Gregory Haskins <ghaskins@novell.com>
12 * Yaozu (Eddie) Dong <eddie.dong@intel.com>
13 *
14 * Based on Xen 3.1 code, Copyright (c) 2004, Intel Corporation.
15 *
16 * This work is licensed under the terms of the GNU GPL, version 2. See
17 * the COPYING file in the top-level directory.
18 */
19
20 #include "kvm.h"
21 #include <linux/kvm.h>
22 #include <linux/mm.h>
23 #include <linux/highmem.h>
24 #include <linux/smp.h>
25 #include <linux/hrtimer.h>
26 #include <linux/io.h>
27 #include <linux/module.h>
28 #include <asm/processor.h>
29 #include <asm/msr.h>
30 #include <asm/page.h>
31 #include <asm/current.h>
32 #include <asm/apicdef.h>
33 #include <asm/atomic.h>
34 #include <asm/div64.h>
35 #include "irq.h"
36
37 #define PRId64 "d"
38 #define PRIx64 "llx"
39 #define PRIu64 "u"
40 #define PRIo64 "o"
41
42 #define APIC_BUS_CYCLE_NS 1
43
44 /* #define apic_debug(fmt,arg...) printk(KERN_WARNING fmt,##arg) */
45 #define apic_debug(fmt, arg...)
46
47 #define APIC_LVT_NUM 6
48 /* 14 is the version for Xeon and Pentium 8.4.8*/
49 #define APIC_VERSION (0x14UL | ((APIC_LVT_NUM - 1) << 16))
50 #define LAPIC_MMIO_LENGTH (1 << 12)
51 /* followed define is not in apicdef.h */
52 #define APIC_SHORT_MASK 0xc0000
53 #define APIC_DEST_NOSHORT 0x0
54 #define APIC_DEST_MASK 0x800
55 #define MAX_APIC_VECTOR 256
56
57 #define VEC_POS(v) ((v) & (32 - 1))
58 #define REG_POS(v) (((v) >> 5) << 4)
59 static inline u32 apic_get_reg(struct kvm_lapic *apic, int reg_off)
60 {
61 return *((u32 *) (apic->regs + reg_off));
62 }
63
64 static inline void apic_set_reg(struct kvm_lapic *apic, int reg_off, u32 val)
65 {
66 *((u32 *) (apic->regs + reg_off)) = val;
67 }
68
69 static inline int apic_test_and_set_vector(int vec, void *bitmap)
70 {
71 return test_and_set_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
72 }
73
74 static inline int apic_test_and_clear_vector(int vec, void *bitmap)
75 {
76 return test_and_clear_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
77 }
78
79 static inline void apic_set_vector(int vec, void *bitmap)
80 {
81 set_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
82 }
83
84 static inline void apic_clear_vector(int vec, void *bitmap)
85 {
86 clear_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
87 }
88
89 static inline int apic_hw_enabled(struct kvm_lapic *apic)
90 {
91 return (apic)->vcpu->apic_base & MSR_IA32_APICBASE_ENABLE;
92 }
93
94 static inline int apic_sw_enabled(struct kvm_lapic *apic)
95 {
96 return apic_get_reg(apic, APIC_SPIV) & APIC_SPIV_APIC_ENABLED;
97 }
98
99 static inline int apic_enabled(struct kvm_lapic *apic)
100 {
101 return apic_sw_enabled(apic) && apic_hw_enabled(apic);
102 }
103
104 #define LVT_MASK \
105 (APIC_LVT_MASKED | APIC_SEND_PENDING | APIC_VECTOR_MASK)
106
107 #define LINT_MASK \
108 (LVT_MASK | APIC_MODE_MASK | APIC_INPUT_POLARITY | \
109 APIC_LVT_REMOTE_IRR | APIC_LVT_LEVEL_TRIGGER)
110
111 static inline int kvm_apic_id(struct kvm_lapic *apic)
112 {
113 return (apic_get_reg(apic, APIC_ID) >> 24) & 0xff;
114 }
115
116 static inline int apic_lvt_enabled(struct kvm_lapic *apic, int lvt_type)
117 {
118 return !(apic_get_reg(apic, lvt_type) & APIC_LVT_MASKED);
119 }
120
121 static inline int apic_lvt_vector(struct kvm_lapic *apic, int lvt_type)
122 {
123 return apic_get_reg(apic, lvt_type) & APIC_VECTOR_MASK;
124 }
125
126 static inline int apic_lvtt_period(struct kvm_lapic *apic)
127 {
128 return apic_get_reg(apic, APIC_LVTT) & APIC_LVT_TIMER_PERIODIC;
129 }
130
131 static unsigned int apic_lvt_mask[APIC_LVT_NUM] = {
132 LVT_MASK | APIC_LVT_TIMER_PERIODIC, /* LVTT */
133 LVT_MASK | APIC_MODE_MASK, /* LVTTHMR */
134 LVT_MASK | APIC_MODE_MASK, /* LVTPC */
135 LINT_MASK, LINT_MASK, /* LVT0-1 */
136 LVT_MASK /* LVTERR */
137 };
138
139 static int find_highest_vector(void *bitmap)
140 {
141 u32 *word = bitmap;
142 int word_offset = MAX_APIC_VECTOR >> 5;
143
144 while ((word_offset != 0) && (word[(--word_offset) << 2] == 0))
145 continue;
146
147 if (likely(!word_offset && !word[0]))
148 return -1;
149 else
150 return fls(word[word_offset << 2]) - 1 + (word_offset << 5);
151 }
152
153 static inline int apic_test_and_set_irr(int vec, struct kvm_lapic *apic)
154 {
155 return apic_test_and_set_vector(vec, apic->regs + APIC_IRR);
156 }
157
158 static inline void apic_clear_irr(int vec, struct kvm_lapic *apic)
159 {
160 apic_clear_vector(vec, apic->regs + APIC_IRR);
161 }
162
163 static inline int apic_find_highest_irr(struct kvm_lapic *apic)
164 {
165 int result;
166
167 result = find_highest_vector(apic->regs + APIC_IRR);
168 ASSERT(result == -1 || result >= 16);
169
170 return result;
171 }
172
173 int kvm_lapic_find_highest_irr(struct kvm_vcpu *vcpu)
174 {
175 struct kvm_lapic *apic = (struct kvm_lapic *)vcpu->apic;
176 int highest_irr;
177
178 if (!apic)
179 return 0;
180 highest_irr = apic_find_highest_irr(apic);
181
182 return highest_irr;
183 }
184 EXPORT_SYMBOL_GPL(kvm_lapic_find_highest_irr);
185
186 int kvm_apic_set_irq(struct kvm_lapic *apic, u8 vec, u8 trig)
187 {
188 if (!apic_test_and_set_irr(vec, apic)) {
189 /* a new pending irq is set in IRR */
190 if (trig)
191 apic_set_vector(vec, apic->regs + APIC_TMR);
192 else
193 apic_clear_vector(vec, apic->regs + APIC_TMR);
194 kvm_vcpu_kick(apic->vcpu);
195 return 1;
196 }
197 return 0;
198 }
199
200 static inline int apic_find_highest_isr(struct kvm_lapic *apic)
201 {
202 int result;
203
204 result = find_highest_vector(apic->regs + APIC_ISR);
205 ASSERT(result == -1 || result >= 16);
206
207 return result;
208 }
209
210 static void apic_update_ppr(struct kvm_lapic *apic)
211 {
212 u32 tpr, isrv, ppr;
213 int isr;
214
215 tpr = apic_get_reg(apic, APIC_TASKPRI);
216 isr = apic_find_highest_isr(apic);
217 isrv = (isr != -1) ? isr : 0;
218
219 if ((tpr & 0xf0) >= (isrv & 0xf0))
220 ppr = tpr & 0xff;
221 else
222 ppr = isrv & 0xf0;
223
224 apic_debug("vlapic %p, ppr 0x%x, isr 0x%x, isrv 0x%x",
225 apic, ppr, isr, isrv);
226
227 apic_set_reg(apic, APIC_PROCPRI, ppr);
228 }
229
230 static void apic_set_tpr(struct kvm_lapic *apic, u32 tpr)
231 {
232 apic_set_reg(apic, APIC_TASKPRI, tpr);
233 apic_update_ppr(apic);
234 }
235
236 int kvm_apic_match_physical_addr(struct kvm_lapic *apic, u16 dest)
237 {
238 return kvm_apic_id(apic) == dest;
239 }
240
241 int kvm_apic_match_logical_addr(struct kvm_lapic *apic, u8 mda)
242 {
243 int result = 0;
244 u8 logical_id;
245
246 logical_id = GET_APIC_LOGICAL_ID(apic_get_reg(apic, APIC_LDR));
247
248 switch (apic_get_reg(apic, APIC_DFR)) {
249 case APIC_DFR_FLAT:
250 if (logical_id & mda)
251 result = 1;
252 break;
253 case APIC_DFR_CLUSTER:
254 if (((logical_id >> 4) == (mda >> 0x4))
255 && (logical_id & mda & 0xf))
256 result = 1;
257 break;
258 default:
259 printk(KERN_WARNING "Bad DFR vcpu %d: %08x\n",
260 apic->vcpu->vcpu_id, apic_get_reg(apic, APIC_DFR));
261 break;
262 }
263
264 return result;
265 }
266
267 static int apic_match_dest(struct kvm_vcpu *vcpu, struct kvm_lapic *source,
268 int short_hand, int dest, int dest_mode)
269 {
270 int result = 0;
271 struct kvm_lapic *target = vcpu->apic;
272
273 apic_debug("target %p, source %p, dest 0x%x, "
274 "dest_mode 0x%x, short_hand 0x%x",
275 target, source, dest, dest_mode, short_hand);
276
277 ASSERT(!target);
278 switch (short_hand) {
279 case APIC_DEST_NOSHORT:
280 if (dest_mode == 0) {
281 /* Physical mode. */
282 if ((dest == 0xFF) || (dest == kvm_apic_id(target)))
283 result = 1;
284 } else
285 /* Logical mode. */
286 result = kvm_apic_match_logical_addr(target, dest);
287 break;
288 case APIC_DEST_SELF:
289 if (target == source)
290 result = 1;
291 break;
292 case APIC_DEST_ALLINC:
293 result = 1;
294 break;
295 case APIC_DEST_ALLBUT:
296 if (target != source)
297 result = 1;
298 break;
299 default:
300 printk(KERN_WARNING "Bad dest shorthand value %x\n",
301 short_hand);
302 break;
303 }
304
305 return result;
306 }
307
308 /*
309 * Add a pending IRQ into lapic.
310 * Return 1 if successfully added and 0 if discarded.
311 */
312 static int __apic_accept_irq(struct kvm_lapic *apic, int delivery_mode,
313 int vector, int level, int trig_mode)
314 {
315 int orig_irr, result = 0;
316 struct kvm_vcpu *vcpu = apic->vcpu;
317
318 switch (delivery_mode) {
319 case APIC_DM_FIXED:
320 case APIC_DM_LOWEST:
321 /* FIXME add logic for vcpu on reset */
322 if (unlikely(!apic_enabled(apic)))
323 break;
324
325 orig_irr = apic_test_and_set_irr(vector, apic);
326 if (orig_irr && trig_mode) {
327 apic_debug("level trig mode repeatedly for vector %d",
328 vector);
329 break;
330 }
331
332 if (trig_mode) {
333 apic_debug("level trig mode for vector %d", vector);
334 apic_set_vector(vector, apic->regs + APIC_TMR);
335 } else
336 apic_clear_vector(vector, apic->regs + APIC_TMR);
337
338 if (vcpu->mp_state == VCPU_MP_STATE_RUNNABLE)
339 kvm_vcpu_kick(vcpu);
340 else if (vcpu->mp_state == VCPU_MP_STATE_HALTED) {
341 vcpu->mp_state = VCPU_MP_STATE_RUNNABLE;
342 if (waitqueue_active(&vcpu->wq))
343 wake_up_interruptible(&vcpu->wq);
344 }
345
346 result = (orig_irr == 0);
347 break;
348
349 case APIC_DM_REMRD:
350 printk(KERN_DEBUG "Ignoring delivery mode 3\n");
351 break;
352
353 case APIC_DM_SMI:
354 printk(KERN_DEBUG "Ignoring guest SMI\n");
355 break;
356 case APIC_DM_NMI:
357 printk(KERN_DEBUG "Ignoring guest NMI\n");
358 break;
359
360 case APIC_DM_INIT:
361 if (level) {
362 if (vcpu->mp_state == VCPU_MP_STATE_RUNNABLE)
363 printk(KERN_DEBUG
364 "INIT on a runnable vcpu %d\n",
365 vcpu->vcpu_id);
366 vcpu->mp_state = VCPU_MP_STATE_INIT_RECEIVED;
367 kvm_vcpu_kick(vcpu);
368 } else {
369 printk(KERN_DEBUG
370 "Ignoring de-assert INIT to vcpu %d\n",
371 vcpu->vcpu_id);
372 }
373
374 break;
375
376 case APIC_DM_STARTUP:
377 printk(KERN_DEBUG "SIPI to vcpu %d vector 0x%02x\n",
378 vcpu->vcpu_id, vector);
379 if (vcpu->mp_state == VCPU_MP_STATE_INIT_RECEIVED) {
380 vcpu->sipi_vector = vector;
381 vcpu->mp_state = VCPU_MP_STATE_SIPI_RECEIVED;
382 if (waitqueue_active(&vcpu->wq))
383 wake_up_interruptible(&vcpu->wq);
384 }
385 break;
386
387 default:
388 printk(KERN_ERR "TODO: unsupported delivery mode %x\n",
389 delivery_mode);
390 break;
391 }
392 return result;
393 }
394
395 struct kvm_lapic *kvm_apic_round_robin(struct kvm *kvm, u8 vector,
396 unsigned long bitmap)
397 {
398 int vcpu_id;
399 int last;
400 int next;
401 struct kvm_lapic *apic;
402
403 last = kvm->round_robin_prev_vcpu;
404 next = last;
405
406 do {
407 if (++next == KVM_MAX_VCPUS)
408 next = 0;
409 if (kvm->vcpus[next] == NULL || !test_bit(next, &bitmap))
410 continue;
411 apic = kvm->vcpus[next]->apic;
412 if (apic && apic_enabled(apic))
413 break;
414 apic = NULL;
415 } while (next != last);
416 kvm->round_robin_prev_vcpu = next;
417
418 if (!apic) {
419 vcpu_id = ffs(bitmap) - 1;
420 if (vcpu_id < 0) {
421 vcpu_id = 0;
422 printk(KERN_DEBUG "vcpu not ready for apic_round_robin\n");
423 }
424 apic = kvm->vcpus[vcpu_id]->apic;
425 }
426
427 return apic;
428 }
429
430 static void apic_set_eoi(struct kvm_lapic *apic)
431 {
432 int vector = apic_find_highest_isr(apic);
433
434 /*
435 * Not every write EOI will has corresponding ISR,
436 * one example is when Kernel check timer on setup_IO_APIC
437 */
438 if (vector == -1)
439 return;
440
441 apic_clear_vector(vector, apic->regs + APIC_ISR);
442 apic_update_ppr(apic);
443
444 if (apic_test_and_clear_vector(vector, apic->regs + APIC_TMR))
445 kvm_ioapic_update_eoi(apic->vcpu->kvm, vector);
446 }
447
448 static void apic_send_ipi(struct kvm_lapic *apic)
449 {
450 u32 icr_low = apic_get_reg(apic, APIC_ICR);
451 u32 icr_high = apic_get_reg(apic, APIC_ICR2);
452
453 unsigned int dest = GET_APIC_DEST_FIELD(icr_high);
454 unsigned int short_hand = icr_low & APIC_SHORT_MASK;
455 unsigned int trig_mode = icr_low & APIC_INT_LEVELTRIG;
456 unsigned int level = icr_low & APIC_INT_ASSERT;
457 unsigned int dest_mode = icr_low & APIC_DEST_MASK;
458 unsigned int delivery_mode = icr_low & APIC_MODE_MASK;
459 unsigned int vector = icr_low & APIC_VECTOR_MASK;
460
461 struct kvm_lapic *target;
462 struct kvm_vcpu *vcpu;
463 unsigned long lpr_map = 0;
464 int i;
465
466 apic_debug("icr_high 0x%x, icr_low 0x%x, "
467 "short_hand 0x%x, dest 0x%x, trig_mode 0x%x, level 0x%x, "
468 "dest_mode 0x%x, delivery_mode 0x%x, vector 0x%x\n",
469 icr_high, icr_low, short_hand, dest,
470 trig_mode, level, dest_mode, delivery_mode, vector);
471
472 for (i = 0; i < KVM_MAX_VCPUS; i++) {
473 vcpu = apic->vcpu->kvm->vcpus[i];
474 if (!vcpu)
475 continue;
476
477 if (vcpu->apic &&
478 apic_match_dest(vcpu, apic, short_hand, dest, dest_mode)) {
479 if (delivery_mode == APIC_DM_LOWEST)
480 set_bit(vcpu->vcpu_id, &lpr_map);
481 else
482 __apic_accept_irq(vcpu->apic, delivery_mode,
483 vector, level, trig_mode);
484 }
485 }
486
487 if (delivery_mode == APIC_DM_LOWEST) {
488 target = kvm_apic_round_robin(vcpu->kvm, vector, lpr_map);
489 if (target != NULL)
490 __apic_accept_irq(target, delivery_mode,
491 vector, level, trig_mode);
492 }
493 }
494
495 static u32 apic_get_tmcct(struct kvm_lapic *apic)
496 {
497 u64 counter_passed;
498 ktime_t passed, now;
499 u32 tmcct;
500
501 ASSERT(apic != NULL);
502
503 now = apic->timer.dev.base->get_time();
504 tmcct = apic_get_reg(apic, APIC_TMICT);
505
506 /* if initial count is 0, current count should also be 0 */
507 if (tmcct == 0)
508 return 0;
509
510 if (unlikely(ktime_to_ns(now) <=
511 ktime_to_ns(apic->timer.last_update))) {
512 /* Wrap around */
513 passed = ktime_add(( {
514 (ktime_t) {
515 .tv64 = KTIME_MAX -
516 (apic->timer.last_update).tv64}; }
517 ), now);
518 apic_debug("time elapsed\n");
519 } else
520 passed = ktime_sub(now, apic->timer.last_update);
521
522 counter_passed = div64_64(ktime_to_ns(passed),
523 (APIC_BUS_CYCLE_NS * apic->timer.divide_count));
524
525 if (counter_passed > tmcct) {
526 if (unlikely(!apic_lvtt_period(apic))) {
527 /* one-shot timers stick at 0 until reset */
528 tmcct = 0;
529 } else {
530 /*
531 * periodic timers reset to APIC_TMICT when they
532 * hit 0. The while loop simulates this happening N
533 * times. (counter_passed %= tmcct) would also work,
534 * but might be slower or not work on 32-bit??
535 */
536 while (counter_passed > tmcct)
537 counter_passed -= tmcct;
538 tmcct -= counter_passed;
539 }
540 } else {
541 tmcct -= counter_passed;
542 }
543
544 return tmcct;
545 }
546
547 static u32 __apic_read(struct kvm_lapic *apic, unsigned int offset)
548 {
549 u32 val = 0;
550
551 if (offset >= LAPIC_MMIO_LENGTH)
552 return 0;
553
554 switch (offset) {
555 case APIC_ARBPRI:
556 printk(KERN_WARNING "Access APIC ARBPRI register "
557 "which is for P6\n");
558 break;
559
560 case APIC_TMCCT: /* Timer CCR */
561 val = apic_get_tmcct(apic);
562 break;
563
564 default:
565 apic_update_ppr(apic);
566 val = apic_get_reg(apic, offset);
567 break;
568 }
569
570 return val;
571 }
572
573 static void apic_mmio_read(struct kvm_io_device *this,
574 gpa_t address, int len, void *data)
575 {
576 struct kvm_lapic *apic = (struct kvm_lapic *)this->private;
577 unsigned int offset = address - apic->base_address;
578 unsigned char alignment = offset & 0xf;
579 u32 result;
580
581 if ((alignment + len) > 4) {
582 printk(KERN_ERR "KVM_APIC_READ: alignment error %lx %d",
583 (unsigned long)address, len);
584 return;
585 }
586 result = __apic_read(apic, offset & ~0xf);
587
588 switch (len) {
589 case 1:
590 case 2:
591 case 4:
592 memcpy(data, (char *)&result + alignment, len);
593 break;
594 default:
595 printk(KERN_ERR "Local APIC read with len = %x, "
596 "should be 1,2, or 4 instead\n", len);
597 break;
598 }
599 }
600
601 static void update_divide_count(struct kvm_lapic *apic)
602 {
603 u32 tmp1, tmp2, tdcr;
604
605 tdcr = apic_get_reg(apic, APIC_TDCR);
606 tmp1 = tdcr & 0xf;
607 tmp2 = ((tmp1 & 0x3) | ((tmp1 & 0x8) >> 1)) + 1;
608 apic->timer.divide_count = 0x1 << (tmp2 & 0x7);
609
610 apic_debug("timer divide count is 0x%x\n",
611 apic->timer.divide_count);
612 }
613
614 static void start_apic_timer(struct kvm_lapic *apic)
615 {
616 ktime_t now = apic->timer.dev.base->get_time();
617
618 apic->timer.last_update = now;
619
620 apic->timer.period = apic_get_reg(apic, APIC_TMICT) *
621 APIC_BUS_CYCLE_NS * apic->timer.divide_count;
622 atomic_set(&apic->timer.pending, 0);
623 hrtimer_start(&apic->timer.dev,
624 ktime_add_ns(now, apic->timer.period),
625 HRTIMER_MODE_ABS);
626
627 apic_debug("%s: bus cycle is %" PRId64 "ns, now 0x%016"
628 PRIx64 ", "
629 "timer initial count 0x%x, period %lldns, "
630 "expire @ 0x%016" PRIx64 ".\n", __FUNCTION__,
631 APIC_BUS_CYCLE_NS, ktime_to_ns(now),
632 apic_get_reg(apic, APIC_TMICT),
633 apic->timer.period,
634 ktime_to_ns(ktime_add_ns(now,
635 apic->timer.period)));
636 }
637
638 static void apic_mmio_write(struct kvm_io_device *this,
639 gpa_t address, int len, const void *data)
640 {
641 struct kvm_lapic *apic = (struct kvm_lapic *)this->private;
642 unsigned int offset = address - apic->base_address;
643 unsigned char alignment = offset & 0xf;
644 u32 val;
645
646 /*
647 * APIC register must be aligned on 128-bits boundary.
648 * 32/64/128 bits registers must be accessed thru 32 bits.
649 * Refer SDM 8.4.1
650 */
651 if (len != 4 || alignment) {
652 if (printk_ratelimit())
653 printk(KERN_ERR "apic write: bad size=%d %lx\n",
654 len, (long)address);
655 return;
656 }
657
658 val = *(u32 *) data;
659
660 /* too common printing */
661 if (offset != APIC_EOI)
662 apic_debug("%s: offset 0x%x with length 0x%x, and value is "
663 "0x%x\n", __FUNCTION__, offset, len, val);
664
665 offset &= 0xff0;
666
667 switch (offset) {
668 case APIC_ID: /* Local APIC ID */
669 apic_set_reg(apic, APIC_ID, val);
670 break;
671
672 case APIC_TASKPRI:
673 apic_set_tpr(apic, val & 0xff);
674 break;
675
676 case APIC_EOI:
677 apic_set_eoi(apic);
678 break;
679
680 case APIC_LDR:
681 apic_set_reg(apic, APIC_LDR, val & APIC_LDR_MASK);
682 break;
683
684 case APIC_DFR:
685 apic_set_reg(apic, APIC_DFR, val | 0x0FFFFFFF);
686 break;
687
688 case APIC_SPIV:
689 apic_set_reg(apic, APIC_SPIV, val & 0x3ff);
690 if (!(val & APIC_SPIV_APIC_ENABLED)) {
691 int i;
692 u32 lvt_val;
693
694 for (i = 0; i < APIC_LVT_NUM; i++) {
695 lvt_val = apic_get_reg(apic,
696 APIC_LVTT + 0x10 * i);
697 apic_set_reg(apic, APIC_LVTT + 0x10 * i,
698 lvt_val | APIC_LVT_MASKED);
699 }
700 atomic_set(&apic->timer.pending, 0);
701
702 }
703 break;
704
705 case APIC_ICR:
706 /* No delay here, so we always clear the pending bit */
707 apic_set_reg(apic, APIC_ICR, val & ~(1 << 12));
708 apic_send_ipi(apic);
709 break;
710
711 case APIC_ICR2:
712 apic_set_reg(apic, APIC_ICR2, val & 0xff000000);
713 break;
714
715 case APIC_LVTT:
716 case APIC_LVTTHMR:
717 case APIC_LVTPC:
718 case APIC_LVT0:
719 case APIC_LVT1:
720 case APIC_LVTERR:
721 /* TODO: Check vector */
722 if (!apic_sw_enabled(apic))
723 val |= APIC_LVT_MASKED;
724
725 val &= apic_lvt_mask[(offset - APIC_LVTT) >> 4];
726 apic_set_reg(apic, offset, val);
727
728 break;
729
730 case APIC_TMICT:
731 hrtimer_cancel(&apic->timer.dev);
732 apic_set_reg(apic, APIC_TMICT, val);
733 start_apic_timer(apic);
734 return;
735
736 case APIC_TDCR:
737 if (val & 4)
738 printk(KERN_ERR "KVM_WRITE:TDCR %x\n", val);
739 apic_set_reg(apic, APIC_TDCR, val);
740 update_divide_count(apic);
741 break;
742
743 default:
744 apic_debug("Local APIC Write to read-only register %x\n",
745 offset);
746 break;
747 }
748
749 }
750
751 static int apic_mmio_range(struct kvm_io_device *this, gpa_t addr)
752 {
753 struct kvm_lapic *apic = (struct kvm_lapic *)this->private;
754 int ret = 0;
755
756
757 if (apic_hw_enabled(apic) &&
758 (addr >= apic->base_address) &&
759 (addr < (apic->base_address + LAPIC_MMIO_LENGTH)))
760 ret = 1;
761
762 return ret;
763 }
764
765 void kvm_free_apic(struct kvm_lapic *apic)
766 {
767 if (!apic)
768 return;
769
770 hrtimer_cancel(&apic->timer.dev);
771
772 if (apic->regs_page) {
773 __free_page(apic->regs_page);
774 apic->regs_page = 0;
775 }
776
777 kfree(apic);
778 }
779
780 /*
781 *----------------------------------------------------------------------
782 * LAPIC interface
783 *----------------------------------------------------------------------
784 */
785
786 void kvm_lapic_set_tpr(struct kvm_vcpu *vcpu, unsigned long cr8)
787 {
788 struct kvm_lapic *apic = (struct kvm_lapic *)vcpu->apic;
789
790 if (!apic)
791 return;
792 apic_set_tpr(apic, ((cr8 & 0x0f) << 4));
793 }
794
795 u64 kvm_lapic_get_cr8(struct kvm_vcpu *vcpu)
796 {
797 struct kvm_lapic *apic = (struct kvm_lapic *)vcpu->apic;
798 u64 tpr;
799
800 if (!apic)
801 return 0;
802 tpr = (u64) apic_get_reg(apic, APIC_TASKPRI);
803
804 return (tpr & 0xf0) >> 4;
805 }
806 EXPORT_SYMBOL_GPL(kvm_lapic_get_cr8);
807
808 void kvm_lapic_set_base(struct kvm_vcpu *vcpu, u64 value)
809 {
810 struct kvm_lapic *apic = (struct kvm_lapic *)vcpu->apic;
811
812 if (!apic) {
813 value |= MSR_IA32_APICBASE_BSP;
814 vcpu->apic_base = value;
815 return;
816 }
817 if (apic->vcpu->vcpu_id)
818 value &= ~MSR_IA32_APICBASE_BSP;
819
820 vcpu->apic_base = value;
821 apic->base_address = apic->vcpu->apic_base &
822 MSR_IA32_APICBASE_BASE;
823
824 /* with FSB delivery interrupt, we can restart APIC functionality */
825 apic_debug("apic base msr is 0x%016" PRIx64 ", and base address is "
826 "0x%lx.\n", apic->apic_base, apic->base_address);
827
828 }
829
830 u64 kvm_lapic_get_base(struct kvm_vcpu *vcpu)
831 {
832 return vcpu->apic_base;
833 }
834 EXPORT_SYMBOL_GPL(kvm_lapic_get_base);
835
836 void kvm_lapic_reset(struct kvm_vcpu *vcpu)
837 {
838 struct kvm_lapic *apic;
839 int i;
840
841 apic_debug("%s\n", __FUNCTION__);
842
843 ASSERT(vcpu);
844 apic = vcpu->apic;
845 ASSERT(apic != NULL);
846
847 /* Stop the timer in case it's a reset to an active apic */
848 hrtimer_cancel(&apic->timer.dev);
849
850 apic_set_reg(apic, APIC_ID, vcpu->vcpu_id << 24);
851 apic_set_reg(apic, APIC_LVR, APIC_VERSION);
852
853 for (i = 0; i < APIC_LVT_NUM; i++)
854 apic_set_reg(apic, APIC_LVTT + 0x10 * i, APIC_LVT_MASKED);
855 apic_set_reg(apic, APIC_LVT0,
856 SET_APIC_DELIVERY_MODE(0, APIC_MODE_EXTINT));
857
858 apic_set_reg(apic, APIC_DFR, 0xffffffffU);
859 apic_set_reg(apic, APIC_SPIV, 0xff);
860 apic_set_reg(apic, APIC_TASKPRI, 0);
861 apic_set_reg(apic, APIC_LDR, 0);
862 apic_set_reg(apic, APIC_ESR, 0);
863 apic_set_reg(apic, APIC_ICR, 0);
864 apic_set_reg(apic, APIC_ICR2, 0);
865 apic_set_reg(apic, APIC_TDCR, 0);
866 apic_set_reg(apic, APIC_TMICT, 0);
867 for (i = 0; i < 8; i++) {
868 apic_set_reg(apic, APIC_IRR + 0x10 * i, 0);
869 apic_set_reg(apic, APIC_ISR + 0x10 * i, 0);
870 apic_set_reg(apic, APIC_TMR + 0x10 * i, 0);
871 }
872 update_divide_count(apic);
873 atomic_set(&apic->timer.pending, 0);
874 if (vcpu->vcpu_id == 0)
875 vcpu->apic_base |= MSR_IA32_APICBASE_BSP;
876 apic_update_ppr(apic);
877
878 apic_debug(KERN_INFO "%s: vcpu=%p, id=%d, base_msr="
879 "0x%016" PRIx64 ", base_address=0x%0lx.\n", __FUNCTION__,
880 vcpu, kvm_apic_id(apic),
881 vcpu->apic_base, apic->base_address);
882 }
883 EXPORT_SYMBOL_GPL(kvm_lapic_reset);
884
885 int kvm_lapic_enabled(struct kvm_vcpu *vcpu)
886 {
887 struct kvm_lapic *apic = (struct kvm_lapic *)vcpu->apic;
888 int ret = 0;
889
890 if (!apic)
891 return 0;
892 ret = apic_enabled(apic);
893
894 return ret;
895 }
896 EXPORT_SYMBOL_GPL(kvm_lapic_enabled);
897
898 /*
899 *----------------------------------------------------------------------
900 * timer interface
901 *----------------------------------------------------------------------
902 */
903
904 /* TODO: make sure __apic_timer_fn runs in current pCPU */
905 static int __apic_timer_fn(struct kvm_lapic *apic)
906 {
907 int result = 0;
908 wait_queue_head_t *q = &apic->vcpu->wq;
909
910 atomic_inc(&apic->timer.pending);
911 if (waitqueue_active(q))
912 {
913 apic->vcpu->mp_state = VCPU_MP_STATE_RUNNABLE;
914 wake_up_interruptible(q);
915 }
916 if (apic_lvtt_period(apic)) {
917 result = 1;
918 apic->timer.dev.expires = ktime_add_ns(
919 apic->timer.dev.expires,
920 apic->timer.period);
921 }
922 return result;
923 }
924
925 static int __inject_apic_timer_irq(struct kvm_lapic *apic)
926 {
927 int vector;
928
929 vector = apic_lvt_vector(apic, APIC_LVTT);
930 return __apic_accept_irq(apic, APIC_DM_FIXED, vector, 1, 0);
931 }
932
933 static enum hrtimer_restart apic_timer_fn(struct hrtimer *data)
934 {
935 struct kvm_lapic *apic;
936 int restart_timer = 0;
937
938 apic = container_of(data, struct kvm_lapic, timer.dev);
939
940 restart_timer = __apic_timer_fn(apic);
941
942 if (restart_timer)
943 return HRTIMER_RESTART;
944 else
945 return HRTIMER_NORESTART;
946 }
947
948 int kvm_create_lapic(struct kvm_vcpu *vcpu)
949 {
950 struct kvm_lapic *apic;
951
952 ASSERT(vcpu != NULL);
953 apic_debug("apic_init %d\n", vcpu->vcpu_id);
954
955 apic = kzalloc(sizeof(*apic), GFP_KERNEL);
956 if (!apic)
957 goto nomem;
958
959 vcpu->apic = apic;
960
961 apic->regs_page = alloc_page(GFP_KERNEL);
962 if (apic->regs_page == NULL) {
963 printk(KERN_ERR "malloc apic regs error for vcpu %x\n",
964 vcpu->vcpu_id);
965 goto nomem;
966 }
967 apic->regs = page_address(apic->regs_page);
968 memset(apic->regs, 0, PAGE_SIZE);
969 apic->vcpu = vcpu;
970
971 hrtimer_init(&apic->timer.dev, CLOCK_MONOTONIC, HRTIMER_MODE_ABS);
972 apic->timer.dev.function = apic_timer_fn;
973 apic->base_address = APIC_DEFAULT_PHYS_BASE;
974 vcpu->apic_base = APIC_DEFAULT_PHYS_BASE;
975
976 kvm_lapic_reset(vcpu);
977 apic->dev.read = apic_mmio_read;
978 apic->dev.write = apic_mmio_write;
979 apic->dev.in_range = apic_mmio_range;
980 apic->dev.private = apic;
981
982 return 0;
983 nomem:
984 kvm_free_apic(apic);
985 return -ENOMEM;
986 }
987 EXPORT_SYMBOL_GPL(kvm_create_lapic);
988
989 int kvm_apic_has_interrupt(struct kvm_vcpu *vcpu)
990 {
991 struct kvm_lapic *apic = vcpu->apic;
992 int highest_irr;
993
994 if (!apic || !apic_enabled(apic))
995 return -1;
996
997 apic_update_ppr(apic);
998 highest_irr = apic_find_highest_irr(apic);
999 if ((highest_irr == -1) ||
1000 ((highest_irr & 0xF0) <= apic_get_reg(apic, APIC_PROCPRI)))
1001 return -1;
1002 return highest_irr;
1003 }
1004
1005 int kvm_apic_accept_pic_intr(struct kvm_vcpu *vcpu)
1006 {
1007 u32 lvt0 = apic_get_reg(vcpu->apic, APIC_LVT0);
1008 int r = 0;
1009
1010 if (vcpu->vcpu_id == 0) {
1011 if (!apic_hw_enabled(vcpu->apic))
1012 r = 1;
1013 if ((lvt0 & APIC_LVT_MASKED) == 0 &&
1014 GET_APIC_DELIVERY_MODE(lvt0) == APIC_MODE_EXTINT)
1015 r = 1;
1016 }
1017 return r;
1018 }
1019
1020 void kvm_inject_apic_timer_irqs(struct kvm_vcpu *vcpu)
1021 {
1022 struct kvm_lapic *apic = vcpu->apic;
1023
1024 if (apic && apic_lvt_enabled(apic, APIC_LVTT) &&
1025 atomic_read(&apic->timer.pending) > 0) {
1026 if (__inject_apic_timer_irq(apic))
1027 atomic_dec(&apic->timer.pending);
1028 }
1029 }
1030
1031 void kvm_apic_timer_intr_post(struct kvm_vcpu *vcpu, int vec)
1032 {
1033 struct kvm_lapic *apic = vcpu->apic;
1034
1035 if (apic && apic_lvt_vector(apic, APIC_LVTT) == vec)
1036 apic->timer.last_update = ktime_add_ns(
1037 apic->timer.last_update,
1038 apic->timer.period);
1039 }
1040
1041 int kvm_get_apic_interrupt(struct kvm_vcpu *vcpu)
1042 {
1043 int vector = kvm_apic_has_interrupt(vcpu);
1044 struct kvm_lapic *apic = vcpu->apic;
1045
1046 if (vector == -1)
1047 return -1;
1048
1049 apic_set_vector(vector, apic->regs + APIC_ISR);
1050 apic_update_ppr(apic);
1051 apic_clear_irr(vector, apic);
1052 return vector;
1053 }
1054
1055 void kvm_apic_post_state_restore(struct kvm_vcpu *vcpu)
1056 {
1057 struct kvm_lapic *apic = vcpu->apic;
1058
1059 apic->base_address = vcpu->apic_base &
1060 MSR_IA32_APICBASE_BASE;
1061 apic_set_reg(apic, APIC_LVR, APIC_VERSION);
1062 apic_update_ppr(apic);
1063 hrtimer_cancel(&apic->timer.dev);
1064 update_divide_count(apic);
1065 start_apic_timer(apic);
1066 }
1067
1068 void kvm_migrate_apic_timer(struct kvm_vcpu *vcpu)
1069 {
1070 struct kvm_lapic *apic = vcpu->apic;
1071 struct hrtimer *timer;
1072
1073 if (!apic)
1074 return;
1075
1076 timer = &apic->timer.dev;
1077 if (hrtimer_cancel(timer))
1078 hrtimer_start(timer, timer->expires, HRTIMER_MODE_ABS);
1079 }
1080 EXPORT_SYMBOL_GPL(kvm_migrate_apic_timer);
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