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eCryptfs: increment extent_offset once per loop interation
[pv_ops_mirror.git] / drivers / kvm / x86_emulate.c
bloba6ace302e0cd454f1f413306013b0920305e4a67
1 /******************************************************************************
2 * x86_emulate.c
3 *
4 * Generic x86 (32-bit and 64-bit) instruction decoder and emulator.
5 *
6 * Copyright (c) 2005 Keir Fraser
7 *
8 * Linux coding style, mod r/m decoder, segment base fixes, real-mode
9 * privileged instructions:
10 *
11 * Copyright (C) 2006 Qumranet
12 *
13 * Avi Kivity <avi@qumranet.com>
14 * Yaniv Kamay <yaniv@qumranet.com>
15 *
16 * This work is licensed under the terms of the GNU GPL, version 2. See
17 * the COPYING file in the top-level directory.
18 *
19 * From: xen-unstable 10676:af9809f51f81a3c43f276f00c81a52ef558afda4
20 */
21
22 #ifndef __KERNEL__
23 #include <stdio.h>
24 #include <stdint.h>
25 #include <public/xen.h>
26 #define DPRINTF(_f, _a ...) printf( _f , ## _a )
27 #else
28 #include "kvm.h"
29 #define DPRINTF(x...) do {} while (0)
30 #endif
31 #include "x86_emulate.h"
32 #include <linux/module.h>
33
34 /*
35 * Opcode effective-address decode tables.
36 * Note that we only emulate instructions that have at least one memory
37 * operand (excluding implicit stack references). We assume that stack
38 * references and instruction fetches will never occur in special memory
39 * areas that require emulation. So, for example, 'mov <imm>,<reg>' need
40 * not be handled.
41 */
42
43 /* Operand sizes: 8-bit operands or specified/overridden size. */
44 #define ByteOp (1<<0) /* 8-bit operands. */
45 /* Destination operand type. */
46 #define ImplicitOps (1<<1) /* Implicit in opcode. No generic decode. */
47 #define DstReg (2<<1) /* Register operand. */
48 #define DstMem (3<<1) /* Memory operand. */
49 #define DstMask (3<<1)
50 /* Source operand type. */
51 #define SrcNone (0<<3) /* No source operand. */
52 #define SrcImplicit (0<<3) /* Source operand is implicit in the opcode. */
53 #define SrcReg (1<<3) /* Register operand. */
54 #define SrcMem (2<<3) /* Memory operand. */
55 #define SrcMem16 (3<<3) /* Memory operand (16-bit). */
56 #define SrcMem32 (4<<3) /* Memory operand (32-bit). */
57 #define SrcImm (5<<3) /* Immediate operand. */
58 #define SrcImmByte (6<<3) /* 8-bit sign-extended immediate operand. */
59 #define SrcMask (7<<3)
60 /* Generic ModRM decode. */
61 #define ModRM (1<<6)
62 /* Destination is only written; never read. */
63 #define Mov (1<<7)
64 #define BitOp (1<<8)
65
66 static u8 opcode_table[256] = {
67 /* 0x00 - 0x07 */
68 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
69 ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM,
70 0, 0, 0, 0,
71 /* 0x08 - 0x0F */
72 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
73 ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM,
74 0, 0, 0, 0,
75 /* 0x10 - 0x17 */
76 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
77 ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM,
78 0, 0, 0, 0,
79 /* 0x18 - 0x1F */
80 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
81 ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM,
82 0, 0, 0, 0,
83 /* 0x20 - 0x27 */
84 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
85 ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM,
86 SrcImmByte, SrcImm, 0, 0,
87 /* 0x28 - 0x2F */
88 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
89 ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM,
90 0, 0, 0, 0,
91 /* 0x30 - 0x37 */
92 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
93 ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM,
94 0, 0, 0, 0,
95 /* 0x38 - 0x3F */
96 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
97 ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM,
98 0, 0, 0, 0,
99 /* 0x40 - 0x4F */
100 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
101 /* 0x50 - 0x57 */
102 ImplicitOps, ImplicitOps, ImplicitOps, ImplicitOps,
103 ImplicitOps, ImplicitOps, ImplicitOps, ImplicitOps,
104 /* 0x58 - 0x5F */
105 ImplicitOps, ImplicitOps, ImplicitOps, ImplicitOps,
106 ImplicitOps, ImplicitOps, ImplicitOps, ImplicitOps,
107 /* 0x60 - 0x67 */
108 0, 0, 0, DstReg | SrcMem32 | ModRM | Mov /* movsxd (x86/64) */ ,
109 0, 0, 0, 0,
110 /* 0x68 - 0x6F */
111 0, 0, ImplicitOps|Mov, 0,
112 SrcNone | ByteOp | ImplicitOps, SrcNone | ImplicitOps, /* insb, insw/insd */
113 SrcNone | ByteOp | ImplicitOps, SrcNone | ImplicitOps, /* outsb, outsw/outsd */
114 /* 0x70 - 0x77 */
115 ImplicitOps, ImplicitOps, ImplicitOps, ImplicitOps,
116 ImplicitOps, ImplicitOps, ImplicitOps, ImplicitOps,
117 /* 0x78 - 0x7F */
118 ImplicitOps, ImplicitOps, ImplicitOps, ImplicitOps,
119 ImplicitOps, ImplicitOps, ImplicitOps, ImplicitOps,
120 /* 0x80 - 0x87 */
121 ByteOp | DstMem | SrcImm | ModRM, DstMem | SrcImm | ModRM,
122 ByteOp | DstMem | SrcImm | ModRM, DstMem | SrcImmByte | ModRM,
123 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
124 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
125 /* 0x88 - 0x8F */
126 ByteOp | DstMem | SrcReg | ModRM | Mov, DstMem | SrcReg | ModRM | Mov,
127 ByteOp | DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
128 0, ModRM | DstReg, 0, DstMem | SrcNone | ModRM | Mov,
129 /* 0x90 - 0x9F */
130 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ImplicitOps, ImplicitOps, 0, 0,
131 /* 0xA0 - 0xA7 */
132 ByteOp | DstReg | SrcMem | Mov, DstReg | SrcMem | Mov,
133 ByteOp | DstMem | SrcReg | Mov, DstMem | SrcReg | Mov,
134 ByteOp | ImplicitOps | Mov, ImplicitOps | Mov,
135 ByteOp | ImplicitOps, ImplicitOps,
136 /* 0xA8 - 0xAF */
137 0, 0, ByteOp | ImplicitOps | Mov, ImplicitOps | Mov,
138 ByteOp | ImplicitOps | Mov, ImplicitOps | Mov,
139 ByteOp | ImplicitOps, ImplicitOps,
140 /* 0xB0 - 0xBF */
141 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
142 /* 0xC0 - 0xC7 */
143 ByteOp | DstMem | SrcImm | ModRM, DstMem | SrcImmByte | ModRM,
144 0, ImplicitOps, 0, 0,
145 ByteOp | DstMem | SrcImm | ModRM | Mov, DstMem | SrcImm | ModRM | Mov,
146 /* 0xC8 - 0xCF */
147 0, 0, 0, 0, 0, 0, 0, 0,
148 /* 0xD0 - 0xD7 */
149 ByteOp | DstMem | SrcImplicit | ModRM, DstMem | SrcImplicit | ModRM,
150 ByteOp | DstMem | SrcImplicit | ModRM, DstMem | SrcImplicit | ModRM,
151 0, 0, 0, 0,
152 /* 0xD8 - 0xDF */
153 0, 0, 0, 0, 0, 0, 0, 0,
154 /* 0xE0 - 0xE7 */
155 0, 0, 0, 0, 0, 0, 0, 0,
156 /* 0xE8 - 0xEF */
157 ImplicitOps, SrcImm|ImplicitOps, 0, SrcImmByte|ImplicitOps, 0, 0, 0, 0,
158 /* 0xF0 - 0xF7 */
159 0, 0, 0, 0,
160 ImplicitOps, 0,
161 ByteOp | DstMem | SrcNone | ModRM, DstMem | SrcNone | ModRM,
162 /* 0xF8 - 0xFF */
163 0, 0, 0, 0,
164 0, 0, ByteOp | DstMem | SrcNone | ModRM, DstMem | SrcNone | ModRM
165 };
166
167 static u16 twobyte_table[256] = {
168 /* 0x00 - 0x0F */
169 0, SrcMem | ModRM | DstReg, 0, 0, 0, 0, ImplicitOps, 0,
170 0, ImplicitOps, 0, 0, 0, ImplicitOps | ModRM, 0, 0,
171 /* 0x10 - 0x1F */
172 0, 0, 0, 0, 0, 0, 0, 0, ImplicitOps | ModRM, 0, 0, 0, 0, 0, 0, 0,
173 /* 0x20 - 0x2F */
174 ModRM | ImplicitOps, ModRM, ModRM | ImplicitOps, ModRM, 0, 0, 0, 0,
175 0, 0, 0, 0, 0, 0, 0, 0,
176 /* 0x30 - 0x3F */
177 ImplicitOps, 0, ImplicitOps, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
178 /* 0x40 - 0x47 */
179 DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
180 DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
181 DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
182 DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
183 /* 0x48 - 0x4F */
184 DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
185 DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
186 DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
187 DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
188 /* 0x50 - 0x5F */
189 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
190 /* 0x60 - 0x6F */
191 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
192 /* 0x70 - 0x7F */
193 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
194 /* 0x80 - 0x8F */
195 ImplicitOps, ImplicitOps, ImplicitOps, ImplicitOps,
196 ImplicitOps, ImplicitOps, ImplicitOps, ImplicitOps,
197 ImplicitOps, ImplicitOps, ImplicitOps, ImplicitOps,
198 ImplicitOps, ImplicitOps, ImplicitOps, ImplicitOps,
199 /* 0x90 - 0x9F */
200 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
201 /* 0xA0 - 0xA7 */
202 0, 0, 0, DstMem | SrcReg | ModRM | BitOp, 0, 0, 0, 0,
203 /* 0xA8 - 0xAF */
204 0, 0, 0, DstMem | SrcReg | ModRM | BitOp, 0, 0, 0, 0,
205 /* 0xB0 - 0xB7 */
206 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM, 0,
207 DstMem | SrcReg | ModRM | BitOp,
208 0, 0, ByteOp | DstReg | SrcMem | ModRM | Mov,
209 DstReg | SrcMem16 | ModRM | Mov,
210 /* 0xB8 - 0xBF */
211 0, 0, DstMem | SrcImmByte | ModRM, DstMem | SrcReg | ModRM | BitOp,
212 0, 0, ByteOp | DstReg | SrcMem | ModRM | Mov,
213 DstReg | SrcMem16 | ModRM | Mov,
214 /* 0xC0 - 0xCF */
215 0, 0, 0, DstMem | SrcReg | ModRM | Mov, 0, 0, 0, ImplicitOps | ModRM,
216 0, 0, 0, 0, 0, 0, 0, 0,
217 /* 0xD0 - 0xDF */
218 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
219 /* 0xE0 - 0xEF */
220 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
221 /* 0xF0 - 0xFF */
222 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
223 };
224
225 /* Type, address-of, and value of an instruction's operand. */
226 struct operand {
227 enum { OP_REG, OP_MEM, OP_IMM } type;
228 unsigned int bytes;
229 unsigned long val, orig_val, *ptr;
230 };
231
232 /* EFLAGS bit definitions. */
233 #define EFLG_OF (1<<11)
234 #define EFLG_DF (1<<10)
235 #define EFLG_SF (1<<7)
236 #define EFLG_ZF (1<<6)
237 #define EFLG_AF (1<<4)
238 #define EFLG_PF (1<<2)
239 #define EFLG_CF (1<<0)
240
241 /*
242 * Instruction emulation:
243 * Most instructions are emulated directly via a fragment of inline assembly
244 * code. This allows us to save/restore EFLAGS and thus very easily pick up
245 * any modified flags.
246 */
247
248 #if defined(CONFIG_X86_64)
249 #define _LO32 "k" /* force 32-bit operand */
250 #define _STK "%%rsp" /* stack pointer */
251 #elif defined(__i386__)
252 #define _LO32 "" /* force 32-bit operand */
253 #define _STK "%%esp" /* stack pointer */
254 #endif
255
256 /*
257 * These EFLAGS bits are restored from saved value during emulation, and
258 * any changes are written back to the saved value after emulation.
259 */
260 #define EFLAGS_MASK (EFLG_OF|EFLG_SF|EFLG_ZF|EFLG_AF|EFLG_PF|EFLG_CF)
261
262 /* Before executing instruction: restore necessary bits in EFLAGS. */
263 #define _PRE_EFLAGS(_sav, _msk, _tmp) \
264 /* EFLAGS = (_sav & _msk) | (EFLAGS & ~_msk); */ \
265 "push %"_sav"; " \
266 "movl %"_msk",%"_LO32 _tmp"; " \
267 "andl %"_LO32 _tmp",("_STK"); " \
268 "pushf; " \
269 "notl %"_LO32 _tmp"; " \
270 "andl %"_LO32 _tmp",("_STK"); " \
271 "pop %"_tmp"; " \
272 "orl %"_LO32 _tmp",("_STK"); " \
273 "popf; " \
274 /* _sav &= ~msk; */ \
275 "movl %"_msk",%"_LO32 _tmp"; " \
276 "notl %"_LO32 _tmp"; " \
277 "andl %"_LO32 _tmp",%"_sav"; "
278
279 /* After executing instruction: write-back necessary bits in EFLAGS. */
280 #define _POST_EFLAGS(_sav, _msk, _tmp) \
281 /* _sav |= EFLAGS & _msk; */ \
282 "pushf; " \
283 "pop %"_tmp"; " \
284 "andl %"_msk",%"_LO32 _tmp"; " \
285 "orl %"_LO32 _tmp",%"_sav"; "
286
287 /* Raw emulation: instruction has two explicit operands. */
288 #define __emulate_2op_nobyte(_op,_src,_dst,_eflags,_wx,_wy,_lx,_ly,_qx,_qy) \
289 do { \
290 unsigned long _tmp; \
291 \
292 switch ((_dst).bytes) { \
293 case 2: \
294 __asm__ __volatile__ ( \
295 _PRE_EFLAGS("0","4","2") \
296 _op"w %"_wx"3,%1; " \
297 _POST_EFLAGS("0","4","2") \
298 : "=m" (_eflags), "=m" ((_dst).val), \
299 "=&r" (_tmp) \
300 : _wy ((_src).val), "i" (EFLAGS_MASK) ); \
301 break; \
302 case 4: \
303 __asm__ __volatile__ ( \
304 _PRE_EFLAGS("0","4","2") \
305 _op"l %"_lx"3,%1; " \
306 _POST_EFLAGS("0","4","2") \
307 : "=m" (_eflags), "=m" ((_dst).val), \
308 "=&r" (_tmp) \
309 : _ly ((_src).val), "i" (EFLAGS_MASK) ); \
310 break; \
311 case 8: \
312 __emulate_2op_8byte(_op, _src, _dst, \
313 _eflags, _qx, _qy); \
314 break; \
315 } \
316 } while (0)
317
318 #define __emulate_2op(_op,_src,_dst,_eflags,_bx,_by,_wx,_wy,_lx,_ly,_qx,_qy) \
319 do { \
320 unsigned long _tmp; \
321 switch ( (_dst).bytes ) \
322 { \
323 case 1: \
324 __asm__ __volatile__ ( \
325 _PRE_EFLAGS("0","4","2") \
326 _op"b %"_bx"3,%1; " \
327 _POST_EFLAGS("0","4","2") \
328 : "=m" (_eflags), "=m" ((_dst).val), \
329 "=&r" (_tmp) \
330 : _by ((_src).val), "i" (EFLAGS_MASK) ); \
331 break; \
332 default: \
333 __emulate_2op_nobyte(_op, _src, _dst, _eflags, \
334 _wx, _wy, _lx, _ly, _qx, _qy); \
335 break; \
336 } \
337 } while (0)
338
339 /* Source operand is byte-sized and may be restricted to just %cl. */
340 #define emulate_2op_SrcB(_op, _src, _dst, _eflags) \
341 __emulate_2op(_op, _src, _dst, _eflags, \
342 "b", "c", "b", "c", "b", "c", "b", "c")
343
344 /* Source operand is byte, word, long or quad sized. */
345 #define emulate_2op_SrcV(_op, _src, _dst, _eflags) \
346 __emulate_2op(_op, _src, _dst, _eflags, \
347 "b", "q", "w", "r", _LO32, "r", "", "r")
348
349 /* Source operand is word, long or quad sized. */
350 #define emulate_2op_SrcV_nobyte(_op, _src, _dst, _eflags) \
351 __emulate_2op_nobyte(_op, _src, _dst, _eflags, \
352 "w", "r", _LO32, "r", "", "r")
353
354 /* Instruction has only one explicit operand (no source operand). */
355 #define emulate_1op(_op, _dst, _eflags) \
356 do { \
357 unsigned long _tmp; \
358 \
359 switch ( (_dst).bytes ) \
360 { \
361 case 1: \
362 __asm__ __volatile__ ( \
363 _PRE_EFLAGS("0","3","2") \
364 _op"b %1; " \
365 _POST_EFLAGS("0","3","2") \
366 : "=m" (_eflags), "=m" ((_dst).val), \
367 "=&r" (_tmp) \
368 : "i" (EFLAGS_MASK) ); \
369 break; \
370 case 2: \
371 __asm__ __volatile__ ( \
372 _PRE_EFLAGS("0","3","2") \
373 _op"w %1; " \
374 _POST_EFLAGS("0","3","2") \
375 : "=m" (_eflags), "=m" ((_dst).val), \
376 "=&r" (_tmp) \
377 : "i" (EFLAGS_MASK) ); \
378 break; \
379 case 4: \
380 __asm__ __volatile__ ( \
381 _PRE_EFLAGS("0","3","2") \
382 _op"l %1; " \
383 _POST_EFLAGS("0","3","2") \
384 : "=m" (_eflags), "=m" ((_dst).val), \
385 "=&r" (_tmp) \
386 : "i" (EFLAGS_MASK) ); \
387 break; \
388 case 8: \
389 __emulate_1op_8byte(_op, _dst, _eflags); \
390 break; \
391 } \
392 } while (0)
393
394 /* Emulate an instruction with quadword operands (x86/64 only). */
395 #if defined(CONFIG_X86_64)
396 #define __emulate_2op_8byte(_op, _src, _dst, _eflags, _qx, _qy) \
397 do { \
398 __asm__ __volatile__ ( \
399 _PRE_EFLAGS("0","4","2") \
400 _op"q %"_qx"3,%1; " \
401 _POST_EFLAGS("0","4","2") \
402 : "=m" (_eflags), "=m" ((_dst).val), "=&r" (_tmp) \
403 : _qy ((_src).val), "i" (EFLAGS_MASK) ); \
404 } while (0)
405
406 #define __emulate_1op_8byte(_op, _dst, _eflags) \
407 do { \
408 __asm__ __volatile__ ( \
409 _PRE_EFLAGS("0","3","2") \
410 _op"q %1; " \
411 _POST_EFLAGS("0","3","2") \
412 : "=m" (_eflags), "=m" ((_dst).val), "=&r" (_tmp) \
413 : "i" (EFLAGS_MASK) ); \
414 } while (0)
415
416 #elif defined(__i386__)
417 #define __emulate_2op_8byte(_op, _src, _dst, _eflags, _qx, _qy)
418 #define __emulate_1op_8byte(_op, _dst, _eflags)
419 #endif /* __i386__ */
420
421 /* Fetch next part of the instruction being emulated. */
422 #define insn_fetch(_type, _size, _eip) \
423 ({ unsigned long _x; \
424 rc = ops->read_std((unsigned long)(_eip) + ctxt->cs_base, &_x, \
425 (_size), ctxt->vcpu); \
426 if ( rc != 0 ) \
427 goto done; \
428 (_eip) += (_size); \
429 (_type)_x; \
430 })
431
432 /* Access/update address held in a register, based on addressing mode. */
433 #define address_mask(reg) \
434 ((ad_bytes == sizeof(unsigned long)) ? \
435 (reg) : ((reg) & ((1UL << (ad_bytes << 3)) - 1)))
436 #define register_address(base, reg) \
437 ((base) + address_mask(reg))
438 #define register_address_increment(reg, inc) \
439 do { \
440 /* signed type ensures sign extension to long */ \
441 int _inc = (inc); \
442 if ( ad_bytes == sizeof(unsigned long) ) \
443 (reg) += _inc; \
444 else \
445 (reg) = ((reg) & ~((1UL << (ad_bytes << 3)) - 1)) | \
446 (((reg) + _inc) & ((1UL << (ad_bytes << 3)) - 1)); \
447 } while (0)
448
449 #define JMP_REL(rel) \
450 do { \
451 _eip += (int)(rel); \
452 _eip = ((op_bytes == 2) ? (uint16_t)_eip : (uint32_t)_eip); \
453 } while (0)
454
455 /*
456 * Given the 'reg' portion of a ModRM byte, and a register block, return a
457 * pointer into the block that addresses the relevant register.
458 * @highbyte_regs specifies whether to decode AH,CH,DH,BH.
459 */
460 static void *decode_register(u8 modrm_reg, unsigned long *regs,
461 int highbyte_regs)
462 {
463 void *p;
464
465 p = &regs[modrm_reg];
466 if (highbyte_regs && modrm_reg >= 4 && modrm_reg < 8)
467 p = (unsigned char *)&regs[modrm_reg & 3] + 1;
468 return p;
469 }
470
471 static int read_descriptor(struct x86_emulate_ctxt *ctxt,
472 struct x86_emulate_ops *ops,
473 void *ptr,
474 u16 *size, unsigned long *address, int op_bytes)
475 {
476 int rc;
477
478 if (op_bytes == 2)
479 op_bytes = 3;
480 *address = 0;
481 rc = ops->read_std((unsigned long)ptr, (unsigned long *)size, 2,
482 ctxt->vcpu);
483 if (rc)
484 return rc;
485 rc = ops->read_std((unsigned long)ptr + 2, address, op_bytes,
486 ctxt->vcpu);
487 return rc;
488 }
489
490 static int test_cc(unsigned int condition, unsigned int flags)
491 {
492 int rc = 0;
493
494 switch ((condition & 15) >> 1) {
495 case 0: /* o */
496 rc |= (flags & EFLG_OF);
497 break;
498 case 1: /* b/c/nae */
499 rc |= (flags & EFLG_CF);
500 break;
501 case 2: /* z/e */
502 rc |= (flags & EFLG_ZF);
503 break;
504 case 3: /* be/na */
505 rc |= (flags & (EFLG_CF|EFLG_ZF));
506 break;
507 case 4: /* s */
508 rc |= (flags & EFLG_SF);
509 break;
510 case 5: /* p/pe */
511 rc |= (flags & EFLG_PF);
512 break;
513 case 7: /* le/ng */
514 rc |= (flags & EFLG_ZF);
515 /* fall through */
516 case 6: /* l/nge */
517 rc |= (!(flags & EFLG_SF) != !(flags & EFLG_OF));
518 break;
519 }
520
521 /* Odd condition identifiers (lsb == 1) have inverted sense. */
522 return (!!rc ^ (condition & 1));
523 }
524
525 int
526 x86_emulate_memop(struct x86_emulate_ctxt *ctxt, struct x86_emulate_ops *ops)
527 {
528 unsigned d;
529 u8 b, sib, twobyte = 0, rex_prefix = 0;
530 u8 modrm, modrm_mod = 0, modrm_reg = 0, modrm_rm = 0;
531 unsigned long *override_base = NULL;
532 unsigned int op_bytes, ad_bytes, lock_prefix = 0, rep_prefix = 0, i;
533 int rc = 0;
534 struct operand src, dst;
535 unsigned long cr2 = ctxt->cr2;
536 int mode = ctxt->mode;
537 unsigned long modrm_ea;
538 int use_modrm_ea, index_reg = 0, base_reg = 0, scale, rip_relative = 0;
539 int no_wb = 0;
540 u64 msr_data;
541
542 /* Shadow copy of register state. Committed on successful emulation. */
543 unsigned long _regs[NR_VCPU_REGS];
544 unsigned long _eip = ctxt->vcpu->rip, _eflags = ctxt->eflags;
545 unsigned long modrm_val = 0;
546
547 memcpy(_regs, ctxt->vcpu->regs, sizeof _regs);
548
549 switch (mode) {
550 case X86EMUL_MODE_REAL:
551 case X86EMUL_MODE_PROT16:
552 op_bytes = ad_bytes = 2;
553 break;
554 case X86EMUL_MODE_PROT32:
555 op_bytes = ad_bytes = 4;
556 break;
557 #ifdef CONFIG_X86_64
558 case X86EMUL_MODE_PROT64:
559 op_bytes = 4;
560 ad_bytes = 8;
561 break;
562 #endif
563 default:
564 return -1;
565 }
566
567 /* Legacy prefixes. */
568 for (i = 0; i < 8; i++) {
569 switch (b = insn_fetch(u8, 1, _eip)) {
570 case 0x66: /* operand-size override */
571 op_bytes ^= 6; /* switch between 2/4 bytes */
572 break;
573 case 0x67: /* address-size override */
574 if (mode == X86EMUL_MODE_PROT64)
575 ad_bytes ^= 12; /* switch between 4/8 bytes */
576 else
577 ad_bytes ^= 6; /* switch between 2/4 bytes */
578 break;
579 case 0x2e: /* CS override */
580 override_base = &ctxt->cs_base;
581 break;
582 case 0x3e: /* DS override */
583 override_base = &ctxt->ds_base;
584 break;
585 case 0x26: /* ES override */
586 override_base = &ctxt->es_base;
587 break;
588 case 0x64: /* FS override */
589 override_base = &ctxt->fs_base;
590 break;
591 case 0x65: /* GS override */
592 override_base = &ctxt->gs_base;
593 break;
594 case 0x36: /* SS override */
595 override_base = &ctxt->ss_base;
596 break;
597 case 0xf0: /* LOCK */
598 lock_prefix = 1;
599 break;
600 case 0xf2: /* REPNE/REPNZ */
601 case 0xf3: /* REP/REPE/REPZ */
602 rep_prefix = 1;
603 break;
604 default:
605 goto done_prefixes;
606 }
607 }
608
609 done_prefixes:
610
611 /* REX prefix. */
612 if ((mode == X86EMUL_MODE_PROT64) && ((b & 0xf0) == 0x40)) {
613 rex_prefix = b;
614 if (b & 8)
615 op_bytes = 8; /* REX.W */
616 modrm_reg = (b & 4) << 1; /* REX.R */
617 index_reg = (b & 2) << 2; /* REX.X */
618 modrm_rm = base_reg = (b & 1) << 3; /* REG.B */
619 b = insn_fetch(u8, 1, _eip);
620 }
621
622 /* Opcode byte(s). */
623 d = opcode_table[b];
624 if (d == 0) {
625 /* Two-byte opcode? */
626 if (b == 0x0f) {
627 twobyte = 1;
628 b = insn_fetch(u8, 1, _eip);
629 d = twobyte_table[b];
630 }
631
632 /* Unrecognised? */
633 if (d == 0)
634 goto cannot_emulate;
635 }
636
637 /* ModRM and SIB bytes. */
638 if (d & ModRM) {
639 modrm = insn_fetch(u8, 1, _eip);
640 modrm_mod |= (modrm & 0xc0) >> 6;
641 modrm_reg |= (modrm & 0x38) >> 3;
642 modrm_rm |= (modrm & 0x07);
643 modrm_ea = 0;
644 use_modrm_ea = 1;
645
646 if (modrm_mod == 3) {
647 modrm_val = *(unsigned long *)
648 decode_register(modrm_rm, _regs, d & ByteOp);
649 goto modrm_done;
650 }
651
652 if (ad_bytes == 2) {
653 unsigned bx = _regs[VCPU_REGS_RBX];
654 unsigned bp = _regs[VCPU_REGS_RBP];
655 unsigned si = _regs[VCPU_REGS_RSI];
656 unsigned di = _regs[VCPU_REGS_RDI];
657
658 /* 16-bit ModR/M decode. */
659 switch (modrm_mod) {
660 case 0:
661 if (modrm_rm == 6)
662 modrm_ea += insn_fetch(u16, 2, _eip);
663 break;
664 case 1:
665 modrm_ea += insn_fetch(s8, 1, _eip);
666 break;
667 case 2:
668 modrm_ea += insn_fetch(u16, 2, _eip);
669 break;
670 }
671 switch (modrm_rm) {
672 case 0:
673 modrm_ea += bx + si;
674 break;
675 case 1:
676 modrm_ea += bx + di;
677 break;
678 case 2:
679 modrm_ea += bp + si;
680 break;
681 case 3:
682 modrm_ea += bp + di;
683 break;
684 case 4:
685 modrm_ea += si;
686 break;
687 case 5:
688 modrm_ea += di;
689 break;
690 case 6:
691 if (modrm_mod != 0)
692 modrm_ea += bp;
693 break;
694 case 7:
695 modrm_ea += bx;
696 break;
697 }
698 if (modrm_rm == 2 || modrm_rm == 3 ||
699 (modrm_rm == 6 && modrm_mod != 0))
700 if (!override_base)
701 override_base = &ctxt->ss_base;
702 modrm_ea = (u16)modrm_ea;
703 } else {
704 /* 32/64-bit ModR/M decode. */
705 switch (modrm_rm) {
706 case 4:
707 case 12:
708 sib = insn_fetch(u8, 1, _eip);
709 index_reg |= (sib >> 3) & 7;
710 base_reg |= sib & 7;
711 scale = sib >> 6;
712
713 switch (base_reg) {
714 case 5:
715 if (modrm_mod != 0)
716 modrm_ea += _regs[base_reg];
717 else
718 modrm_ea += insn_fetch(s32, 4, _eip);
719 break;
720 default:
721 modrm_ea += _regs[base_reg];
722 }
723 switch (index_reg) {
724 case 4:
725 break;
726 default:
727 modrm_ea += _regs[index_reg] << scale;
728
729 }
730 break;
731 case 5:
732 if (modrm_mod != 0)
733 modrm_ea += _regs[modrm_rm];
734 else if (mode == X86EMUL_MODE_PROT64)
735 rip_relative = 1;
736 break;
737 default:
738 modrm_ea += _regs[modrm_rm];
739 break;
740 }
741 switch (modrm_mod) {
742 case 0:
743 if (modrm_rm == 5)
744 modrm_ea += insn_fetch(s32, 4, _eip);
745 break;
746 case 1:
747 modrm_ea += insn_fetch(s8, 1, _eip);
748 break;
749 case 2:
750 modrm_ea += insn_fetch(s32, 4, _eip);
751 break;
752 }
753 }
754 if (!override_base)
755 override_base = &ctxt->ds_base;
756 if (mode == X86EMUL_MODE_PROT64 &&
757 override_base != &ctxt->fs_base &&
758 override_base != &ctxt->gs_base)
759 override_base = NULL;
760
761 if (override_base)
762 modrm_ea += *override_base;
763
764 if (rip_relative) {
765 modrm_ea += _eip;
766 switch (d & SrcMask) {
767 case SrcImmByte:
768 modrm_ea += 1;
769 break;
770 case SrcImm:
771 if (d & ByteOp)
772 modrm_ea += 1;
773 else
774 if (op_bytes == 8)
775 modrm_ea += 4;
776 else
777 modrm_ea += op_bytes;
778 }
779 }
780 if (ad_bytes != 8)
781 modrm_ea = (u32)modrm_ea;
782 cr2 = modrm_ea;
783 modrm_done:
784 ;
785 }
786
787 /*
788 * Decode and fetch the source operand: register, memory
789 * or immediate.
790 */
791 switch (d & SrcMask) {
792 case SrcNone:
793 break;
794 case SrcReg:
795 src.type = OP_REG;
796 if (d & ByteOp) {
797 src.ptr = decode_register(modrm_reg, _regs,
798 (rex_prefix == 0));
799 src.val = src.orig_val = *(u8 *) src.ptr;
800 src.bytes = 1;
801 } else {
802 src.ptr = decode_register(modrm_reg, _regs, 0);
803 switch ((src.bytes = op_bytes)) {
804 case 2:
805 src.val = src.orig_val = *(u16 *) src.ptr;
806 break;
807 case 4:
808 src.val = src.orig_val = *(u32 *) src.ptr;
809 break;
810 case 8:
811 src.val = src.orig_val = *(u64 *) src.ptr;
812 break;
813 }
814 }
815 break;
816 case SrcMem16:
817 src.bytes = 2;
818 goto srcmem_common;
819 case SrcMem32:
820 src.bytes = 4;
821 goto srcmem_common;
822 case SrcMem:
823 src.bytes = (d & ByteOp) ? 1 : op_bytes;
824 /* Don't fetch the address for invlpg: it could be unmapped. */
825 if (twobyte && b == 0x01 && modrm_reg == 7)
826 break;
827 srcmem_common:
828 /*
829 * For instructions with a ModR/M byte, switch to register
830 * access if Mod = 3.
831 */
832 if ((d & ModRM) && modrm_mod == 3) {
833 src.type = OP_REG;
834 break;
835 }
836 src.type = OP_MEM;
837 src.ptr = (unsigned long *)cr2;
838 src.val = 0;
839 if ((rc = ops->read_emulated((unsigned long)src.ptr,
840 &src.val, src.bytes, ctxt->vcpu)) != 0)
841 goto done;
842 src.orig_val = src.val;
843 break;
844 case SrcImm:
845 src.type = OP_IMM;
846 src.ptr = (unsigned long *)_eip;
847 src.bytes = (d & ByteOp) ? 1 : op_bytes;
848 if (src.bytes == 8)
849 src.bytes = 4;
850 /* NB. Immediates are sign-extended as necessary. */
851 switch (src.bytes) {
852 case 1:
853 src.val = insn_fetch(s8, 1, _eip);
854 break;
855 case 2:
856 src.val = insn_fetch(s16, 2, _eip);
857 break;
858 case 4:
859 src.val = insn_fetch(s32, 4, _eip);
860 break;
861 }
862 break;
863 case SrcImmByte:
864 src.type = OP_IMM;
865 src.ptr = (unsigned long *)_eip;
866 src.bytes = 1;
867 src.val = insn_fetch(s8, 1, _eip);
868 break;
869 }
870
871 /* Decode and fetch the destination operand: register or memory. */
872 switch (d & DstMask) {
873 case ImplicitOps:
874 /* Special instructions do their own operand decoding. */
875 goto special_insn;
876 case DstReg:
877 dst.type = OP_REG;
878 if ((d & ByteOp)
879 && !(twobyte && (b == 0xb6 || b == 0xb7))) {
880 dst.ptr = decode_register(modrm_reg, _regs,
881 (rex_prefix == 0));
882 dst.val = *(u8 *) dst.ptr;
883 dst.bytes = 1;
884 } else {
885 dst.ptr = decode_register(modrm_reg, _regs, 0);
886 switch ((dst.bytes = op_bytes)) {
887 case 2:
888 dst.val = *(u16 *)dst.ptr;
889 break;
890 case 4:
891 dst.val = *(u32 *)dst.ptr;
892 break;
893 case 8:
894 dst.val = *(u64 *)dst.ptr;
895 break;
896 }
897 }
898 break;
899 case DstMem:
900 dst.type = OP_MEM;
901 dst.ptr = (unsigned long *)cr2;
902 dst.bytes = (d & ByteOp) ? 1 : op_bytes;
903 dst.val = 0;
904 /*
905 * For instructions with a ModR/M byte, switch to register
906 * access if Mod = 3.
907 */
908 if ((d & ModRM) && modrm_mod == 3) {
909 dst.type = OP_REG;
910 break;
911 }
912 if (d & BitOp) {
913 unsigned long mask = ~(dst.bytes * 8 - 1);
914
915 dst.ptr = (void *)dst.ptr + (src.val & mask) / 8;
916 }
917 if (!(d & Mov) && /* optimisation - avoid slow emulated read */
918 ((rc = ops->read_emulated((unsigned long)dst.ptr,
919 &dst.val, dst.bytes, ctxt->vcpu)) != 0))
920 goto done;
921 break;
922 }
923 dst.orig_val = dst.val;
924
925 if (twobyte)
926 goto twobyte_insn;
927
928 switch (b) {
929 case 0x00 ... 0x05:
930 add: /* add */
931 emulate_2op_SrcV("add", src, dst, _eflags);
932 break;
933 case 0x08 ... 0x0d:
934 or: /* or */
935 emulate_2op_SrcV("or", src, dst, _eflags);
936 break;
937 case 0x10 ... 0x15:
938 adc: /* adc */
939 emulate_2op_SrcV("adc", src, dst, _eflags);
940 break;
941 case 0x18 ... 0x1d:
942 sbb: /* sbb */
943 emulate_2op_SrcV("sbb", src, dst, _eflags);
944 break;
945 case 0x20 ... 0x23:
946 and: /* and */
947 emulate_2op_SrcV("and", src, dst, _eflags);
948 break;
949 case 0x24: /* and al imm8 */
950 dst.type = OP_REG;
951 dst.ptr = &_regs[VCPU_REGS_RAX];
952 dst.val = *(u8 *)dst.ptr;
953 dst.bytes = 1;
954 dst.orig_val = dst.val;
955 goto and;
956 case 0x25: /* and ax imm16, or eax imm32 */
957 dst.type = OP_REG;
958 dst.bytes = op_bytes;
959 dst.ptr = &_regs[VCPU_REGS_RAX];
960 if (op_bytes == 2)
961 dst.val = *(u16 *)dst.ptr;
962 else
963 dst.val = *(u32 *)dst.ptr;
964 dst.orig_val = dst.val;
965 goto and;
966 case 0x28 ... 0x2d:
967 sub: /* sub */
968 emulate_2op_SrcV("sub", src, dst, _eflags);
969 break;
970 case 0x30 ... 0x35:
971 xor: /* xor */
972 emulate_2op_SrcV("xor", src, dst, _eflags);
973 break;
974 case 0x38 ... 0x3d:
975 cmp: /* cmp */
976 emulate_2op_SrcV("cmp", src, dst, _eflags);
977 break;
978 case 0x63: /* movsxd */
979 if (mode != X86EMUL_MODE_PROT64)
980 goto cannot_emulate;
981 dst.val = (s32) src.val;
982 break;
983 case 0x6a: /* push imm8 */
984 src.val = 0L;
985 src.val = insn_fetch(s8, 1, _eip);
986 push:
987 dst.type = OP_MEM;
988 dst.bytes = op_bytes;
989 dst.val = src.val;
990 register_address_increment(_regs[VCPU_REGS_RSP], -op_bytes);
991 dst.ptr = (void *) register_address(ctxt->ss_base,
992 _regs[VCPU_REGS_RSP]);
993 break;
994 case 0x80 ... 0x83: /* Grp1 */
995 switch (modrm_reg) {
996 case 0:
997 goto add;
998 case 1:
999 goto or;
1000 case 2:
1001 goto adc;
1002 case 3:
1003 goto sbb;
1004 case 4:
1005 goto and;
1006 case 5:
1007 goto sub;
1008 case 6:
1009 goto xor;
1010 case 7:
1011 goto cmp;
1012 }
1013 break;
1014 case 0x84 ... 0x85:
1015 test: /* test */
1016 emulate_2op_SrcV("test", src, dst, _eflags);
1017 break;
1018 case 0x86 ... 0x87: /* xchg */
1019 /* Write back the register source. */
1020 switch (dst.bytes) {
1021 case 1:
1022 *(u8 *) src.ptr = (u8) dst.val;
1023 break;
1024 case 2:
1025 *(u16 *) src.ptr = (u16) dst.val;
1026 break;
1027 case 4:
1028 *src.ptr = (u32) dst.val;
1029 break; /* 64b reg: zero-extend */
1030 case 8:
1031 *src.ptr = dst.val;
1032 break;
1033 }
1034 /*
1035 * Write back the memory destination with implicit LOCK
1036 * prefix.
1037 */
1038 dst.val = src.val;
1039 lock_prefix = 1;
1040 break;
1041 case 0x88 ... 0x8b: /* mov */
1042 goto mov;
1043 case 0x8d: /* lea r16/r32, m */
1044 dst.val = modrm_val;
1045 break;
1046 case 0x8f: /* pop (sole member of Grp1a) */
1047 /* 64-bit mode: POP always pops a 64-bit operand. */
1048 if (mode == X86EMUL_MODE_PROT64)
1049 dst.bytes = 8;
1050 if ((rc = ops->read_std(register_address(ctxt->ss_base,
1051 _regs[VCPU_REGS_RSP]),
1052 &dst.val, dst.bytes, ctxt->vcpu)) != 0)
1053 goto done;
1054 register_address_increment(_regs[VCPU_REGS_RSP], dst.bytes);
1055 break;
1056 case 0xa0 ... 0xa1: /* mov */
1057 dst.ptr = (unsigned long *)&_regs[VCPU_REGS_RAX];
1058 dst.val = src.val;
1059 _eip += ad_bytes; /* skip src displacement */
1060 break;
1061 case 0xa2 ... 0xa3: /* mov */
1062 dst.val = (unsigned long)_regs[VCPU_REGS_RAX];
1063 _eip += ad_bytes; /* skip dst displacement */
1064 break;
1065 case 0xc0 ... 0xc1:
1066 grp2: /* Grp2 */
1067 switch (modrm_reg) {
1068 case 0: /* rol */
1069 emulate_2op_SrcB("rol", src, dst, _eflags);
1070 break;
1071 case 1: /* ror */
1072 emulate_2op_SrcB("ror", src, dst, _eflags);
1073 break;
1074 case 2: /* rcl */
1075 emulate_2op_SrcB("rcl", src, dst, _eflags);
1076 break;
1077 case 3: /* rcr */
1078 emulate_2op_SrcB("rcr", src, dst, _eflags);
1079 break;
1080 case 4: /* sal/shl */
1081 case 6: /* sal/shl */
1082 emulate_2op_SrcB("sal", src, dst, _eflags);
1083 break;
1084 case 5: /* shr */
1085 emulate_2op_SrcB("shr", src, dst, _eflags);
1086 break;
1087 case 7: /* sar */
1088 emulate_2op_SrcB("sar", src, dst, _eflags);
1089 break;
1090 }
1091 break;
1092 case 0xc6 ... 0xc7: /* mov (sole member of Grp11) */
1093 mov:
1094 dst.val = src.val;
1095 break;
1096 case 0xd0 ... 0xd1: /* Grp2 */
1097 src.val = 1;
1098 goto grp2;
1099 case 0xd2 ... 0xd3: /* Grp2 */
1100 src.val = _regs[VCPU_REGS_RCX];
1101 goto grp2;
1102 case 0xf6 ... 0xf7: /* Grp3 */
1103 switch (modrm_reg) {
1104 case 0 ... 1: /* test */
1105 /*
1106 * Special case in Grp3: test has an immediate
1107 * source operand.
1108 */
1109 src.type = OP_IMM;
1110 src.ptr = (unsigned long *)_eip;
1111 src.bytes = (d & ByteOp) ? 1 : op_bytes;
1112 if (src.bytes == 8)
1113 src.bytes = 4;
1114 switch (src.bytes) {
1115 case 1:
1116 src.val = insn_fetch(s8, 1, _eip);
1117 break;
1118 case 2:
1119 src.val = insn_fetch(s16, 2, _eip);
1120 break;
1121 case 4:
1122 src.val = insn_fetch(s32, 4, _eip);
1123 break;
1124 }
1125 goto test;
1126 case 2: /* not */
1127 dst.val = ~dst.val;
1128 break;
1129 case 3: /* neg */
1130 emulate_1op("neg", dst, _eflags);
1131 break;
1132 default:
1133 goto cannot_emulate;
1134 }
1135 break;
1136 case 0xfe ... 0xff: /* Grp4/Grp5 */
1137 switch (modrm_reg) {
1138 case 0: /* inc */
1139 emulate_1op("inc", dst, _eflags);
1140 break;
1141 case 1: /* dec */
1142 emulate_1op("dec", dst, _eflags);
1143 break;
1144 case 4: /* jmp abs */
1145 if (b == 0xff)
1146 _eip = dst.val;
1147 else
1148 goto cannot_emulate;
1149 break;
1150 case 6: /* push */
1151 /* 64-bit mode: PUSH always pushes a 64-bit operand. */
1152 if (mode == X86EMUL_MODE_PROT64) {
1153 dst.bytes = 8;
1154 if ((rc = ops->read_std((unsigned long)dst.ptr,
1155 &dst.val, 8,
1156 ctxt->vcpu)) != 0)
1157 goto done;
1158 }
1159 register_address_increment(_regs[VCPU_REGS_RSP],
1160 -dst.bytes);
1161 if ((rc = ops->write_std(
1162 register_address(ctxt->ss_base,
1163 _regs[VCPU_REGS_RSP]),
1164 &dst.val, dst.bytes, ctxt->vcpu)) != 0)
1165 goto done;
1166 no_wb = 1;
1167 break;
1168 default:
1169 goto cannot_emulate;
1170 }
1171 break;
1172 }
1173
1174 writeback:
1175 if (!no_wb) {
1176 switch (dst.type) {
1177 case OP_REG:
1178 /* The 4-byte case *is* correct: in 64-bit mode we zero-extend. */
1179 switch (dst.bytes) {
1180 case 1:
1181 *(u8 *)dst.ptr = (u8)dst.val;
1182 break;
1183 case 2:
1184 *(u16 *)dst.ptr = (u16)dst.val;
1185 break;
1186 case 4:
1187 *dst.ptr = (u32)dst.val;
1188 break; /* 64b: zero-ext */
1189 case 8:
1190 *dst.ptr = dst.val;
1191 break;
1192 }
1193 break;
1194 case OP_MEM:
1195 if (lock_prefix)
1196 rc = ops->cmpxchg_emulated((unsigned long)dst.
1197 ptr, &dst.orig_val,
1198 &dst.val, dst.bytes,
1199 ctxt->vcpu);
1200 else
1201 rc = ops->write_emulated((unsigned long)dst.ptr,
1202 &dst.val, dst.bytes,
1203 ctxt->vcpu);
1204 if (rc != 0)
1205 goto done;
1206 default:
1207 break;
1208 }
1209 }
1210
1211 /* Commit shadow register state. */
1212 memcpy(ctxt->vcpu->regs, _regs, sizeof _regs);
1213 ctxt->eflags = _eflags;
1214 ctxt->vcpu->rip = _eip;
1215
1216 done:
1217 return (rc == X86EMUL_UNHANDLEABLE) ? -1 : 0;
1218
1219 special_insn:
1220 if (twobyte)
1221 goto twobyte_special_insn;
1222 switch(b) {
1223 case 0x50 ... 0x57: /* push reg */
1224 if (op_bytes == 2)
1225 src.val = (u16) _regs[b & 0x7];
1226 else
1227 src.val = (u32) _regs[b & 0x7];
1228 dst.type = OP_MEM;
1229 dst.bytes = op_bytes;
1230 dst.val = src.val;
1231 register_address_increment(_regs[VCPU_REGS_RSP], -op_bytes);
1232 dst.ptr = (void *) register_address(
1233 ctxt->ss_base, _regs[VCPU_REGS_RSP]);
1234 break;
1235 case 0x58 ... 0x5f: /* pop reg */
1236 dst.ptr = (unsigned long *)&_regs[b & 0x7];
1237 pop_instruction:
1238 if ((rc = ops->read_std(register_address(ctxt->ss_base,
1239 _regs[VCPU_REGS_RSP]), dst.ptr, op_bytes, ctxt->vcpu))
1240 != 0)
1241 goto done;
1242
1243 register_address_increment(_regs[VCPU_REGS_RSP], op_bytes);
1244 no_wb = 1; /* Disable writeback. */
1245 break;
1246 case 0x6c: /* insb */
1247 case 0x6d: /* insw/insd */
1248 if (kvm_emulate_pio_string(ctxt->vcpu, NULL,
1249 1, /* in */
1250 (d & ByteOp) ? 1 : op_bytes, /* size */
1251 rep_prefix ?
1252 address_mask(_regs[VCPU_REGS_RCX]) : 1, /* count */
1253 (_eflags & EFLG_DF), /* down */
1254 register_address(ctxt->es_base,
1255 _regs[VCPU_REGS_RDI]), /* address */
1256 rep_prefix,
1257 _regs[VCPU_REGS_RDX] /* port */
1258 ) == 0)
1259 return -1;
1260 return 0;
1261 case 0x6e: /* outsb */
1262 case 0x6f: /* outsw/outsd */
1263 if (kvm_emulate_pio_string(ctxt->vcpu, NULL,
1264 0, /* in */
1265 (d & ByteOp) ? 1 : op_bytes, /* size */
1266 rep_prefix ?
1267 address_mask(_regs[VCPU_REGS_RCX]) : 1, /* count */
1268 (_eflags & EFLG_DF), /* down */
1269 register_address(override_base ?
1270 *override_base : ctxt->ds_base,
1271 _regs[VCPU_REGS_RSI]), /* address */
1272 rep_prefix,
1273 _regs[VCPU_REGS_RDX] /* port */
1274 ) == 0)
1275 return -1;
1276 return 0;
1277 case 0x70 ... 0x7f: /* jcc (short) */ {
1278 int rel = insn_fetch(s8, 1, _eip);
1279
1280 if (test_cc(b, _eflags))
1281 JMP_REL(rel);
1282 break;
1283 }
1284 case 0x9c: /* pushf */
1285 src.val = (unsigned long) _eflags;
1286 goto push;
1287 case 0x9d: /* popf */
1288 dst.ptr = (unsigned long *) &_eflags;
1289 goto pop_instruction;
1290 case 0xc3: /* ret */
1291 dst.ptr = &_eip;
1292 goto pop_instruction;
1293 case 0xf4: /* hlt */
1294 ctxt->vcpu->halt_request = 1;
1295 goto done;
1296 }
1297 if (rep_prefix) {
1298 if (_regs[VCPU_REGS_RCX] == 0) {
1299 ctxt->vcpu->rip = _eip;
1300 goto done;
1301 }
1302 _regs[VCPU_REGS_RCX]--;
1303 _eip = ctxt->vcpu->rip;
1304 }
1305 switch (b) {
1306 case 0xa4 ... 0xa5: /* movs */
1307 dst.type = OP_MEM;
1308 dst.bytes = (d & ByteOp) ? 1 : op_bytes;
1309 dst.ptr = (unsigned long *)register_address(ctxt->es_base,
1310 _regs[VCPU_REGS_RDI]);
1311 if ((rc = ops->read_emulated(register_address(
1312 override_base ? *override_base : ctxt->ds_base,
1313 _regs[VCPU_REGS_RSI]), &dst.val, dst.bytes, ctxt->vcpu)) != 0)
1314 goto done;
1315 register_address_increment(_regs[VCPU_REGS_RSI],
1316 (_eflags & EFLG_DF) ? -dst.bytes : dst.bytes);
1317 register_address_increment(_regs[VCPU_REGS_RDI],
1318 (_eflags & EFLG_DF) ? -dst.bytes : dst.bytes);
1319 break;
1320 case 0xa6 ... 0xa7: /* cmps */
1321 DPRINTF("Urk! I don't handle CMPS.\n");
1322 goto cannot_emulate;
1323 case 0xaa ... 0xab: /* stos */
1324 dst.type = OP_MEM;
1325 dst.bytes = (d & ByteOp) ? 1 : op_bytes;
1326 dst.ptr = (unsigned long *)cr2;
1327 dst.val = _regs[VCPU_REGS_RAX];
1328 register_address_increment(_regs[VCPU_REGS_RDI],
1329 (_eflags & EFLG_DF) ? -dst.bytes : dst.bytes);
1330 break;
1331 case 0xac ... 0xad: /* lods */
1332 dst.type = OP_REG;
1333 dst.bytes = (d & ByteOp) ? 1 : op_bytes;
1334 dst.ptr = (unsigned long *)&_regs[VCPU_REGS_RAX];
1335 if ((rc = ops->read_emulated(cr2, &dst.val, dst.bytes,
1336 ctxt->vcpu)) != 0)
1337 goto done;
1338 register_address_increment(_regs[VCPU_REGS_RSI],
1339 (_eflags & EFLG_DF) ? -dst.bytes : dst.bytes);
1340 break;
1341 case 0xae ... 0xaf: /* scas */
1342 DPRINTF("Urk! I don't handle SCAS.\n");
1343 goto cannot_emulate;
1344 case 0xe8: /* call (near) */ {
1345 long int rel;
1346 switch (op_bytes) {
1347 case 2:
1348 rel = insn_fetch(s16, 2, _eip);
1349 break;
1350 case 4:
1351 rel = insn_fetch(s32, 4, _eip);
1352 break;
1353 case 8:
1354 rel = insn_fetch(s64, 8, _eip);
1355 break;
1356 default:
1357 DPRINTF("Call: Invalid op_bytes\n");
1358 goto cannot_emulate;
1359 }
1360 src.val = (unsigned long) _eip;
1361 JMP_REL(rel);
1362 goto push;
1363 }
1364 case 0xe9: /* jmp rel */
1365 case 0xeb: /* jmp rel short */
1366 JMP_REL(src.val);
1367 no_wb = 1; /* Disable writeback. */
1368 break;
1369
1370
1371 }
1372 goto writeback;
1373
1374 twobyte_insn:
1375 switch (b) {
1376 case 0x01: /* lgdt, lidt, lmsw */
1377 /* Disable writeback. */
1378 no_wb = 1;
1379 switch (modrm_reg) {
1380 u16 size;
1381 unsigned long address;
1382
1383 case 2: /* lgdt */
1384 rc = read_descriptor(ctxt, ops, src.ptr,
1385 &size, &address, op_bytes);
1386 if (rc)
1387 goto done;
1388 realmode_lgdt(ctxt->vcpu, size, address);
1389 break;
1390 case 3: /* lidt */
1391 rc = read_descriptor(ctxt, ops, src.ptr,
1392 &size, &address, op_bytes);
1393 if (rc)
1394 goto done;
1395 realmode_lidt(ctxt->vcpu, size, address);
1396 break;
1397 case 4: /* smsw */
1398 if (modrm_mod != 3)
1399 goto cannot_emulate;
1400 *(u16 *)&_regs[modrm_rm]
1401 = realmode_get_cr(ctxt->vcpu, 0);
1402 break;
1403 case 6: /* lmsw */
1404 if (modrm_mod != 3)
1405 goto cannot_emulate;
1406 realmode_lmsw(ctxt->vcpu, (u16)modrm_val, &_eflags);
1407 break;
1408 case 7: /* invlpg*/
1409 emulate_invlpg(ctxt->vcpu, cr2);
1410 break;
1411 default:
1412 goto cannot_emulate;
1413 }
1414 break;
1415 case 0x21: /* mov from dr to reg */
1416 no_wb = 1;
1417 if (modrm_mod != 3)
1418 goto cannot_emulate;
1419 rc = emulator_get_dr(ctxt, modrm_reg, &_regs[modrm_rm]);
1420 break;
1421 case 0x23: /* mov from reg to dr */
1422 no_wb = 1;
1423 if (modrm_mod != 3)
1424 goto cannot_emulate;
1425 rc = emulator_set_dr(ctxt, modrm_reg, _regs[modrm_rm]);
1426 break;
1427 case 0x40 ... 0x4f: /* cmov */
1428 dst.val = dst.orig_val = src.val;
1429 no_wb = 1;
1430 /*
1431 * First, assume we're decoding an even cmov opcode
1432 * (lsb == 0).
1433 */
1434 switch ((b & 15) >> 1) {
1435 case 0: /* cmovo */
1436 no_wb = (_eflags & EFLG_OF) ? 0 : 1;
1437 break;
1438 case 1: /* cmovb/cmovc/cmovnae */
1439 no_wb = (_eflags & EFLG_CF) ? 0 : 1;
1440 break;
1441 case 2: /* cmovz/cmove */
1442 no_wb = (_eflags & EFLG_ZF) ? 0 : 1;
1443 break;
1444 case 3: /* cmovbe/cmovna */
1445 no_wb = (_eflags & (EFLG_CF | EFLG_ZF)) ? 0 : 1;
1446 break;
1447 case 4: /* cmovs */
1448 no_wb = (_eflags & EFLG_SF) ? 0 : 1;
1449 break;
1450 case 5: /* cmovp/cmovpe */
1451 no_wb = (_eflags & EFLG_PF) ? 0 : 1;
1452 break;
1453 case 7: /* cmovle/cmovng */
1454 no_wb = (_eflags & EFLG_ZF) ? 0 : 1;
1455 /* fall through */
1456 case 6: /* cmovl/cmovnge */
1457 no_wb &= (!(_eflags & EFLG_SF) !=
1458 !(_eflags & EFLG_OF)) ? 0 : 1;
1459 break;
1460 }
1461 /* Odd cmov opcodes (lsb == 1) have inverted sense. */
1462 no_wb ^= b & 1;
1463 break;
1464 case 0xa3:
1465 bt: /* bt */
1466 src.val &= (dst.bytes << 3) - 1; /* only subword offset */
1467 emulate_2op_SrcV_nobyte("bt", src, dst, _eflags);
1468 break;
1469 case 0xab:
1470 bts: /* bts */
1471 src.val &= (dst.bytes << 3) - 1; /* only subword offset */
1472 emulate_2op_SrcV_nobyte("bts", src, dst, _eflags);
1473 break;
1474 case 0xb0 ... 0xb1: /* cmpxchg */
1475 /*
1476 * Save real source value, then compare EAX against
1477 * destination.
1478 */
1479 src.orig_val = src.val;
1480 src.val = _regs[VCPU_REGS_RAX];
1481 emulate_2op_SrcV("cmp", src, dst, _eflags);
1482 if (_eflags & EFLG_ZF) {
1483 /* Success: write back to memory. */
1484 dst.val = src.orig_val;
1485 } else {
1486 /* Failure: write the value we saw to EAX. */
1487 dst.type = OP_REG;
1488 dst.ptr = (unsigned long *)&_regs[VCPU_REGS_RAX];
1489 }
1490 break;
1491 case 0xb3:
1492 btr: /* btr */
1493 src.val &= (dst.bytes << 3) - 1; /* only subword offset */
1494 emulate_2op_SrcV_nobyte("btr", src, dst, _eflags);
1495 break;
1496 case 0xb6 ... 0xb7: /* movzx */
1497 dst.bytes = op_bytes;
1498 dst.val = (d & ByteOp) ? (u8) src.val : (u16) src.val;
1499 break;
1500 case 0xba: /* Grp8 */
1501 switch (modrm_reg & 3) {
1502 case 0:
1503 goto bt;
1504 case 1:
1505 goto bts;
1506 case 2:
1507 goto btr;
1508 case 3:
1509 goto btc;
1510 }
1511 break;
1512 case 0xbb:
1513 btc: /* btc */
1514 src.val &= (dst.bytes << 3) - 1; /* only subword offset */
1515 emulate_2op_SrcV_nobyte("btc", src, dst, _eflags);
1516 break;
1517 case 0xbe ... 0xbf: /* movsx */
1518 dst.bytes = op_bytes;
1519 dst.val = (d & ByteOp) ? (s8) src.val : (s16) src.val;
1520 break;
1521 case 0xc3: /* movnti */
1522 dst.bytes = op_bytes;
1523 dst.val = (op_bytes == 4) ? (u32) src.val : (u64) src.val;
1524 break;
1525 }
1526 goto writeback;
1527
1528 twobyte_special_insn:
1529 /* Disable writeback. */
1530 no_wb = 1;
1531 switch (b) {
1532 case 0x06:
1533 emulate_clts(ctxt->vcpu);
1534 break;
1535 case 0x09: /* wbinvd */
1536 break;
1537 case 0x0d: /* GrpP (prefetch) */
1538 case 0x18: /* Grp16 (prefetch/nop) */
1539 break;
1540 case 0x20: /* mov cr, reg */
1541 if (modrm_mod != 3)
1542 goto cannot_emulate;
1543 _regs[modrm_rm] = realmode_get_cr(ctxt->vcpu, modrm_reg);
1544 break;
1545 case 0x22: /* mov reg, cr */
1546 if (modrm_mod != 3)
1547 goto cannot_emulate;
1548 realmode_set_cr(ctxt->vcpu, modrm_reg, modrm_val, &_eflags);
1549 break;
1550 case 0x30:
1551 /* wrmsr */
1552 msr_data = (u32)_regs[VCPU_REGS_RAX]
1553 | ((u64)_regs[VCPU_REGS_RDX] << 32);
1554 rc = kvm_set_msr(ctxt->vcpu, _regs[VCPU_REGS_RCX], msr_data);
1555 if (rc) {
1556 kvm_x86_ops->inject_gp(ctxt->vcpu, 0);
1557 _eip = ctxt->vcpu->rip;
1558 }
1559 rc = X86EMUL_CONTINUE;
1560 break;
1561 case 0x32:
1562 /* rdmsr */
1563 rc = kvm_get_msr(ctxt->vcpu, _regs[VCPU_REGS_RCX], &msr_data);
1564 if (rc) {
1565 kvm_x86_ops->inject_gp(ctxt->vcpu, 0);
1566 _eip = ctxt->vcpu->rip;
1567 } else {
1568 _regs[VCPU_REGS_RAX] = (u32)msr_data;
1569 _regs[VCPU_REGS_RDX] = msr_data >> 32;
1570 }
1571 rc = X86EMUL_CONTINUE;
1572 break;
1573 case 0x80 ... 0x8f: /* jnz rel, etc*/ {
1574 long int rel;
1575
1576 switch (op_bytes) {
1577 case 2:
1578 rel = insn_fetch(s16, 2, _eip);
1579 break;
1580 case 4:
1581 rel = insn_fetch(s32, 4, _eip);
1582 break;
1583 case 8:
1584 rel = insn_fetch(s64, 8, _eip);
1585 break;
1586 default:
1587 DPRINTF("jnz: Invalid op_bytes\n");
1588 goto cannot_emulate;
1589 }
1590 if (test_cc(b, _eflags))
1591 JMP_REL(rel);
1592 break;
1593 }
1594 case 0xc7: /* Grp9 (cmpxchg8b) */
1595 {
1596 u64 old, new;
1597 if ((rc = ops->read_emulated(cr2, &old, 8, ctxt->vcpu))
1598 != 0)
1599 goto done;
1600 if (((u32) (old >> 0) != (u32) _regs[VCPU_REGS_RAX]) ||
1601 ((u32) (old >> 32) != (u32) _regs[VCPU_REGS_RDX])) {
1602 _regs[VCPU_REGS_RAX] = (u32) (old >> 0);
1603 _regs[VCPU_REGS_RDX] = (u32) (old >> 32);
1604 _eflags &= ~EFLG_ZF;
1605 } else {
1606 new = ((u64)_regs[VCPU_REGS_RCX] << 32)
1607 | (u32) _regs[VCPU_REGS_RBX];
1608 if ((rc = ops->cmpxchg_emulated(cr2, &old,
1609 &new, 8, ctxt->vcpu)) != 0)
1610 goto done;
1611 _eflags |= EFLG_ZF;
1612 }
1613 break;
1614 }
1615 }
1616 goto writeback;
1617
1618 cannot_emulate:
1619 DPRINTF("Cannot emulate %02x\n", b);
1620 return -1;
1621 }
1622
1623 #ifdef __XEN__
1624
1625 #include <asm/mm.h>
1626 #include <asm/uaccess.h>
1627
1628 int
1629 x86_emulate_read_std(unsigned long addr,
1630 unsigned long *val,
1631 unsigned int bytes, struct x86_emulate_ctxt *ctxt)
1632 {
1633 unsigned int rc;
1634
1635 *val = 0;
1636
1637 if ((rc = copy_from_user((void *)val, (void *)addr, bytes)) != 0) {
1638 propagate_page_fault(addr + bytes - rc, 0); /* read fault */
1639 return X86EMUL_PROPAGATE_FAULT;
1640 }
1641
1642 return X86EMUL_CONTINUE;
1643 }
1644
1645 int
1646 x86_emulate_write_std(unsigned long addr,
1647 unsigned long val,
1648 unsigned int bytes, struct x86_emulate_ctxt *ctxt)
1649 {
1650 unsigned int rc;
1651
1652 if ((rc = copy_to_user((void *)addr, (void *)&val, bytes)) != 0) {
1653 propagate_page_fault(addr + bytes - rc, PGERR_write_access);
1654 return X86EMUL_PROPAGATE_FAULT;
1655 }
1656
1657 return X86EMUL_CONTINUE;
1658 }
1659
1660 #endif
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