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libata pata_via: ACPI checks for 80wire cable
[pv_ops_mirror.git] / drivers / ide / mips / au1xxx-ide.c
blob85819ae20602e9c5696f78642e9032944680d4e0
1 /*
2 * linux/drivers/ide/mips/au1xxx-ide.c version 01.30.00 Aug. 02 2005
3 *
4 * BRIEF MODULE DESCRIPTION
5 * AMD Alchemy Au1xxx IDE interface routines over the Static Bus
6 *
7 * Copyright (c) 2003-2005 AMD, Personal Connectivity Solutions
8 *
9 * This program is free software; you can redistribute it and/or modify it under
10 * the terms of the GNU General Public License as published by the Free Software
11 * Foundation; either version 2 of the License, or (at your option) any later
12 * version.
13 *
14 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES,
15 * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND
16 * FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR
17 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
18 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
19 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
20 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
21 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
22 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
23 * POSSIBILITY OF SUCH DAMAGE.
24 *
25 * You should have received a copy of the GNU General Public License along with
26 * this program; if not, write to the Free Software Foundation, Inc.,
27 * 675 Mass Ave, Cambridge, MA 02139, USA.
28 *
29 * Note: for more information, please refer "AMD Alchemy Au1200/Au1550 IDE
30 * Interface and Linux Device Driver" Application Note.
31 */
32 #include <linux/types.h>
33 #include <linux/module.h>
34 #include <linux/kernel.h>
35 #include <linux/delay.h>
36 #include <linux/platform_device.h>
37
38 #include <linux/init.h>
39 #include <linux/ide.h>
40 #include <linux/sysdev.h>
41
42 #include <linux/dma-mapping.h>
43
44 #include "ide-timing.h"
45
46 #include <asm/io.h>
47 #include <asm/mach-au1x00/au1xxx.h>
48 #include <asm/mach-au1x00/au1xxx_dbdma.h>
49
50 #include <asm/mach-au1x00/au1xxx_ide.h>
51
52 #define DRV_NAME "au1200-ide"
53 #define DRV_VERSION "1.0"
54 #define DRV_AUTHOR "Enrico Walther <enrico.walther@amd.com> / Pete Popov <ppopov@embeddedalley.com>"
55
56 /* enable the burstmode in the dbdma */
57 #define IDE_AU1XXX_BURSTMODE 1
58
59 static _auide_hwif auide_hwif;
60 static int dbdma_init_done;
61
62 #if defined(CONFIG_BLK_DEV_IDE_AU1XXX_PIO_DBDMA)
63
64 void auide_insw(unsigned long port, void *addr, u32 count)
65 {
66 _auide_hwif *ahwif = &auide_hwif;
67 chan_tab_t *ctp;
68 au1x_ddma_desc_t *dp;
69
70 if(!put_dest_flags(ahwif->rx_chan, (void*)addr, count << 1,
71 DDMA_FLAGS_NOIE)) {
72 printk(KERN_ERR "%s failed %d\n", __FUNCTION__, __LINE__);
73 return;
74 }
75 ctp = *((chan_tab_t **)ahwif->rx_chan);
76 dp = ctp->cur_ptr;
77 while (dp->dscr_cmd0 & DSCR_CMD0_V)
78 ;
79 ctp->cur_ptr = au1xxx_ddma_get_nextptr_virt(dp);
80 }
81
82 void auide_outsw(unsigned long port, void *addr, u32 count)
83 {
84 _auide_hwif *ahwif = &auide_hwif;
85 chan_tab_t *ctp;
86 au1x_ddma_desc_t *dp;
87
88 if(!put_source_flags(ahwif->tx_chan, (void*)addr,
89 count << 1, DDMA_FLAGS_NOIE)) {
90 printk(KERN_ERR "%s failed %d\n", __FUNCTION__, __LINE__);
91 return;
92 }
93 ctp = *((chan_tab_t **)ahwif->tx_chan);
94 dp = ctp->cur_ptr;
95 while (dp->dscr_cmd0 & DSCR_CMD0_V)
96 ;
97 ctp->cur_ptr = au1xxx_ddma_get_nextptr_virt(dp);
98 }
99
100 #endif
101
102 static void au1xxx_set_pio_mode(ide_drive_t *drive, const u8 pio)
103 {
104 int mem_sttime;
105 int mem_stcfg;
106 u8 speed;
107
108 mem_sttime = 0;
109 mem_stcfg = au_readl(MEM_STCFG2);
110
111 /* set pio mode! */
112 switch(pio) {
113 case 0:
114 mem_sttime = SBC_IDE_TIMING(PIO0);
115
116 /* set configuration for RCS2# */
117 mem_stcfg |= TS_MASK;
118 mem_stcfg &= ~TCSOE_MASK;
119 mem_stcfg &= ~TOECS_MASK;
120 mem_stcfg |= SBC_IDE_PIO0_TCSOE | SBC_IDE_PIO0_TOECS;
121 break;
122
123 case 1:
124 mem_sttime = SBC_IDE_TIMING(PIO1);
125
126 /* set configuration for RCS2# */
127 mem_stcfg |= TS_MASK;
128 mem_stcfg &= ~TCSOE_MASK;
129 mem_stcfg &= ~TOECS_MASK;
130 mem_stcfg |= SBC_IDE_PIO1_TCSOE | SBC_IDE_PIO1_TOECS;
131 break;
132
133 case 2:
134 mem_sttime = SBC_IDE_TIMING(PIO2);
135
136 /* set configuration for RCS2# */
137 mem_stcfg &= ~TS_MASK;
138 mem_stcfg &= ~TCSOE_MASK;
139 mem_stcfg &= ~TOECS_MASK;
140 mem_stcfg |= SBC_IDE_PIO2_TCSOE | SBC_IDE_PIO2_TOECS;
141 break;
142
143 case 3:
144 mem_sttime = SBC_IDE_TIMING(PIO3);
145
146 /* set configuration for RCS2# */
147 mem_stcfg &= ~TS_MASK;
148 mem_stcfg &= ~TCSOE_MASK;
149 mem_stcfg &= ~TOECS_MASK;
150 mem_stcfg |= SBC_IDE_PIO3_TCSOE | SBC_IDE_PIO3_TOECS;
151
152 break;
153
154 case 4:
155 mem_sttime = SBC_IDE_TIMING(PIO4);
156
157 /* set configuration for RCS2# */
158 mem_stcfg &= ~TS_MASK;
159 mem_stcfg &= ~TCSOE_MASK;
160 mem_stcfg &= ~TOECS_MASK;
161 mem_stcfg |= SBC_IDE_PIO4_TCSOE | SBC_IDE_PIO4_TOECS;
162 break;
163 }
164
165 au_writel(mem_sttime,MEM_STTIME2);
166 au_writel(mem_stcfg,MEM_STCFG2);
167
168 speed = pio + XFER_PIO_0;
169 ide_config_drive_speed(drive, speed);
170 }
171
172 static int auide_tune_chipset(ide_drive_t *drive, const u8 speed)
173 {
174 int mem_sttime;
175 int mem_stcfg;
176
177 mem_sttime = 0;
178 mem_stcfg = au_readl(MEM_STCFG2);
179
180 switch(speed) {
181 #ifdef CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA
182 case XFER_MW_DMA_2:
183 mem_sttime = SBC_IDE_TIMING(MDMA2);
184
185 /* set configuration for RCS2# */
186 mem_stcfg &= ~TS_MASK;
187 mem_stcfg &= ~TCSOE_MASK;
188 mem_stcfg &= ~TOECS_MASK;
189 mem_stcfg |= SBC_IDE_MDMA2_TCSOE | SBC_IDE_MDMA2_TOECS;
190
191 break;
192 case XFER_MW_DMA_1:
193 mem_sttime = SBC_IDE_TIMING(MDMA1);
194
195 /* set configuration for RCS2# */
196 mem_stcfg &= ~TS_MASK;
197 mem_stcfg &= ~TCSOE_MASK;
198 mem_stcfg &= ~TOECS_MASK;
199 mem_stcfg |= SBC_IDE_MDMA1_TCSOE | SBC_IDE_MDMA1_TOECS;
200
201 break;
202 case XFER_MW_DMA_0:
203 mem_sttime = SBC_IDE_TIMING(MDMA0);
204
205 /* set configuration for RCS2# */
206 mem_stcfg |= TS_MASK;
207 mem_stcfg &= ~TCSOE_MASK;
208 mem_stcfg &= ~TOECS_MASK;
209 mem_stcfg |= SBC_IDE_MDMA0_TCSOE | SBC_IDE_MDMA0_TOECS;
210
211 break;
212 #endif
213 default:
214 return 1;
215 }
216
217 if (ide_config_drive_speed(drive, speed))
218 return 1;
219
220 au_writel(mem_sttime,MEM_STTIME2);
221 au_writel(mem_stcfg,MEM_STCFG2);
222
223 return 0;
224 }
225
226 /*
227 * Multi-Word DMA + DbDMA functions
228 */
229
230 #ifdef CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA
231
232 static int auide_build_sglist(ide_drive_t *drive, struct request *rq)
233 {
234 ide_hwif_t *hwif = drive->hwif;
235 _auide_hwif *ahwif = (_auide_hwif*)hwif->hwif_data;
236 struct scatterlist *sg = hwif->sg_table;
237
238 ide_map_sg(drive, rq);
239
240 if (rq_data_dir(rq) == READ)
241 hwif->sg_dma_direction = DMA_FROM_DEVICE;
242 else
243 hwif->sg_dma_direction = DMA_TO_DEVICE;
244
245 return dma_map_sg(ahwif->dev, sg, hwif->sg_nents,
246 hwif->sg_dma_direction);
247 }
248
249 static int auide_build_dmatable(ide_drive_t *drive)
250 {
251 int i, iswrite, count = 0;
252 ide_hwif_t *hwif = HWIF(drive);
253
254 struct request *rq = HWGROUP(drive)->rq;
255
256 _auide_hwif *ahwif = (_auide_hwif*)hwif->hwif_data;
257 struct scatterlist *sg;
258
259 iswrite = (rq_data_dir(rq) == WRITE);
260 /* Save for interrupt context */
261 ahwif->drive = drive;
262
263 /* Build sglist */
264 hwif->sg_nents = i = auide_build_sglist(drive, rq);
265
266 if (!i)
267 return 0;
268
269 /* fill the descriptors */
270 sg = hwif->sg_table;
271 while (i && sg_dma_len(sg)) {
272 u32 cur_addr;
273 u32 cur_len;
274
275 cur_addr = sg_dma_address(sg);
276 cur_len = sg_dma_len(sg);
277
278 while (cur_len) {
279 u32 flags = DDMA_FLAGS_NOIE;
280 unsigned int tc = (cur_len < 0xfe00)? cur_len: 0xfe00;
281
282 if (++count >= PRD_ENTRIES) {
283 printk(KERN_WARNING "%s: DMA table too small\n",
284 drive->name);
285 goto use_pio_instead;
286 }
287
288 /* Lets enable intr for the last descriptor only */
289 if (1==i)
290 flags = DDMA_FLAGS_IE;
291 else
292 flags = DDMA_FLAGS_NOIE;
293
294 if (iswrite) {
295 if(!put_source_flags(ahwif->tx_chan,
296 (void*)(page_address(sg->page)
297 + sg->offset),
298 tc, flags)) {
299 printk(KERN_ERR "%s failed %d\n",
300 __FUNCTION__, __LINE__);
301 }
302 } else
303 {
304 if(!put_dest_flags(ahwif->rx_chan,
305 (void*)(page_address(sg->page)
306 + sg->offset),
307 tc, flags)) {
308 printk(KERN_ERR "%s failed %d\n",
309 __FUNCTION__, __LINE__);
310 }
311 }
312
313 cur_addr += tc;
314 cur_len -= tc;
315 }
316 sg++;
317 i--;
318 }
319
320 if (count)
321 return 1;
322
323 use_pio_instead:
324 dma_unmap_sg(ahwif->dev,
325 hwif->sg_table,
326 hwif->sg_nents,
327 hwif->sg_dma_direction);
328
329 return 0; /* revert to PIO for this request */
330 }
331
332 static int auide_dma_end(ide_drive_t *drive)
333 {
334 ide_hwif_t *hwif = HWIF(drive);
335 _auide_hwif *ahwif = (_auide_hwif*)hwif->hwif_data;
336
337 if (hwif->sg_nents) {
338 dma_unmap_sg(ahwif->dev, hwif->sg_table, hwif->sg_nents,
339 hwif->sg_dma_direction);
340 hwif->sg_nents = 0;
341 }
342
343 return 0;
344 }
345
346 static void auide_dma_start(ide_drive_t *drive )
347 {
348 }
349
350
351 static void auide_dma_exec_cmd(ide_drive_t *drive, u8 command)
352 {
353 /* issue cmd to drive */
354 ide_execute_command(drive, command, &ide_dma_intr,
355 (2*WAIT_CMD), NULL);
356 }
357
358 static int auide_dma_setup(ide_drive_t *drive)
359 {
360 struct request *rq = HWGROUP(drive)->rq;
361
362 if (!auide_build_dmatable(drive)) {
363 ide_map_sg(drive, rq);
364 return 1;
365 }
366
367 drive->waiting_for_dma = 1;
368 return 0;
369 }
370
371 static int auide_dma_check(ide_drive_t *drive)
372 {
373 u8 speed = ide_max_dma_mode(drive);
374
375 if( dbdma_init_done == 0 ){
376 auide_hwif.white_list = ide_in_drive_list(drive->id,
377 dma_white_list);
378 auide_hwif.black_list = ide_in_drive_list(drive->id,
379 dma_black_list);
380 auide_hwif.drive = drive;
381 auide_ddma_init(&auide_hwif);
382 dbdma_init_done = 1;
383 }
384
385 /* Is the drive in our DMA black list? */
386
387 if ( auide_hwif.black_list ) {
388 drive->using_dma = 0;
389
390 /* Borrowed the warning message from ide-dma.c */
391
392 printk(KERN_WARNING "%s: Disabling DMA for %s (blacklisted)\n",
393 drive->name, drive->id->model);
394 }
395 else
396 drive->using_dma = 1;
397
398 if (drive->autodma && (speed & XFER_MODE) != XFER_PIO)
399 return 0;
400
401 return -1;
402 }
403
404 static int auide_dma_test_irq(ide_drive_t *drive)
405 {
406 if (drive->waiting_for_dma == 0)
407 printk(KERN_WARNING "%s: ide_dma_test_irq \
408 called while not waiting\n", drive->name);
409
410 /* If dbdma didn't execute the STOP command yet, the
411 * active bit is still set
412 */
413 drive->waiting_for_dma++;
414 if (drive->waiting_for_dma >= DMA_WAIT_TIMEOUT) {
415 printk(KERN_WARNING "%s: timeout waiting for ddma to \
416 complete\n", drive->name);
417 return 1;
418 }
419 udelay(10);
420 return 0;
421 }
422
423 static void auide_dma_host_on(ide_drive_t *drive)
424 {
425 }
426
427 static int auide_dma_on(ide_drive_t *drive)
428 {
429 drive->using_dma = 1;
430
431 return 0;
432 }
433
434 static void auide_dma_host_off(ide_drive_t *drive)
435 {
436 }
437
438 static void auide_dma_off_quietly(ide_drive_t *drive)
439 {
440 drive->using_dma = 0;
441 }
442
443 static void auide_dma_lost_irq(ide_drive_t *drive)
444 {
445 printk(KERN_ERR "%s: IRQ lost\n", drive->name);
446 }
447
448 static void auide_ddma_tx_callback(int irq, void *param)
449 {
450 _auide_hwif *ahwif = (_auide_hwif*)param;
451 ahwif->drive->waiting_for_dma = 0;
452 }
453
454 static void auide_ddma_rx_callback(int irq, void *param)
455 {
456 _auide_hwif *ahwif = (_auide_hwif*)param;
457 ahwif->drive->waiting_for_dma = 0;
458 }
459
460 #endif /* end CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA */
461
462 static void auide_init_dbdma_dev(dbdev_tab_t *dev, u32 dev_id, u32 tsize, u32 devwidth, u32 flags)
463 {
464 dev->dev_id = dev_id;
465 dev->dev_physaddr = (u32)AU1XXX_ATA_PHYS_ADDR;
466 dev->dev_intlevel = 0;
467 dev->dev_intpolarity = 0;
468 dev->dev_tsize = tsize;
469 dev->dev_devwidth = devwidth;
470 dev->dev_flags = flags;
471 }
472
473 #if defined(CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA)
474
475 static void auide_dma_timeout(ide_drive_t *drive)
476 {
477 ide_hwif_t *hwif = HWIF(drive);
478
479 printk(KERN_ERR "%s: DMA timeout occurred: ", drive->name);
480
481 if (hwif->ide_dma_test_irq(drive))
482 return;
483
484 hwif->ide_dma_end(drive);
485 }
486
487
488 static int auide_ddma_init(_auide_hwif *auide) {
489
490 dbdev_tab_t source_dev_tab, target_dev_tab;
491 u32 dev_id, tsize, devwidth, flags;
492 ide_hwif_t *hwif = auide->hwif;
493
494 dev_id = AU1XXX_ATA_DDMA_REQ;
495
496 if (auide->white_list || auide->black_list) {
497 tsize = 8;
498 devwidth = 32;
499 }
500 else {
501 tsize = 1;
502 devwidth = 16;
503
504 printk(KERN_ERR "au1xxx-ide: %s is not on ide driver whitelist.\n",auide_hwif.drive->id->model);
505 printk(KERN_ERR " please read 'Documentation/mips/AU1xxx_IDE.README'");
506 }
507
508 #ifdef IDE_AU1XXX_BURSTMODE
509 flags = DEV_FLAGS_SYNC | DEV_FLAGS_BURSTABLE;
510 #else
511 flags = DEV_FLAGS_SYNC;
512 #endif
513
514 /* setup dev_tab for tx channel */
515 auide_init_dbdma_dev( &source_dev_tab,
516 dev_id,
517 tsize, devwidth, DEV_FLAGS_OUT | flags);
518 auide->tx_dev_id = au1xxx_ddma_add_device( &source_dev_tab );
519
520 auide_init_dbdma_dev( &source_dev_tab,
521 dev_id,
522 tsize, devwidth, DEV_FLAGS_IN | flags);
523 auide->rx_dev_id = au1xxx_ddma_add_device( &source_dev_tab );
524
525 /* We also need to add a target device for the DMA */
526 auide_init_dbdma_dev( &target_dev_tab,
527 (u32)DSCR_CMD0_ALWAYS,
528 tsize, devwidth, DEV_FLAGS_ANYUSE);
529 auide->target_dev_id = au1xxx_ddma_add_device(&target_dev_tab);
530
531 /* Get a channel for TX */
532 auide->tx_chan = au1xxx_dbdma_chan_alloc(auide->target_dev_id,
533 auide->tx_dev_id,
534 auide_ddma_tx_callback,
535 (void*)auide);
536
537 /* Get a channel for RX */
538 auide->rx_chan = au1xxx_dbdma_chan_alloc(auide->rx_dev_id,
539 auide->target_dev_id,
540 auide_ddma_rx_callback,
541 (void*)auide);
542
543 auide->tx_desc_head = (void*)au1xxx_dbdma_ring_alloc(auide->tx_chan,
544 NUM_DESCRIPTORS);
545 auide->rx_desc_head = (void*)au1xxx_dbdma_ring_alloc(auide->rx_chan,
546 NUM_DESCRIPTORS);
547
548 hwif->dmatable_cpu = dma_alloc_coherent(auide->dev,
549 PRD_ENTRIES * PRD_BYTES, /* 1 Page */
550 &hwif->dmatable_dma, GFP_KERNEL);
551
552 au1xxx_dbdma_start( auide->tx_chan );
553 au1xxx_dbdma_start( auide->rx_chan );
554
555 return 0;
556 }
557 #else
558
559 static int auide_ddma_init( _auide_hwif *auide )
560 {
561 dbdev_tab_t source_dev_tab;
562 int flags;
563
564 #ifdef IDE_AU1XXX_BURSTMODE
565 flags = DEV_FLAGS_SYNC | DEV_FLAGS_BURSTABLE;
566 #else
567 flags = DEV_FLAGS_SYNC;
568 #endif
569
570 /* setup dev_tab for tx channel */
571 auide_init_dbdma_dev( &source_dev_tab,
572 (u32)DSCR_CMD0_ALWAYS,
573 8, 32, DEV_FLAGS_OUT | flags);
574 auide->tx_dev_id = au1xxx_ddma_add_device( &source_dev_tab );
575
576 auide_init_dbdma_dev( &source_dev_tab,
577 (u32)DSCR_CMD0_ALWAYS,
578 8, 32, DEV_FLAGS_IN | flags);
579 auide->rx_dev_id = au1xxx_ddma_add_device( &source_dev_tab );
580
581 /* Get a channel for TX */
582 auide->tx_chan = au1xxx_dbdma_chan_alloc(DSCR_CMD0_ALWAYS,
583 auide->tx_dev_id,
584 NULL,
585 (void*)auide);
586
587 /* Get a channel for RX */
588 auide->rx_chan = au1xxx_dbdma_chan_alloc(auide->rx_dev_id,
589 DSCR_CMD0_ALWAYS,
590 NULL,
591 (void*)auide);
592
593 auide->tx_desc_head = (void*)au1xxx_dbdma_ring_alloc(auide->tx_chan,
594 NUM_DESCRIPTORS);
595 auide->rx_desc_head = (void*)au1xxx_dbdma_ring_alloc(auide->rx_chan,
596 NUM_DESCRIPTORS);
597
598 au1xxx_dbdma_start( auide->tx_chan );
599 au1xxx_dbdma_start( auide->rx_chan );
600
601 return 0;
602 }
603 #endif
604
605 static void auide_setup_ports(hw_regs_t *hw, _auide_hwif *ahwif)
606 {
607 int i;
608 unsigned long *ata_regs = hw->io_ports;
609
610 /* FIXME? */
611 for (i = 0; i < IDE_CONTROL_OFFSET; i++) {
612 *ata_regs++ = ahwif->regbase + (i << AU1XXX_ATA_REG_OFFSET);
613 }
614
615 /* set the Alternative Status register */
616 *ata_regs = ahwif->regbase + (14 << AU1XXX_ATA_REG_OFFSET);
617 }
618
619 static int au_ide_probe(struct device *dev)
620 {
621 struct platform_device *pdev = to_platform_device(dev);
622 _auide_hwif *ahwif = &auide_hwif;
623 ide_hwif_t *hwif;
624 struct resource *res;
625 hw_regs_t *hw;
626 int ret = 0;
627
628 #if defined(CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA)
629 char *mode = "MWDMA2";
630 #elif defined(CONFIG_BLK_DEV_IDE_AU1XXX_PIO_DBDMA)
631 char *mode = "PIO+DDMA(offload)";
632 #endif
633
634 memset(&auide_hwif, 0, sizeof(_auide_hwif));
635 auide_hwif.dev = 0;
636
637 ahwif->dev = dev;
638 ahwif->irq = platform_get_irq(pdev, 0);
639
640 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
641
642 if (res == NULL) {
643 pr_debug("%s %d: no base address\n", DRV_NAME, pdev->id);
644 ret = -ENODEV;
645 goto out;
646 }
647 if (ahwif->irq < 0) {
648 pr_debug("%s %d: no IRQ\n", DRV_NAME, pdev->id);
649 ret = -ENODEV;
650 goto out;
651 }
652
653 if (!request_mem_region (res->start, res->end-res->start, pdev->name)) {
654 pr_debug("%s: request_mem_region failed\n", DRV_NAME);
655 ret = -EBUSY;
656 goto out;
657 }
658
659 ahwif->regbase = (u32)ioremap(res->start, res->end-res->start);
660 if (ahwif->regbase == 0) {
661 ret = -ENOMEM;
662 goto out;
663 }
664
665 /* FIXME: This might possibly break PCMCIA IDE devices */
666
667 hwif = &ide_hwifs[pdev->id];
668 hw = &hwif->hw;
669 hwif->irq = hw->irq = ahwif->irq;
670 hwif->chipset = ide_au1xxx;
671
672 auide_setup_ports(hw, ahwif);
673 memcpy(hwif->io_ports, hw->io_ports, sizeof(hwif->io_ports));
674
675 hwif->ultra_mask = 0x0; /* Disable Ultra DMA */
676 #ifdef CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA
677 hwif->mwdma_mask = 0x07; /* Multimode-2 DMA */
678 hwif->swdma_mask = 0x00;
679 #else
680 hwif->mwdma_mask = 0x0;
681 hwif->swdma_mask = 0x0;
682 #endif
683
684 hwif->pio_mask = ATA_PIO4;
685
686 hwif->noprobe = 0;
687 hwif->drives[0].unmask = 1;
688 hwif->drives[1].unmask = 1;
689
690 /* hold should be on in all cases */
691 hwif->hold = 1;
692
693 hwif->mmio = 1;
694
695 /* If the user has selected DDMA assisted copies,
696 then set up a few local I/O function entry points
697 */
698
699 #ifdef CONFIG_BLK_DEV_IDE_AU1XXX_PIO_DBDMA
700 hwif->INSW = auide_insw;
701 hwif->OUTSW = auide_outsw;
702 #endif
703
704 hwif->set_pio_mode = &au1xxx_set_pio_mode;
705 hwif->speedproc = &auide_tune_chipset;
706
707 #ifdef CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA
708 hwif->dma_off_quietly = &auide_dma_off_quietly;
709 hwif->dma_timeout = &auide_dma_timeout;
710
711 hwif->ide_dma_check = &auide_dma_check;
712 hwif->dma_exec_cmd = &auide_dma_exec_cmd;
713 hwif->dma_start = &auide_dma_start;
714 hwif->ide_dma_end = &auide_dma_end;
715 hwif->dma_setup = &auide_dma_setup;
716 hwif->ide_dma_test_irq = &auide_dma_test_irq;
717 hwif->dma_host_off = &auide_dma_host_off;
718 hwif->dma_host_on = &auide_dma_host_on;
719 hwif->dma_lost_irq = &auide_dma_lost_irq;
720 hwif->ide_dma_on = &auide_dma_on;
721
722 hwif->autodma = 1;
723 hwif->drives[0].autodma = hwif->autodma;
724 hwif->drives[1].autodma = hwif->autodma;
725 hwif->atapi_dma = 1;
726
727 #else /* !CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA */
728 hwif->autodma = 0;
729 hwif->channel = 0;
730 hwif->hold = 1;
731 hwif->select_data = 0; /* no chipset-specific code */
732 hwif->config_data = 0; /* no chipset-specific code */
733
734 hwif->drives[0].autodma = 0;
735 hwif->drives[0].autotune = 1; /* 1=autotune, 2=noautotune, 0=default */
736 #endif
737 hwif->drives[0].no_io_32bit = 1;
738
739 auide_hwif.hwif = hwif;
740 hwif->hwif_data = &auide_hwif;
741
742 #ifdef CONFIG_BLK_DEV_IDE_AU1XXX_PIO_DBDMA
743 auide_ddma_init(&auide_hwif);
744 dbdma_init_done = 1;
745 #endif
746
747 probe_hwif_init(hwif);
748
749 ide_proc_register_port(hwif);
750
751 dev_set_drvdata(dev, hwif);
752
753 printk(KERN_INFO "Au1xxx IDE(builtin) configured for %s\n", mode );
754
755 out:
756 return ret;
757 }
758
759 static int au_ide_remove(struct device *dev)
760 {
761 struct platform_device *pdev = to_platform_device(dev);
762 struct resource *res;
763 ide_hwif_t *hwif = dev_get_drvdata(dev);
764 _auide_hwif *ahwif = &auide_hwif;
765
766 ide_unregister(hwif - ide_hwifs);
767
768 iounmap((void *)ahwif->regbase);
769
770 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
771 release_mem_region(res->start, res->end - res->start);
772
773 return 0;
774 }
775
776 static struct device_driver au1200_ide_driver = {
777 .name = "au1200-ide",
778 .bus = &platform_bus_type,
779 .probe = au_ide_probe,
780 .remove = au_ide_remove,
781 };
782
783 static int __init au_ide_init(void)
784 {
785 return driver_register(&au1200_ide_driver);
786 }
787
788 static void __exit au_ide_exit(void)
789 {
790 driver_unregister(&au1200_ide_driver);
791 }
792
793 MODULE_LICENSE("GPL");
794 MODULE_DESCRIPTION("AU1200 IDE driver");
795
796 module_init(au_ide_init);
797 module_exit(au_ide_exit);
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