drivers/net/pcmcia/nmclan_cs.c

   1 /* ----------------------------------------------------------------------------
   2 Linux PCMCIA ethernet adapter driver for the New Media Ethernet LAN.
   3   nmclan_cs.c,v 0.16 1995/07/01 06:42:17 rpao Exp rpao
   4
   5   The Ethernet LAN uses the Advanced Micro Devices (AMD) Am79C940 Media
   6   Access Controller for Ethernet (MACE).  It is essentially the Am2150
   7   PCMCIA Ethernet card contained in the Am2150 Demo Kit.
   8
   9 Written by Roger C. Pao <rpao@paonet.org>
  10   Copyright 1995 Roger C. Pao
  11   Linux 2.5 cleanups Copyright Red Hat 2003
  12
  13   This software may be used and distributed according to the terms of
  14   the GNU General Public License.
  15
  16 Ported to Linux 1.3.* network driver environment by
  17   Matti Aarnio <mea@utu.fi>
  18
  19 References
  20
  21   Am2150 Technical Reference Manual, Revision 1.0, August 17, 1993
  22   Am79C940 (MACE) Data Sheet, 1994
  23   Am79C90 (C-LANCE) Data Sheet, 1994
  24   Linux PCMCIA Programmer's Guide v1.17
  25   /usr/src/linux/net/inet/dev.c, Linux kernel 1.2.8
  26
  27   Eric Mears, New Media Corporation
  28   Tom Pollard, New Media Corporation
  29   Dean Siasoyco, New Media Corporation
  30   Ken Lesniak, Silicon Graphics, Inc. <lesniak@boston.sgi.com>
  31   Donald Becker <becker@scyld.com>
  32   David Hinds <dahinds@users.sourceforge.net>
  33
  34   The Linux client driver is based on the 3c589_cs.c client driver by
  35   David Hinds.
  36
  37   The Linux network driver outline is based on the 3c589_cs.c driver,
  38   the 8390.c driver, and the example skeleton.c kernel code, which are
  39   by Donald Becker.
  40
  41   The Am2150 network driver hardware interface code is based on the
  42   OS/9000 driver for the New Media Ethernet LAN by Eric Mears.
  43
  44   Special thanks for testing and help in debugging this driver goes
  45   to Ken Lesniak.
  46
  47 -------------------------------------------------------------------------------
  48 Driver Notes and Issues
  49 -------------------------------------------------------------------------------
  50
  51 1. Developed on a Dell 320SLi
  52    PCMCIA Card Services 2.6.2
  53    Linux dell 1.2.10 #1 Thu Jun 29 20:23:41 PDT 1995 i386
  54
  55 2. rc.pcmcia may require loading pcmcia_core with io_speed=300:
  56    'insmod pcmcia_core.o io_speed=300'.
  57    This will avoid problems with fast systems which causes rx_framecnt
  58    to return random values.
  59
  60 3. If hot extraction does not work for you, use 'ifconfig eth0 down'
  61    before extraction.
  62
  63 4. There is a bad slow-down problem in this driver.
  64
  65 5. Future: Multicast processing.  In the meantime, do _not_ compile your
  66    kernel with multicast ip enabled.
  67
  68 -------------------------------------------------------------------------------
  69 History
  70 -------------------------------------------------------------------------------
  71 Log: nmclan_cs.c,v
  72  * 2.5.75-ac1 2003/07/11 Alan Cox <alan@redhat.com>
  73  * Fixed hang on card eject as we probe it
  74  * Cleaned up to use new style locking.
  75  *
  76  * Revision 0.16  1995/07/01  06:42:17  rpao
  77  * Bug fix: nmclan_reset() called CardServices incorrectly.
  78  *
  79  * Revision 0.15  1995/05/24  08:09:47  rpao
  80  * Re-implement MULTI_TX dev->tbusy handling.
  81  *
  82  * Revision 0.14  1995/05/23  03:19:30  rpao
  83  * Added, in nmclan_config(), "tuple.Attributes = 0;".
  84  * Modified MACE ID check to ignore chip revision level.
  85  * Avoid tx_free_frames race condition between _start_xmit and _interrupt.
  86  *
  87  * Revision 0.13  1995/05/18  05:56:34  rpao
  88  * Statistics changes.
  89  * Bug fix: nmclan_reset did not enable TX and RX: call restore_multicast_list.
  90  * Bug fix: mace_interrupt checks ~MACE_IMR_DEFAULT.  Fixes driver lockup.
  91  *
  92  * Revision 0.12  1995/05/14  00:12:23  rpao
  93  * Statistics overhaul.
  94  *
  95
  96 95/05/13 rpao   V0.10a
  97                 Bug fix: MACE statistics counters used wrong I/O ports.
  98                 Bug fix: mace_interrupt() needed to allow statistics to be
  99                 processed without RX or TX interrupts pending.
 100 95/05/11 rpao   V0.10
 101                 Multiple transmit request processing.
 102                 Modified statistics to use MACE counters where possible.
 103 95/05/10 rpao   V0.09 Bug fix: Must use IO_DATA_PATH_WIDTH_AUTO.
 104                 *Released
 105 95/05/10 rpao   V0.08
 106                 Bug fix: Make all non-exported functions private by using
 107                 static keyword.
 108                 Bug fix: Test IntrCnt _before_ reading MACE_IR.
 109 95/05/10 rpao   V0.07 Statistics.
 110 95/05/09 rpao   V0.06 Fix rx_framecnt problem by addition of PCIC wait states.
 111
 112 ---------------------------------------------------------------------------- */
 113
 114 #define DRV_NAME        "nmclan_cs"
 115 #define DRV_VERSION     "0.16"
 116
 117
 118 /* ----------------------------------------------------------------------------
 119 Conditional Compilation Options
 120 ---------------------------------------------------------------------------- */
 121
 122 #define MULTI_TX                        0
 123 #define RESET_ON_TIMEOUT                1
 124 #define TX_INTERRUPTABLE                1
 125 #define RESET_XILINX                    0
 126
 127 /* ----------------------------------------------------------------------------
 128 Include Files
 129 ---------------------------------------------------------------------------- */
 130
 131 #include <linux/module.h>
 132 #include <linux/kernel.h>
 133 #include <linux/init.h>
 134 #include <linux/ptrace.h>
 135 #include <linux/slab.h>
 136 #include <linux/string.h>
 137 #include <linux/timer.h>
 138 #include <linux/interrupt.h>
 139 #include <linux/in.h>
 140 #include <linux/delay.h>
 141 #include <linux/ethtool.h>
 142 #include <linux/netdevice.h>
 143 #include <linux/etherdevice.h>
 144 #include <linux/skbuff.h>
 145 #include <linux/if_arp.h>
 146 #include <linux/ioport.h>
 147 #include <linux/bitops.h>
 148
 149 #include <pcmcia/cs_types.h>
 150 #include <pcmcia/cs.h>
 151 #include <pcmcia/cisreg.h>
 152 #include <pcmcia/cistpl.h>
 153 #include <pcmcia/ds.h>
 154
 155 #include <asm/uaccess.h>
 156 #include <asm/io.h>
 157 #include <asm/system.h>
 158
 159 /* ----------------------------------------------------------------------------
 160 Defines
 161 ---------------------------------------------------------------------------- */
 162
 163 #define ETHER_ADDR_LEN                  ETH_ALEN
 164                                         /* 6 bytes in an Ethernet Address */
 165 #define MACE_LADRF_LEN                  8
 166                                         /* 8 bytes in Logical Address Filter */
 167
 168 /* Loop Control Defines */
 169 #define MACE_MAX_IR_ITERATIONS          10
 170 #define MACE_MAX_RX_ITERATIONS          12
 171         /*
 172         TBD: Dean brought this up, and I assumed the hardware would
 173         handle it:
 174
 175         If MACE_MAX_RX_ITERATIONS is > 1, rx_framecnt may still be
 176         non-zero when the isr exits.  We may not get another interrupt
 177         to process the remaining packets for some time.
 178         */
 179
 180 /*
 181 The Am2150 has a Xilinx XC3042 field programmable gate array (FPGA)
 182 which manages the interface between the MACE and the PCMCIA bus.  It
 183 also includes buffer management for the 32K x 8 SRAM to control up to
 184 four transmit and 12 receive frames at a time.
 185 */
 186 #define AM2150_MAX_TX_FRAMES            4
 187 #define AM2150_MAX_RX_FRAMES            12
 188
 189 /* Am2150 Ethernet Card I/O Mapping */
 190 #define AM2150_RCV                      0x00
 191 #define AM2150_XMT                      0x04
 192 #define AM2150_XMT_SKIP                 0x09
 193 #define AM2150_RCV_NEXT                 0x0A
 194 #define AM2150_RCV_FRAME_COUNT          0x0B
 195 #define AM2150_MACE_BANK                0x0C
 196 #define AM2150_MACE_BASE                0x10
 197
 198 /* MACE Registers */
 199 #define MACE_RCVFIFO                    0
 200 #define MACE_XMTFIFO                    1
 201 #define MACE_XMTFC                      2
 202 #define MACE_XMTFS                      3
 203 #define MACE_XMTRC                      4
 204 #define MACE_RCVFC                      5
 205 #define MACE_RCVFS                      6
 206 #define MACE_FIFOFC                     7
 207 #define MACE_IR                         8
 208 #define MACE_IMR                        9
 209 #define MACE_PR                         10
 210 #define MACE_BIUCC                      11
 211 #define MACE_FIFOCC                     12
 212 #define MACE_MACCC                      13
 213 #define MACE_PLSCC                      14
 214 #define MACE_PHYCC                      15
 215 #define MACE_CHIPIDL                    16
 216 #define MACE_CHIPIDH                    17
 217 #define MACE_IAC                        18
 218 /* Reserved */
 219 #define MACE_LADRF                      20
 220 #define MACE_PADR                       21
 221 /* Reserved */
 222 /* Reserved */
 223 #define MACE_MPC                        24
 224 /* Reserved */
 225 #define MACE_RNTPC                      26
 226 #define MACE_RCVCC                      27
 227 /* Reserved */
 228 #define MACE_UTR                        29
 229 #define MACE_RTR1                       30
 230 #define MACE_RTR2                       31
 231
 232 /* MACE Bit Masks */
 233 #define MACE_XMTRC_EXDEF                0x80
 234 #define MACE_XMTRC_XMTRC                0x0F
 235
 236 #define MACE_XMTFS_XMTSV                0x80
 237 #define MACE_XMTFS_UFLO                 0x40
 238 #define MACE_XMTFS_LCOL                 0x20
 239 #define MACE_XMTFS_MORE                 0x10
 240 #define MACE_XMTFS_ONE                  0x08
 241 #define MACE_XMTFS_DEFER                0x04
 242 #define MACE_XMTFS_LCAR                 0x02
 243 #define MACE_XMTFS_RTRY                 0x01
 244
 245 #define MACE_RCVFS_RCVSTS               0xF000
 246 #define MACE_RCVFS_OFLO                 0x8000
 247 #define MACE_RCVFS_CLSN                 0x4000
 248 #define MACE_RCVFS_FRAM                 0x2000
 249 #define MACE_RCVFS_FCS                  0x1000
 250
 251 #define MACE_FIFOFC_RCVFC               0xF0
 252 #define MACE_FIFOFC_XMTFC               0x0F
 253
 254 #define MACE_IR_JAB                     0x80
 255 #define MACE_IR_BABL                    0x40
 256 #define MACE_IR_CERR                    0x20
 257 #define MACE_IR_RCVCCO                  0x10
 258 #define MACE_IR_RNTPCO                  0x08
 259 #define MACE_IR_MPCO                    0x04
 260 #define MACE_IR_RCVINT                  0x02
 261 #define MACE_IR_XMTINT                  0x01
 262
 263 #define MACE_MACCC_PROM                 0x80
 264 #define MACE_MACCC_DXMT2PD              0x40
 265 #define MACE_MACCC_EMBA                 0x20
 266 #define MACE_MACCC_RESERVED             0x10
 267 #define MACE_MACCC_DRCVPA               0x08
 268 #define MACE_MACCC_DRCVBC               0x04
 269 #define MACE_MACCC_ENXMT                0x02
 270 #define MACE_MACCC_ENRCV                0x01
 271
 272 #define MACE_PHYCC_LNKFL                0x80
 273 #define MACE_PHYCC_DLNKTST              0x40
 274 #define MACE_PHYCC_REVPOL               0x20
 275 #define MACE_PHYCC_DAPC                 0x10
 276 #define MACE_PHYCC_LRT                  0x08
 277 #define MACE_PHYCC_ASEL                 0x04
 278 #define MACE_PHYCC_RWAKE                0x02
 279 #define MACE_PHYCC_AWAKE                0x01
 280
 281 #define MACE_IAC_ADDRCHG                0x80
 282 #define MACE_IAC_PHYADDR                0x04
 283 #define MACE_IAC_LOGADDR                0x02
 284
 285 #define MACE_UTR_RTRE                   0x80
 286 #define MACE_UTR_RTRD                   0x40
 287 #define MACE_UTR_RPA                    0x20
 288 #define MACE_UTR_FCOLL                  0x10
 289 #define MACE_UTR_RCVFCSE                0x08
 290 #define MACE_UTR_LOOP_INCL_MENDEC       0x06
 291 #define MACE_UTR_LOOP_NO_MENDEC         0x04
 292 #define MACE_UTR_LOOP_EXTERNAL          0x02
 293 #define MACE_UTR_LOOP_NONE              0x00
 294 #define MACE_UTR_RESERVED               0x01
 295
 296 /* Switch MACE register bank (only 0 and 1 are valid) */
 297 #define MACEBANK(win_num) outb((win_num), ioaddr + AM2150_MACE_BANK)
 298
 299 #define MACE_IMR_DEFAULT \
 300   (0xFF - \
 301     ( \
 302       MACE_IR_CERR | \
 303       MACE_IR_RCVCCO | \
 304       MACE_IR_RNTPCO | \
 305       MACE_IR_MPCO | \
 306       MACE_IR_RCVINT | \
 307       MACE_IR_XMTINT \
 308     ) \
 309   )
 310 #undef MACE_IMR_DEFAULT
 311 #define MACE_IMR_DEFAULT 0x00 /* New statistics handling: grab everything */
 312
 313 #define TX_TIMEOUT              ((400*HZ)/1000)
 314
 315 /* ----------------------------------------------------------------------------
 316 Type Definitions
 317 ---------------------------------------------------------------------------- */
 318
 319 typedef struct _mace_statistics {
 320     /* MACE_XMTFS */
 321     int xmtsv;
 322     int uflo;
 323     int lcol;
 324     int more;
 325     int one;
 326     int defer;
 327     int lcar;
 328     int rtry;
 329
 330     /* MACE_XMTRC */
 331     int exdef;
 332     int xmtrc;
 333
 334     /* RFS1--Receive Status (RCVSTS) */
 335     int oflo;
 336     int clsn;
 337     int fram;
 338     int fcs;
 339
 340     /* RFS2--Runt Packet Count (RNTPC) */
 341     int rfs_rntpc;
 342
 343     /* RFS3--Receive Collision Count (RCVCC) */
 344     int rfs_rcvcc;
 345
 346     /* MACE_IR */
 347     int jab;
 348     int babl;
 349     int cerr;
 350     int rcvcco;
 351     int rntpco;
 352     int mpco;
 353
 354     /* MACE_MPC */
 355     int mpc;
 356
 357     /* MACE_RNTPC */
 358     int rntpc;
 359
 360     /* MACE_RCVCC */
 361     int rcvcc;
 362 } mace_statistics;
 363
 364 typedef struct _mace_private {
 365         struct pcmcia_device    *p_dev;
 366     dev_node_t node;
 367     struct net_device_stats linux_stats; /* Linux statistics counters */
 368     mace_statistics mace_stats; /* MACE chip statistics counters */
 369
 370     /* restore_multicast_list() state variables */
 371     int multicast_ladrf[MACE_LADRF_LEN]; /* Logical address filter */
 372     int multicast_num_addrs;
 373
 374     char tx_free_frames; /* Number of free transmit frame buffers */
 375     char tx_irq_disabled; /* MACE TX interrupt disabled */
 376
 377     spinlock_t bank_lock; /* Must be held if you step off bank 0 */
 378 } mace_private;
 379
 380 /* ----------------------------------------------------------------------------
 381 Private Global Variables
 382 ---------------------------------------------------------------------------- */
 383
 384 #ifdef PCMCIA_DEBUG
 385 static char rcsid[] =
 386 "nmclan_cs.c,v 0.16 1995/07/01 06:42:17 rpao Exp rpao";
 387 static char *version =
 388 DRV_NAME " " DRV_VERSION " (Roger C. Pao)";
 389 #endif
 390
 391 static const char *if_names[]={
 392     "Auto", "10baseT", "BNC",
 393 };
 394
 395 /* ----------------------------------------------------------------------------
 396 Parameters
 397         These are the parameters that can be set during loading with
 398         'insmod'.
 399 ---------------------------------------------------------------------------- */
 400
 401 MODULE_DESCRIPTION("New Media PCMCIA ethernet driver");
 402 MODULE_LICENSE("GPL");
 403
 404 #define INT_MODULE_PARM(n, v) static int n = v; module_param(n, int, 0)
 405
 406 /* 0=auto, 1=10baseT, 2 = 10base2, default=auto */
 407 INT_MODULE_PARM(if_port, 0);
 408
 409 #ifdef PCMCIA_DEBUG
 410 INT_MODULE_PARM(pc_debug, PCMCIA_DEBUG);
 411 #define DEBUG(n, args...) if (pc_debug>(n)) printk(KERN_DEBUG args)
 412 #else
 413 #define DEBUG(n, args...)
 414 #endif
 415
 416 /* ----------------------------------------------------------------------------
 417 Function Prototypes
 418 ---------------------------------------------------------------------------- */
 419
 420 static int nmclan_config(struct pcmcia_device *link);
 421 static void nmclan_release(struct pcmcia_device *link);
 422
 423 static void nmclan_reset(struct net_device *dev);
 424 static int mace_config(struct net_device *dev, struct ifmap *map);
 425 static int mace_open(struct net_device *dev);
 426 static int mace_close(struct net_device *dev);
 427 static int mace_start_xmit(struct sk_buff *skb, struct net_device *dev);
 428 static void mace_tx_timeout(struct net_device *dev);
 429 static irqreturn_t mace_interrupt(int irq, void *dev_id);
 430 static struct net_device_stats *mace_get_stats(struct net_device *dev);
 431 static int mace_rx(struct net_device *dev, unsigned char RxCnt);
 432 static void restore_multicast_list(struct net_device *dev);
 433 static void set_multicast_list(struct net_device *dev);
 434 static const struct ethtool_ops netdev_ethtool_ops;
 435
 436
 437 static void nmclan_detach(struct pcmcia_device *p_dev);
 438
 439 /* ----------------------------------------------------------------------------
 440 nmclan_attach
 441         Creates an "instance" of the driver, allocating local data
 442         structures for one device.  The device is registered with Card
 443         Services.
 444 ---------------------------------------------------------------------------- */
 445
 446 static int nmclan_probe(struct pcmcia_device *link)
 447 {
 448     mace_private *lp;
 449     struct net_device *dev;
 450
 451     DEBUG(0, "nmclan_attach()\n");
 452     DEBUG(1, "%s\n", rcsid);
 453
 454     /* Create new ethernet device */
 455     dev = alloc_etherdev(sizeof(mace_private));
 456     if (!dev)
 457             return -ENOMEM;
 458     lp = netdev_priv(dev);
 459     lp->p_dev = link;
 460     link->priv = dev;
 461
 462     spin_lock_init(&lp->bank_lock);
 463     link->io.NumPorts1 = 32;
 464     link->io.Attributes1 = IO_DATA_PATH_WIDTH_AUTO;
 465     link->io.IOAddrLines = 5;
 466     link->irq.Attributes = IRQ_TYPE_EXCLUSIVE | IRQ_HANDLE_PRESENT;
 467     link->irq.IRQInfo1 = IRQ_LEVEL_ID;
 468     link->irq.Handler = &mace_interrupt;
 469     link->irq.Instance = dev;
 470     link->conf.Attributes = CONF_ENABLE_IRQ;
 471     link->conf.IntType = INT_MEMORY_AND_IO;
 472     link->conf.ConfigIndex = 1;
 473     link->conf.Present = PRESENT_OPTION;
 474
 475     lp->tx_free_frames=AM2150_MAX_TX_FRAMES;
 476
 477     dev->hard_start_xmit = &mace_start_xmit;
 478     dev->set_config = &mace_config;
 479     dev->get_stats = &mace_get_stats;
 480     dev->set_multicast_list = &set_multicast_list;
 481     SET_ETHTOOL_OPS(dev, &netdev_ethtool_ops);
 482     dev->open = &mace_open;
 483     dev->stop = &mace_close;
 484 #ifdef HAVE_TX_TIMEOUT
 485     dev->tx_timeout = mace_tx_timeout;
 486     dev->watchdog_timeo = TX_TIMEOUT;
 487 #endif
 488
 489     return nmclan_config(link);
 490 } /* nmclan_attach */
 491
 492 /* ----------------------------------------------------------------------------
 493 nmclan_detach
 494         This deletes a driver "instance".  The device is de-registered
 495         with Card Services.  If it has been released, all local data
 496         structures are freed.  Otherwise, the structures will be freed
 497         when the device is released.
 498 ---------------------------------------------------------------------------- */
 499
 500 static void nmclan_detach(struct pcmcia_device *link)
 501 {
 502     struct net_device *dev = link->priv;
 503
 504     DEBUG(0, "nmclan_detach(0x%p)\n", link);
 505
 506     if (link->dev_node)
 507         unregister_netdev(dev);
 508
 509     nmclan_release(link);
 510
 511     free_netdev(dev);
 512 } /* nmclan_detach */
 513
 514 /* ----------------------------------------------------------------------------
 515 mace_read
 516         Reads a MACE register.  This is bank independent; however, the
 517         caller must ensure that this call is not interruptable.  We are
 518         assuming that during normal operation, the MACE is always in
 519         bank 0.
 520 ---------------------------------------------------------------------------- */
 521 static int mace_read(mace_private *lp, kio_addr_t ioaddr, int reg)
 522 {
 523   int data = 0xFF;
 524   unsigned long flags;
 525
 526   switch (reg >> 4) {
 527     case 0: /* register 0-15 */
 528       data = inb(ioaddr + AM2150_MACE_BASE + reg);
 529       break;
 530     case 1: /* register 16-31 */
 531       spin_lock_irqsave(&lp->bank_lock, flags);
 532       MACEBANK(1);
 533       data = inb(ioaddr + AM2150_MACE_BASE + (reg & 0x0F));
 534       MACEBANK(0);
 535       spin_unlock_irqrestore(&lp->bank_lock, flags);
 536       break;
 537   }
 538   return (data & 0xFF);
 539 } /* mace_read */
 540
 541 /* ----------------------------------------------------------------------------
 542 mace_write
 543         Writes to a MACE register.  This is bank independent; however,
 544         the caller must ensure that this call is not interruptable.  We
 545         are assuming that during normal operation, the MACE is always in
 546         bank 0.
 547 ---------------------------------------------------------------------------- */
 548 static void mace_write(mace_private *lp, kio_addr_t ioaddr, int reg, int data)
 549 {
 550   unsigned long flags;
 551
 552   switch (reg >> 4) {
 553     case 0: /* register 0-15 */
 554       outb(data & 0xFF, ioaddr + AM2150_MACE_BASE + reg);
 555       break;
 556     case 1: /* register 16-31 */
 557       spin_lock_irqsave(&lp->bank_lock, flags);
 558       MACEBANK(1);
 559       outb(data & 0xFF, ioaddr + AM2150_MACE_BASE + (reg & 0x0F));
 560       MACEBANK(0);
 561       spin_unlock_irqrestore(&lp->bank_lock, flags);
 562       break;
 563   }
 564 } /* mace_write */
 565
 566 /* ----------------------------------------------------------------------------
 567 mace_init
 568         Resets the MACE chip.
 569 ---------------------------------------------------------------------------- */
 570 static int mace_init(mace_private *lp, kio_addr_t ioaddr, char *enet_addr)
 571 {
 572   int i;
 573   int ct = 0;
 574
 575   /* MACE Software reset */
 576   mace_write(lp, ioaddr, MACE_BIUCC, 1);
 577   while (mace_read(lp, ioaddr, MACE_BIUCC) & 0x01) {
 578     /* Wait for reset bit to be cleared automatically after <= 200ns */;
 579     if(++ct > 500)
 580     {
 581         printk(KERN_ERR "mace: reset failed, card removed ?\n");
 582         return -1;
 583     }
 584     udelay(1);
 585   }
 586   mace_write(lp, ioaddr, MACE_BIUCC, 0);
 587
 588   /* The Am2150 requires that the MACE FIFOs operate in burst mode. */
 589   mace_write(lp, ioaddr, MACE_FIFOCC, 0x0F);
 590
 591   mace_write(lp,ioaddr, MACE_RCVFC, 0); /* Disable Auto Strip Receive */
 592   mace_write(lp, ioaddr, MACE_IMR, 0xFF); /* Disable all interrupts until _open */
 593
 594   /*
 595    * Bit 2-1 PORTSEL[1-0] Port Select.
 596    * 00 AUI/10Base-2
 597    * 01 10Base-T
 598    * 10 DAI Port (reserved in Am2150)
 599    * 11 GPSI
 600    * For this card, only the first two are valid.
 601    * So, PLSCC should be set to
 602    * 0x00 for 10Base-2
 603    * 0x02 for 10Base-T
 604    * Or just set ASEL in PHYCC below!
 605    */
 606   switch (if_port) {
 607     case 1:
 608       mace_write(lp, ioaddr, MACE_PLSCC, 0x02);
 609       break;
 610     case 2:
 611       mace_write(lp, ioaddr, MACE_PLSCC, 0x00);
 612       break;
 613     default:
 614       mace_write(lp, ioaddr, MACE_PHYCC, /* ASEL */ 4);
 615       /* ASEL Auto Select.  When set, the PORTSEL[1-0] bits are overridden,
 616          and the MACE device will automatically select the operating media
 617          interface port. */
 618       break;
 619   }
 620
 621   mace_write(lp, ioaddr, MACE_IAC, MACE_IAC_ADDRCHG | MACE_IAC_PHYADDR);
 622   /* Poll ADDRCHG bit */
 623   ct = 0;
 624   while (mace_read(lp, ioaddr, MACE_IAC) & MACE_IAC_ADDRCHG)
 625   {
 626         if(++ ct > 500)
 627         {
 628                 printk(KERN_ERR "mace: ADDRCHG timeout, card removed ?\n");
 629                 return -1;
 630         }
 631   }
 632   /* Set PADR register */
 633   for (i = 0; i < ETHER_ADDR_LEN; i++)
 634     mace_write(lp, ioaddr, MACE_PADR, enet_addr[i]);
 635
 636   /* MAC Configuration Control Register should be written last */
 637   /* Let set_multicast_list set this. */
 638   /* mace_write(lp, ioaddr, MACE_MACCC, MACE_MACCC_ENXMT | MACE_MACCC_ENRCV); */
 639   mace_write(lp, ioaddr, MACE_MACCC, 0x00);
 640   return 0;
 641 } /* mace_init */
 642
 643 /* ----------------------------------------------------------------------------
 644 nmclan_config
 645         This routine is scheduled to run after a CARD_INSERTION event
 646         is received, to configure the PCMCIA socket, and to make the
 647         ethernet device available to the system.
 648 ---------------------------------------------------------------------------- */
 649
 650 #define CS_CHECK(fn, ret) \
 651   do { last_fn = (fn); if ((last_ret = (ret)) != 0) goto cs_failed; } while (0)
 652
 653 static int nmclan_config(struct pcmcia_device *link)
 654 {
 655   struct net_device *dev = link->priv;
 656   mace_private *lp = netdev_priv(dev);
 657   tuple_t tuple;
 658   u_char buf[64];
 659   int i, last_ret, last_fn;
 660   kio_addr_t ioaddr;
 661   DECLARE_MAC_BUF(mac);
 662
 663   DEBUG(0, "nmclan_config(0x%p)\n", link);
 664
 665   CS_CHECK(RequestIO, pcmcia_request_io(link, &link->io));
 666   CS_CHECK(RequestIRQ, pcmcia_request_irq(link, &link->irq));
 667   CS_CHECK(RequestConfiguration, pcmcia_request_configuration(link, &link->conf));
 668   dev->irq = link->irq.AssignedIRQ;
 669   dev->base_addr = link->io.BasePort1;
 670
 671   ioaddr = dev->base_addr;
 672
 673   /* Read the ethernet address from the CIS. */
 674   tuple.DesiredTuple = 0x80 /* CISTPL_CFTABLE_ENTRY_MISC */;
 675   tuple.TupleData = buf;
 676   tuple.TupleDataMax = 64;
 677   tuple.TupleOffset = 0;
 678   tuple.Attributes = 0;
 679   CS_CHECK(GetFirstTuple, pcmcia_get_first_tuple(link, &tuple));
 680   CS_CHECK(GetTupleData, pcmcia_get_tuple_data(link, &tuple));
 681   memcpy(dev->dev_addr, tuple.TupleData, ETHER_ADDR_LEN);
 682
 683   /* Verify configuration by reading the MACE ID. */
 684   {
 685     char sig[2];
 686
 687     sig[0] = mace_read(lp, ioaddr, MACE_CHIPIDL);
 688     sig[1] = mace_read(lp, ioaddr, MACE_CHIPIDH);
 689     if ((sig[0] == 0x40) && ((sig[1] & 0x0F) == 0x09)) {
 690       DEBUG(0, "nmclan_cs configured: mace id=%x %x\n",
 691             sig[0], sig[1]);
 692     } else {
 693       printk(KERN_NOTICE "nmclan_cs: mace id not found: %x %x should"
 694              " be 0x40 0x?9\n", sig[0], sig[1]);
 695       return -ENODEV;
 696     }
 697   }
 698
 699   if(mace_init(lp, ioaddr, dev->dev_addr) == -1)
 700         goto failed;
 701
 702   /* The if_port symbol can be set when the module is loaded */
 703   if (if_port <= 2)
 704     dev->if_port = if_port;
 705   else
 706     printk(KERN_NOTICE "nmclan_cs: invalid if_port requested\n");
 707
 708   link->dev_node = &lp->node;
 709   SET_NETDEV_DEV(dev, &handle_to_dev(link));
 710
 711   i = register_netdev(dev);
 712   if (i != 0) {
 713     printk(KERN_NOTICE "nmclan_cs: register_netdev() failed\n");
 714     link->dev_node = NULL;
 715     goto failed;
 716   }
 717
 718   strcpy(lp->node.dev_name, dev->name);
 719
 720   printk(KERN_INFO "%s: nmclan: port %#3lx, irq %d, %s port,"
 721          " hw_addr %s\n",
 722          dev->name, dev->base_addr, dev->irq, if_names[dev->if_port],
 723          print_mac(mac, dev->dev_addr));
 724   return 0;
 725
 726 cs_failed:
 727         cs_error(link, last_fn, last_ret);
 728 failed:
 729         nmclan_release(link);
 730         return -ENODEV;
 731 } /* nmclan_config */
 732
 733 /* ----------------------------------------------------------------------------
 734 nmclan_release
 735         After a card is removed, nmclan_release() will unregister the
 736         net device, and release the PCMCIA configuration.  If the device
 737         is still open, this will be postponed until it is closed.
 738 ---------------------------------------------------------------------------- */
 739 static void nmclan_release(struct pcmcia_device *link)
 740 {
 741         DEBUG(0, "nmclan_release(0x%p)\n", link);
 742         pcmcia_disable_device(link);
 743 }
 744
 745 static int nmclan_suspend(struct pcmcia_device *link)
 746 {
 747         struct net_device *dev = link->priv;
 748
 749         if (link->open)
 750                 netif_device_detach(dev);
 751
 752         return 0;
 753 }
 754
 755 static int nmclan_resume(struct pcmcia_device *link)
 756 {
 757         struct net_device *dev = link->priv;
 758
 759         if (link->open) {
 760                 nmclan_reset(dev);
 761                 netif_device_attach(dev);
 762         }
 763
 764         return 0;
 765 }
 766
 767
 768 /* ----------------------------------------------------------------------------
 769 nmclan_reset
 770         Reset and restore all of the Xilinx and MACE registers.
 771 ---------------------------------------------------------------------------- */
 772 static void nmclan_reset(struct net_device *dev)
 773 {
 774   mace_private *lp = netdev_priv(dev);
 775
 776 #if RESET_XILINX
 777   struct pcmcia_device *link = &lp->link;
 778   conf_reg_t reg;
 779   u_long OrigCorValue;
 780
 781   /* Save original COR value */
 782   reg.Function = 0;
 783   reg.Action = CS_READ;
 784   reg.Offset = CISREG_COR;
 785   reg.Value = 0;
 786   pcmcia_access_configuration_register(link, &reg);
 787   OrigCorValue = reg.Value;
 788
 789   /* Reset Xilinx */
 790   reg.Action = CS_WRITE;
 791   reg.Offset = CISREG_COR;
 792   DEBUG(1, "nmclan_reset: OrigCorValue=0x%lX, resetting...\n",
 793         OrigCorValue);
 794   reg.Value = COR_SOFT_RESET;
 795   pcmcia_access_configuration_register(link, &reg);
 796   /* Need to wait for 20 ms for PCMCIA to finish reset. */
 797
 798   /* Restore original COR configuration index */
 799   reg.Value = COR_LEVEL_REQ | (OrigCorValue & COR_CONFIG_MASK);
 800   pcmcia_access_configuration_register(link, &reg);
 801   /* Xilinx is now completely reset along with the MACE chip. */
 802   lp->tx_free_frames=AM2150_MAX_TX_FRAMES;
 803
 804 #endif /* #if RESET_XILINX */
 805
 806   /* Xilinx is now completely reset along with the MACE chip. */
 807   lp->tx_free_frames=AM2150_MAX_TX_FRAMES;
 808
 809   /* Reinitialize the MACE chip for operation. */
 810   mace_init(lp, dev->base_addr, dev->dev_addr);
 811   mace_write(lp, dev->base_addr, MACE_IMR, MACE_IMR_DEFAULT);
 812
 813   /* Restore the multicast list and enable TX and RX. */
 814   restore_multicast_list(dev);
 815 } /* nmclan_reset */
 816
 817 /* ----------------------------------------------------------------------------
 818 mace_config
 819         [Someone tell me what this is supposed to do?  Is if_port a defined
 820         standard?  If so, there should be defines to indicate 1=10Base-T,
 821         2=10Base-2, etc. including limited automatic detection.]
 822 ---------------------------------------------------------------------------- */
 823 static int mace_config(struct net_device *dev, struct ifmap *map)
 824 {
 825   if ((map->port != (u_char)(-1)) && (map->port != dev->if_port)) {
 826     if (map->port <= 2) {
 827       dev->if_port = map->port;
 828       printk(KERN_INFO "%s: switched to %s port\n", dev->name,
 829              if_names[dev->if_port]);
 830     } else
 831       return -EINVAL;
 832   }
 833   return 0;
 834 } /* mace_config */
 835
 836 /* ----------------------------------------------------------------------------
 837 mace_open
 838         Open device driver.
 839 ---------------------------------------------------------------------------- */
 840 static int mace_open(struct net_device *dev)
 841 {
 842   kio_addr_t ioaddr = dev->base_addr;
 843   mace_private *lp = netdev_priv(dev);
 844   struct pcmcia_device *link = lp->p_dev;
 845
 846   if (!pcmcia_dev_present(link))
 847     return -ENODEV;
 848
 849   link->open++;
 850
 851   MACEBANK(0);
 852
 853   netif_start_queue(dev);
 854   nmclan_reset(dev);
 855
 856   return 0; /* Always succeed */
 857 } /* mace_open */
 858
 859 /* ----------------------------------------------------------------------------
 860 mace_close
 861         Closes device driver.
 862 ---------------------------------------------------------------------------- */
 863 static int mace_close(struct net_device *dev)
 864 {
 865   kio_addr_t ioaddr = dev->base_addr;
 866   mace_private *lp = netdev_priv(dev);
 867   struct pcmcia_device *link = lp->p_dev;
 868
 869   DEBUG(2, "%s: shutting down ethercard.\n", dev->name);
 870
 871   /* Mask off all interrupts from the MACE chip. */
 872   outb(0xFF, ioaddr + AM2150_MACE_BASE + MACE_IMR);
 873
 874   link->open--;
 875   netif_stop_queue(dev);
 876
 877   return 0;
 878 } /* mace_close */
 879
 880 static void netdev_get_drvinfo(struct net_device *dev,
 881                                struct ethtool_drvinfo *info)
 882 {
 883         strcpy(info->driver, DRV_NAME);
 884         strcpy(info->version, DRV_VERSION);
 885         sprintf(info->bus_info, "PCMCIA 0x%lx", dev->base_addr);
 886 }
 887
 888 #ifdef PCMCIA_DEBUG
 889 static u32 netdev_get_msglevel(struct net_device *dev)
 890 {
 891         return pc_debug;
 892 }
 893
 894 static void netdev_set_msglevel(struct net_device *dev, u32 level)
 895 {
 896         pc_debug = level;
 897 }
 898 #endif /* PCMCIA_DEBUG */
 899
 900 static const struct ethtool_ops netdev_ethtool_ops = {
 901         .get_drvinfo            = netdev_get_drvinfo,
 902 #ifdef PCMCIA_DEBUG
 903         .get_msglevel           = netdev_get_msglevel,
 904         .set_msglevel           = netdev_set_msglevel,
 905 #endif /* PCMCIA_DEBUG */
 906 };
 907
 908 /* ----------------------------------------------------------------------------
 909 mace_start_xmit
 910         This routine begins the packet transmit function.  When completed,
 911         it will generate a transmit interrupt.
 912
 913         According to /usr/src/linux/net/inet/dev.c, if _start_xmit
 914         returns 0, the "packet is now solely the responsibility of the
 915         driver."  If _start_xmit returns non-zero, the "transmission
 916         failed, put skb back into a list."
 917 ---------------------------------------------------------------------------- */
 918
 919 static void mace_tx_timeout(struct net_device *dev)
 920 {
 921   mace_private *lp = netdev_priv(dev);
 922   struct pcmcia_device *link = lp->p_dev;
 923
 924   printk(KERN_NOTICE "%s: transmit timed out -- ", dev->name);
 925 #if RESET_ON_TIMEOUT
 926   printk("resetting card\n");
 927   pcmcia_reset_card(link, NULL);
 928 #else /* #if RESET_ON_TIMEOUT */
 929   printk("NOT resetting card\n");
 930 #endif /* #if RESET_ON_TIMEOUT */
 931   dev->trans_start = jiffies;
 932   netif_wake_queue(dev);
 933 }
 934
 935 static int mace_start_xmit(struct sk_buff *skb, struct net_device *dev)
 936 {
 937   mace_private *lp = netdev_priv(dev);
 938   kio_addr_t ioaddr = dev->base_addr;
 939
 940   netif_stop_queue(dev);
 941
 942   DEBUG(3, "%s: mace_start_xmit(length = %ld) called.\n",
 943         dev->name, (long)skb->len);
 944
 945 #if (!TX_INTERRUPTABLE)
 946   /* Disable MACE TX interrupts. */
 947   outb(MACE_IMR_DEFAULT | MACE_IR_XMTINT,
 948     ioaddr + AM2150_MACE_BASE + MACE_IMR);
 949   lp->tx_irq_disabled=1;
 950 #endif /* #if (!TX_INTERRUPTABLE) */
 951
 952   {
 953     /* This block must not be interrupted by another transmit request!
 954        mace_tx_timeout will take care of timer-based retransmissions from
 955        the upper layers.  The interrupt handler is guaranteed never to
 956        service a transmit interrupt while we are in here.
 957     */
 958
 959     lp->linux_stats.tx_bytes += skb->len;
 960     lp->tx_free_frames--;
 961
 962     /* WARNING: Write the _exact_ number of bytes written in the header! */
 963     /* Put out the word header [must be an outw()] . . . */
 964     outw(skb->len, ioaddr + AM2150_XMT);
 965     /* . . . and the packet [may be any combination of outw() and outb()] */
 966     outsw(ioaddr + AM2150_XMT, skb->data, skb->len >> 1);
 967     if (skb->len & 1) {
 968       /* Odd byte transfer */
 969       outb(skb->data[skb->len-1], ioaddr + AM2150_XMT);
 970     }
 971
 972     dev->trans_start = jiffies;
 973
 974 #if MULTI_TX
 975     if (lp->tx_free_frames > 0)
 976       netif_start_queue(dev);
 977 #endif /* #if MULTI_TX */
 978   }
 979
 980 #if (!TX_INTERRUPTABLE)
 981   /* Re-enable MACE TX interrupts. */
 982   lp->tx_irq_disabled=0;
 983   outb(MACE_IMR_DEFAULT, ioaddr + AM2150_MACE_BASE + MACE_IMR);
 984 #endif /* #if (!TX_INTERRUPTABLE) */
 985
 986   dev_kfree_skb(skb);
 987
 988   return 0;
 989 } /* mace_start_xmit */
 990
 991 /* ----------------------------------------------------------------------------
 992 mace_interrupt
 993         The interrupt handler.
 994 ---------------------------------------------------------------------------- */
 995 static irqreturn_t mace_interrupt(int irq, void *dev_id)
 996 {
 997   struct net_device *dev = (struct net_device *) dev_id;
 998   mace_private *lp = netdev_priv(dev);
 999   kio_addr_t ioaddr;
1000   int status;
1001   int IntrCnt = MACE_MAX_IR_ITERATIONS;
1002
1003   if (dev == NULL) {
1004     DEBUG(2, "mace_interrupt(): irq 0x%X for unknown device.\n",
1005           irq);
1006     return IRQ_NONE;
1007   }
1008
1009   ioaddr = dev->base_addr;
1010
1011   if (lp->tx_irq_disabled) {
1012     printk(
1013       (lp->tx_irq_disabled?
1014        KERN_NOTICE "%s: Interrupt with tx_irq_disabled "
1015        "[isr=%02X, imr=%02X]\n":
1016        KERN_NOTICE "%s: Re-entering the interrupt handler "
1017        "[isr=%02X, imr=%02X]\n"),
1018       dev->name,
1019       inb(ioaddr + AM2150_MACE_BASE + MACE_IR),
1020       inb(ioaddr + AM2150_MACE_BASE + MACE_IMR)
1021     );
1022     /* WARNING: MACE_IR has been read! */
1023     return IRQ_NONE;
1024   }
1025
1026   if (!netif_device_present(dev)) {
1027     DEBUG(2, "%s: interrupt from dead card\n", dev->name);
1028     return IRQ_NONE;
1029   }
1030
1031   do {
1032     /* WARNING: MACE_IR is a READ/CLEAR port! */
1033     status = inb(ioaddr + AM2150_MACE_BASE + MACE_IR);
1034
1035     DEBUG(3, "mace_interrupt: irq 0x%X status 0x%X.\n", irq, status);
1036
1037     if (status & MACE_IR_RCVINT) {
1038       mace_rx(dev, MACE_MAX_RX_ITERATIONS);
1039     }
1040
1041     if (status & MACE_IR_XMTINT) {
1042       unsigned char fifofc;
1043       unsigned char xmtrc;
1044       unsigned char xmtfs;
1045
1046       fifofc = inb(ioaddr + AM2150_MACE_BASE + MACE_FIFOFC);
1047       if ((fifofc & MACE_FIFOFC_XMTFC)==0) {
1048         lp->linux_stats.tx_errors++;
1049         outb(0xFF, ioaddr + AM2150_XMT_SKIP);
1050       }
1051
1052       /* Transmit Retry Count (XMTRC, reg 4) */
1053       xmtrc = inb(ioaddr + AM2150_MACE_BASE + MACE_XMTRC);
1054       if (xmtrc & MACE_XMTRC_EXDEF) lp->mace_stats.exdef++;
1055       lp->mace_stats.xmtrc += (xmtrc & MACE_XMTRC_XMTRC);
1056
1057       if (
1058         (xmtfs = inb(ioaddr + AM2150_MACE_BASE + MACE_XMTFS)) &
1059         MACE_XMTFS_XMTSV /* Transmit Status Valid */
1060       ) {
1061         lp->mace_stats.xmtsv++;
1062
1063         if (xmtfs & ~MACE_XMTFS_XMTSV) {
1064           if (xmtfs & MACE_XMTFS_UFLO) {
1065             /* Underflow.  Indicates that the Transmit FIFO emptied before
1066                the end of frame was reached. */
1067             lp->mace_stats.uflo++;
1068           }
1069           if (xmtfs & MACE_XMTFS_LCOL) {
1070             /* Late Collision */
1071             lp->mace_stats.lcol++;
1072           }
1073           if (xmtfs & MACE_XMTFS_MORE) {
1074             /* MORE than one retry was needed */
1075             lp->mace_stats.more++;
1076           }
1077           if (xmtfs & MACE_XMTFS_ONE) {
1078             /* Exactly ONE retry occurred */
1079             lp->mace_stats.one++;
1080           }
1081           if (xmtfs & MACE_XMTFS_DEFER) {
1082             /* Transmission was defered */
1083             lp->mace_stats.defer++;
1084           }
1085           if (xmtfs & MACE_XMTFS_LCAR) {
1086             /* Loss of carrier */
1087             lp->mace_stats.lcar++;
1088           }
1089           if (xmtfs & MACE_XMTFS_RTRY) {
1090             /* Retry error: transmit aborted after 16 attempts */
1091             lp->mace_stats.rtry++;
1092           }
1093         } /* if (xmtfs & ~MACE_XMTFS_XMTSV) */
1094
1095       } /* if (xmtfs & MACE_XMTFS_XMTSV) */
1096
1097       lp->linux_stats.tx_packets++;
1098       lp->tx_free_frames++;
1099       netif_wake_queue(dev);
1100     } /* if (status & MACE_IR_XMTINT) */
1101
1102     if (status & ~MACE_IMR_DEFAULT & ~MACE_IR_RCVINT & ~MACE_IR_XMTINT) {
1103       if (status & MACE_IR_JAB) {
1104         /* Jabber Error.  Excessive transmit duration (20-150ms). */
1105         lp->mace_stats.jab++;
1106       }
1107       if (status & MACE_IR_BABL) {
1108         /* Babble Error.  >1518 bytes transmitted. */
1109         lp->mace_stats.babl++;
1110       }
1111       if (status & MACE_IR_CERR) {
1112         /* Collision Error.  CERR indicates the absence of the
1113            Signal Quality Error Test message after a packet
1114            transmission. */
1115         lp->mace_stats.cerr++;
1116       }
1117       if (status & MACE_IR_RCVCCO) {
1118         /* Receive Collision Count Overflow; */
1119         lp->mace_stats.rcvcco++;
1120       }
1121       if (status & MACE_IR_RNTPCO) {
1122         /* Runt Packet Count Overflow */
1123         lp->mace_stats.rntpco++;
1124       }
1125       if (status & MACE_IR_MPCO) {
1126         /* Missed Packet Count Overflow */
1127         lp->mace_stats.mpco++;
1128       }
1129     } /* if (status & ~MACE_IMR_DEFAULT & ~MACE_IR_RCVINT & ~MACE_IR_XMTINT) */
1130
1131   } while ((status & ~MACE_IMR_DEFAULT) && (--IntrCnt));
1132
1133   return IRQ_HANDLED;
1134 } /* mace_interrupt */
1135
1136 /* ----------------------------------------------------------------------------
1137 mace_rx
1138         Receives packets.
1139 ---------------------------------------------------------------------------- */
1140 static int mace_rx(struct net_device *dev, unsigned char RxCnt)
1141 {
1142   mace_private *lp = netdev_priv(dev);
1143   kio_addr_t ioaddr = dev->base_addr;
1144   unsigned char rx_framecnt;
1145   unsigned short rx_status;
1146
1147   while (
1148     ((rx_framecnt = inb(ioaddr + AM2150_RCV_FRAME_COUNT)) > 0) &&
1149     (rx_framecnt <= 12) && /* rx_framecnt==0xFF if card is extracted. */
1150     (RxCnt--)
1151   ) {
1152     rx_status = inw(ioaddr + AM2150_RCV);
1153
1154     DEBUG(3, "%s: in mace_rx(), framecnt 0x%X, rx_status"
1155           " 0x%X.\n", dev->name, rx_framecnt, rx_status);
1156
1157     if (rx_status & MACE_RCVFS_RCVSTS) { /* Error, update stats. */
1158       lp->linux_stats.rx_errors++;
1159       if (rx_status & MACE_RCVFS_OFLO) {
1160         lp->mace_stats.oflo++;
1161       }
1162       if (rx_status & MACE_RCVFS_CLSN) {
1163         lp->mace_stats.clsn++;
1164       }
1165       if (rx_status & MACE_RCVFS_FRAM) {
1166         lp->mace_stats.fram++;
1167       }
1168       if (rx_status & MACE_RCVFS_FCS) {
1169         lp->mace_stats.fcs++;
1170       }
1171     } else {
1172       short pkt_len = (rx_status & ~MACE_RCVFS_RCVSTS) - 4;
1173         /* Auto Strip is off, always subtract 4 */
1174       struct sk_buff *skb;
1175
1176       lp->mace_stats.rfs_rntpc += inb(ioaddr + AM2150_RCV);
1177         /* runt packet count */
1178       lp->mace_stats.rfs_rcvcc += inb(ioaddr + AM2150_RCV);
1179         /* rcv collision count */
1180
1181       DEBUG(3, "    receiving packet size 0x%X rx_status"
1182             " 0x%X.\n", pkt_len, rx_status);
1183
1184       skb = dev_alloc_skb(pkt_len+2);
1185
1186       if (skb != NULL) {
1187         skb_reserve(skb, 2);
1188         insw(ioaddr + AM2150_RCV, skb_put(skb, pkt_len), pkt_len>>1);
1189         if (pkt_len & 1)
1190             *(skb_tail_pointer(skb) - 1) = inb(ioaddr + AM2150_RCV);
1191         skb->protocol = eth_type_trans(skb, dev);
1192
1193         netif_rx(skb); /* Send the packet to the upper (protocol) layers. */
1194
1195         dev->last_rx = jiffies;
1196         lp->linux_stats.rx_packets++;
1197         lp->linux_stats.rx_bytes += pkt_len;
1198         outb(0xFF, ioaddr + AM2150_RCV_NEXT); /* skip to next frame */
1199         continue;
1200       } else {
1201         DEBUG(1, "%s: couldn't allocate a sk_buff of size"
1202               " %d.\n", dev->name, pkt_len);
1203         lp->linux_stats.rx_dropped++;
1204       }
1205     }
1206     outb(0xFF, ioaddr + AM2150_RCV_NEXT); /* skip to next frame */
1207   } /* while */
1208
1209   return 0;
1210 } /* mace_rx */
1211
1212 /* ----------------------------------------------------------------------------
1213 pr_linux_stats
1214 ---------------------------------------------------------------------------- */
1215 static void pr_linux_stats(struct net_device_stats *pstats)
1216 {
1217   DEBUG(2, "pr_linux_stats\n");
1218   DEBUG(2, " rx_packets=%-7ld        tx_packets=%ld\n",
1219         (long)pstats->rx_packets, (long)pstats->tx_packets);
1220   DEBUG(2, " rx_errors=%-7ld         tx_errors=%ld\n",
1221         (long)pstats->rx_errors, (long)pstats->tx_errors);
1222   DEBUG(2, " rx_dropped=%-7ld        tx_dropped=%ld\n",
1223         (long)pstats->rx_dropped, (long)pstats->tx_dropped);
1224   DEBUG(2, " multicast=%-7ld         collisions=%ld\n",
1225         (long)pstats->multicast, (long)pstats->collisions);
1226
1227   DEBUG(2, " rx_length_errors=%-7ld  rx_over_errors=%ld\n",
1228         (long)pstats->rx_length_errors, (long)pstats->rx_over_errors);
1229   DEBUG(2, " rx_crc_errors=%-7ld     rx_frame_errors=%ld\n",
1230         (long)pstats->rx_crc_errors, (long)pstats->rx_frame_errors);
1231   DEBUG(2, " rx_fifo_errors=%-7ld    rx_missed_errors=%ld\n",
1232         (long)pstats->rx_fifo_errors, (long)pstats->rx_missed_errors);
1233
1234   DEBUG(2, " tx_aborted_errors=%-7ld tx_carrier_errors=%ld\n",
1235         (long)pstats->tx_aborted_errors, (long)pstats->tx_carrier_errors);
1236   DEBUG(2, " tx_fifo_errors=%-7ld    tx_heartbeat_errors=%ld\n",
1237         (long)pstats->tx_fifo_errors, (long)pstats->tx_heartbeat_errors);
1238   DEBUG(2, " tx_window_errors=%ld\n",
1239         (long)pstats->tx_window_errors);
1240 } /* pr_linux_stats */
1241
1242 /* ----------------------------------------------------------------------------
1243 pr_mace_stats
1244 ---------------------------------------------------------------------------- */
1245 static void pr_mace_stats(mace_statistics *pstats)
1246 {
1247   DEBUG(2, "pr_mace_stats\n");
1248
1249   DEBUG(2, " xmtsv=%-7d             uflo=%d\n",
1250         pstats->xmtsv, pstats->uflo);
1251   DEBUG(2, " lcol=%-7d              more=%d\n",
1252         pstats->lcol, pstats->more);
1253   DEBUG(2, " one=%-7d               defer=%d\n",
1254         pstats->one, pstats->defer);
1255   DEBUG(2, " lcar=%-7d              rtry=%d\n",
1256         pstats->lcar, pstats->rtry);
1257
1258   /* MACE_XMTRC */
1259   DEBUG(2, " exdef=%-7d             xmtrc=%d\n",
1260         pstats->exdef, pstats->xmtrc);
1261
1262   /* RFS1--Receive Status (RCVSTS) */
1263   DEBUG(2, " oflo=%-7d              clsn=%d\n",
1264         pstats->oflo, pstats->clsn);
1265   DEBUG(2, " fram=%-7d              fcs=%d\n",
1266         pstats->fram, pstats->fcs);
1267
1268   /* RFS2--Runt Packet Count (RNTPC) */
1269   /* RFS3--Receive Collision Count (RCVCC) */
1270   DEBUG(2, " rfs_rntpc=%-7d         rfs_rcvcc=%d\n",
1271         pstats->rfs_rntpc, pstats->rfs_rcvcc);
1272
1273   /* MACE_IR */
1274   DEBUG(2, " jab=%-7d               babl=%d\n",
1275         pstats->jab, pstats->babl);
1276   DEBUG(2, " cerr=%-7d              rcvcco=%d\n",
1277         pstats->cerr, pstats->rcvcco);
1278   DEBUG(2, " rntpco=%-7d            mpco=%d\n",
1279         pstats->rntpco, pstats->mpco);
1280
1281   /* MACE_MPC */
1282   DEBUG(2, " mpc=%d\n", pstats->mpc);
1283
1284   /* MACE_RNTPC */
1285   DEBUG(2, " rntpc=%d\n", pstats->rntpc);
1286
1287   /* MACE_RCVCC */
1288   DEBUG(2, " rcvcc=%d\n", pstats->rcvcc);
1289
1290 } /* pr_mace_stats */
1291
1292 /* ----------------------------------------------------------------------------
1293 update_stats
1294         Update statistics.  We change to register window 1, so this
1295         should be run single-threaded if the device is active. This is
1296         expected to be a rare operation, and it's simpler for the rest
1297         of the driver to assume that window 0 is always valid rather
1298         than use a special window-state variable.
1299
1300         oflo & uflo should _never_ occur since it would mean the Xilinx
1301         was not able to transfer data between the MACE FIFO and the
1302         card's SRAM fast enough.  If this happens, something is
1303         seriously wrong with the hardware.
1304 ---------------------------------------------------------------------------- */
1305 static void update_stats(kio_addr_t ioaddr, struct net_device *dev)
1306 {
1307   mace_private *lp = netdev_priv(dev);
1308
1309   lp->mace_stats.rcvcc += mace_read(lp, ioaddr, MACE_RCVCC);
1310   lp->mace_stats.rntpc += mace_read(lp, ioaddr, MACE_RNTPC);
1311   lp->mace_stats.mpc += mace_read(lp, ioaddr, MACE_MPC);
1312   /* At this point, mace_stats is fully updated for this call.
1313      We may now update the linux_stats. */
1314
1315   /* The MACE has no equivalent for linux_stats field which are commented
1316      out. */
1317
1318   /* lp->linux_stats.multicast; */
1319   lp->linux_stats.collisions =
1320     lp->mace_stats.rcvcco * 256 + lp->mace_stats.rcvcc;
1321     /* Collision: The MACE may retry sending a packet 15 times
1322        before giving up.  The retry count is in XMTRC.
1323        Does each retry constitute a collision?
1324        If so, why doesn't the RCVCC record these collisions? */
1325
1326   /* detailed rx_errors: */
1327   lp->linux_stats.rx_length_errors =
1328     lp->mace_stats.rntpco * 256 + lp->mace_stats.rntpc;
1329   /* lp->linux_stats.rx_over_errors */
1330   lp->linux_stats.rx_crc_errors = lp->mace_stats.fcs;
1331   lp->linux_stats.rx_frame_errors = lp->mace_stats.fram;
1332   lp->linux_stats.rx_fifo_errors = lp->mace_stats.oflo;
1333   lp->linux_stats.rx_missed_errors =
1334     lp->mace_stats.mpco * 256 + lp->mace_stats.mpc;
1335
1336   /* detailed tx_errors */
1337   lp->linux_stats.tx_aborted_errors = lp->mace_stats.rtry;
1338   lp->linux_stats.tx_carrier_errors = lp->mace_stats.lcar;
1339     /* LCAR usually results from bad cabling. */
1340   lp->linux_stats.tx_fifo_errors = lp->mace_stats.uflo;
1341   lp->linux_stats.tx_heartbeat_errors = lp->mace_stats.cerr;
1342   /* lp->linux_stats.tx_window_errors; */
1343
1344   return;
1345 } /* update_stats */
1346
1347 /* ----------------------------------------------------------------------------
1348 mace_get_stats
1349         Gathers ethernet statistics from the MACE chip.
1350 ---------------------------------------------------------------------------- */
1351 static struct net_device_stats *mace_get_stats(struct net_device *dev)
1352 {
1353   mace_private *lp = netdev_priv(dev);
1354
1355   update_stats(dev->base_addr, dev);
1356
1357   DEBUG(1, "%s: updating the statistics.\n", dev->name);
1358   pr_linux_stats(&lp->linux_stats);
1359   pr_mace_stats(&lp->mace_stats);
1360
1361   return &lp->linux_stats;
1362 } /* net_device_stats */
1363
1364 /* ----------------------------------------------------------------------------
1365 updateCRC
1366         Modified from Am79C90 data sheet.
1367 ---------------------------------------------------------------------------- */
1368
1369 #ifdef BROKEN_MULTICAST
1370
1371 static void updateCRC(int *CRC, int bit)
1372 {
1373   int poly[]={
1374     1,1,1,0, 1,1,0,1,
1375     1,0,1,1, 1,0,0,0,
1376     1,0,0,0, 0,0,1,1,
1377     0,0,1,0, 0,0,0,0
1378   }; /* CRC polynomial.  poly[n] = coefficient of the x**n term of the
1379         CRC generator polynomial. */
1380
1381   int j;
1382
1383   /* shift CRC and control bit (CRC[32]) */
1384   for (j = 32; j > 0; j--)
1385     CRC[j] = CRC[j-1];
1386   CRC[0] = 0;
1387
1388   /* If bit XOR(control bit) = 1, set CRC = CRC XOR polynomial. */
1389   if (bit ^ CRC[32])
1390     for (j = 0; j < 32; j++)
1391       CRC[j] ^= poly[j];
1392 } /* updateCRC */
1393
1394 /* ----------------------------------------------------------------------------
1395 BuildLAF
1396         Build logical address filter.
1397         Modified from Am79C90 data sheet.
1398
1399 Input
1400         ladrf: logical address filter (contents initialized to 0)
1401         adr: ethernet address
1402 ---------------------------------------------------------------------------- */
1403 static void BuildLAF(int *ladrf, int *adr)
1404 {
1405   int CRC[33]={1}; /* CRC register, 1 word/bit + extra control bit */
1406
1407   int i, byte; /* temporary array indices */
1408   int hashcode; /* the output object */
1409
1410   CRC[32]=0;
1411
1412   for (byte = 0; byte < 6; byte++)
1413     for (i = 0; i < 8; i++)
1414       updateCRC(CRC, (adr[byte] >> i) & 1);
1415
1416   hashcode = 0;
1417   for (i = 0; i < 6; i++)
1418     hashcode = (hashcode << 1) + CRC[i];
1419
1420   byte = hashcode >> 3;
1421   ladrf[byte] |= (1 << (hashcode & 7));
1422
1423 #ifdef PCMCIA_DEBUG
1424   if (pc_debug > 2) {
1425     printk(KERN_DEBUG "    adr =");
1426     for (i = 0; i < 6; i++)
1427       printk(" %02X", adr[i]);
1428     printk("\n" KERN_DEBUG "    hashcode = %d(decimal), ladrf[0:63]"
1429            " =", hashcode);
1430     for (i = 0; i < 8; i++)
1431       printk(" %02X", ladrf[i]);
1432     printk("\n");
1433   }
1434 #endif
1435 } /* BuildLAF */
1436
1437 /* ----------------------------------------------------------------------------
1438 restore_multicast_list
1439         Restores the multicast filter for MACE chip to the last
1440         set_multicast_list() call.
1441
1442 Input
1443         multicast_num_addrs
1444         multicast_ladrf[]
1445 ---------------------------------------------------------------------------- */
1446 static void restore_multicast_list(struct net_device *dev)
1447 {
1448   mace_private *lp = netdev_priv(dev);
1449   int num_addrs = lp->multicast_num_addrs;
1450   int *ladrf = lp->multicast_ladrf;
1451   kio_addr_t ioaddr = dev->base_addr;
1452   int i;
1453
1454   DEBUG(2, "%s: restoring Rx mode to %d addresses.\n",
1455         dev->name, num_addrs);
1456
1457   if (num_addrs > 0) {
1458
1459     DEBUG(1, "Attempt to restore multicast list detected.\n");
1460
1461     mace_write(lp, ioaddr, MACE_IAC, MACE_IAC_ADDRCHG | MACE_IAC_LOGADDR);
1462     /* Poll ADDRCHG bit */
1463     while (mace_read(lp, ioaddr, MACE_IAC) & MACE_IAC_ADDRCHG)
1464       ;
1465     /* Set LADRF register */
1466     for (i = 0; i < MACE_LADRF_LEN; i++)
1467       mace_write(lp, ioaddr, MACE_LADRF, ladrf[i]);
1468
1469     mace_write(lp, ioaddr, MACE_UTR, MACE_UTR_RCVFCSE | MACE_UTR_LOOP_EXTERNAL);
1470     mace_write(lp, ioaddr, MACE_MACCC, MACE_MACCC_ENXMT | MACE_MACCC_ENRCV);
1471
1472   } else if (num_addrs < 0) {
1473
1474     /* Promiscuous mode: receive all packets */
1475     mace_write(lp, ioaddr, MACE_UTR, MACE_UTR_LOOP_EXTERNAL);
1476     mace_write(lp, ioaddr, MACE_MACCC,
1477       MACE_MACCC_PROM | MACE_MACCC_ENXMT | MACE_MACCC_ENRCV
1478     );
1479
1480   } else {
1481
1482     /* Normal mode */
1483     mace_write(lp, ioaddr, MACE_UTR, MACE_UTR_LOOP_EXTERNAL);
1484     mace_write(lp, ioaddr, MACE_MACCC, MACE_MACCC_ENXMT | MACE_MACCC_ENRCV);
1485
1486   }
1487 } /* restore_multicast_list */
1488
1489 /* ----------------------------------------------------------------------------
1490 set_multicast_list
1491         Set or clear the multicast filter for this adaptor.
1492
1493 Input
1494         num_addrs == -1 Promiscuous mode, receive all packets
1495         num_addrs == 0  Normal mode, clear multicast list
1496         num_addrs > 0   Multicast mode, receive normal and MC packets, and do
1497                         best-effort filtering.
1498 Output
1499         multicast_num_addrs
1500         multicast_ladrf[]
1501 ---------------------------------------------------------------------------- */
1502
1503 static void set_multicast_list(struct net_device *dev)
1504 {
1505   mace_private *lp = netdev_priv(dev);
1506   int adr[ETHER_ADDR_LEN] = {0}; /* Ethernet address */
1507   int i;
1508   struct dev_mc_list *dmi = dev->mc_list;
1509
1510 #ifdef PCMCIA_DEBUG
1511   if (pc_debug > 1) {
1512     static int old;
1513     if (dev->mc_count != old) {
1514       old = dev->mc_count;
1515       DEBUG(0, "%s: setting Rx mode to %d addresses.\n",
1516             dev->name, old);
1517     }
1518   }
1519 #endif
1520
1521   /* Set multicast_num_addrs. */
1522   lp->multicast_num_addrs = dev->mc_count;
1523
1524   /* Set multicast_ladrf. */
1525   if (num_addrs > 0) {
1526     /* Calculate multicast logical address filter */
1527     memset(lp->multicast_ladrf, 0, MACE_LADRF_LEN);
1528     for (i = 0; i < dev->mc_count; i++) {
1529       memcpy(adr, dmi->dmi_addr, ETHER_ADDR_LEN);
1530       dmi = dmi->next;
1531       BuildLAF(lp->multicast_ladrf, adr);
1532     }
1533   }
1534
1535   restore_multicast_list(dev);
1536
1537 } /* set_multicast_list */
1538
1539 #endif /* BROKEN_MULTICAST */
1540
1541 static void restore_multicast_list(struct net_device *dev)
1542 {
1543   kio_addr_t ioaddr = dev->base_addr;
1544   mace_private *lp = netdev_priv(dev);
1545
1546   DEBUG(2, "%s: restoring Rx mode to %d addresses.\n", dev->name,
1547         lp->multicast_num_addrs);
1548
1549   if (dev->flags & IFF_PROMISC) {
1550     /* Promiscuous mode: receive all packets */
1551     mace_write(lp,ioaddr, MACE_UTR, MACE_UTR_LOOP_EXTERNAL);
1552     mace_write(lp, ioaddr, MACE_MACCC,
1553       MACE_MACCC_PROM | MACE_MACCC_ENXMT | MACE_MACCC_ENRCV
1554     );
1555   } else {
1556     /* Normal mode */
1557     mace_write(lp, ioaddr, MACE_UTR, MACE_UTR_LOOP_EXTERNAL);
1558     mace_write(lp, ioaddr, MACE_MACCC, MACE_MACCC_ENXMT | MACE_MACCC_ENRCV);
1559   }
1560 } /* restore_multicast_list */
1561
1562 static void set_multicast_list(struct net_device *dev)
1563 {
1564   mace_private *lp = netdev_priv(dev);
1565
1566 #ifdef PCMCIA_DEBUG
1567   if (pc_debug > 1) {
1568     static int old;
1569     if (dev->mc_count != old) {
1570       old = dev->mc_count;
1571       DEBUG(0, "%s: setting Rx mode to %d addresses.\n",
1572             dev->name, old);
1573     }
1574   }
1575 #endif
1576
1577   lp->multicast_num_addrs = dev->mc_count;
1578   restore_multicast_list(dev);
1579
1580 } /* set_multicast_list */
1581
1582 static struct pcmcia_device_id nmclan_ids[] = {
1583         PCMCIA_DEVICE_PROD_ID12("New Media Corporation", "Ethernet", 0x085a850b, 0x00b2e941),
1584         PCMCIA_DEVICE_PROD_ID12("Portable Add-ons", "Ethernet+", 0xebf1d60, 0xad673aaf),
1585         PCMCIA_DEVICE_NULL,
1586 };
1587 MODULE_DEVICE_TABLE(pcmcia, nmclan_ids);
1588
1589 static struct pcmcia_driver nmclan_cs_driver = {
1590         .owner          = THIS_MODULE,
1591         .drv            = {
1592                 .name   = "nmclan_cs",
1593         },
1594         .probe          = nmclan_probe,
1595         .remove         = nmclan_detach,
1596         .id_table       = nmclan_ids,
1597         .suspend        = nmclan_suspend,
1598         .resume         = nmclan_resume,
1599 };
1600
1601 static int __init init_nmclan_cs(void)
1602 {
1603         return pcmcia_register_driver(&nmclan_cs_driver);
1604 }
1605
1606 static void __exit exit_nmclan_cs(void)
1607 {
1608         pcmcia_unregister_driver(&nmclan_cs_driver);
1609 }
1610
1611 module_init(init_nmclan_cs);
1612 module_exit(exit_nmclan_cs);