| blob | 7dca225752c1c49e1e77c9014bf831e3045b1ffa |
1 /*
2 * linux/arch/arm/kernel/entry-armv.S
3 *
4 * Copyright (C) 1996,1997,1998 Russell King.
5 * ARM700 fix by Matthew Godbolt (linux-user@willothewisp.demon.co.uk)
6 * nommu support by Hyok S. Choi (hyok.choi@samsung.com)
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 *
12 * Low-level vector interface routines
13 *
14 * Note: there is a StrongARM bug in the STMIA rn, {regs}^ instruction
15 * that causes it to save wrong values... Be aware!
16 */
18 #include <asm/memory.h>
19 #include <asm/glue.h>
20 #include <asm/vfpmacros.h>
21 #include <asm/arch/entry-macro.S>
22 #include <asm/thread_notify.h>
24 #include "entry-header.S"
26 /*
27 * Interrupt handling. Preserves r7, r8, r9
28 */
29 .macro irq_handler
30 get_irqnr_preamble r5, lr
31 1: get_irqnr_and_base r0, r6, r5, lr
32 movne r1, sp
33 @
34 @ routine called with r0 = irq number, r1 = struct pt_regs *
35 @
36 adrne lr, 1b
37 bne asm_do_IRQ
39 #ifdef CONFIG_SMP
40 /*
41 * XXX
42 *
43 * this macro assumes that irqstat (r6) and base (r5) are
44 * preserved from get_irqnr_and_base above
45 */
46 test_for_ipi r0, r6, r5, lr
47 movne r0, sp
48 adrne lr, 1b
49 bne do_IPI
51 #ifdef CONFIG_LOCAL_TIMERS
52 test_for_ltirq r0, r6, r5, lr
53 movne r0, sp
54 adrne lr, 1b
55 bne do_local_timer
56 #endif
57 #endif
59 .endm
61 #ifdef CONFIG_KPROBES
62 .section .kprobes.text,"ax",%progbits
63 #else
64 .text
65 #endif
67 /*
68 * Invalid mode handlers
69 */
70 .macro inv_entry, reason
71 sub sp, sp, #S_FRAME_SIZE
72 stmib sp, {r1 - lr}
73 mov r1, #\reason
74 .endm
76 __pabt_invalid:
77 inv_entry BAD_PREFETCH
78 b common_invalid
80 __dabt_invalid:
81 inv_entry BAD_DATA
82 b common_invalid
84 __irq_invalid:
85 inv_entry BAD_IRQ
86 b common_invalid
88 __und_invalid:
89 inv_entry BAD_UNDEFINSTR
91 @
92 @ XXX fall through to common_invalid
93 @
95 @
96 @ common_invalid - generic code for failed exception (re-entrant version of handlers)
97 @
98 common_invalid:
99 zero_fp
101 ldmia r0, {r4 - r6}
102 add r0, sp, #S_PC @ here for interlock avoidance
103 mov r7, #-1 @ "" "" "" ""
104 str r4, [sp] @ save preserved r0
105 stmia r0, {r5 - r7} @ lr_<exception>,
106 @ cpsr_<exception>, "old_r0"
108 mov r0, sp
109 b bad_mode
111 /*
112 * SVC mode handlers
113 */
115 #if defined(CONFIG_AEABI) && (__LINUX_ARM_ARCH__ >= 5)
116 #define SPFIX(code...) code
117 #else
118 #define SPFIX(code...)
119 #endif
121 .macro svc_entry, stack_hole=0
122 sub sp, sp, #(S_FRAME_SIZE + \stack_hole)
123 SPFIX( tst sp, #4 )
124 SPFIX( bicne sp, sp, #4 )
125 stmib sp, {r1 - r12}
127 ldmia r0, {r1 - r3}
128 add r5, sp, #S_SP @ here for interlock avoidance
129 mov r4, #-1 @ "" "" "" ""
130 add r0, sp, #(S_FRAME_SIZE + \stack_hole)
131 SPFIX( addne r0, r0, #4 )
132 str r1, [sp] @ save the "real" r0 copied
133 @ from the exception stack
135 mov r1, lr
137 @
138 @ We are now ready to fill in the remaining blanks on the stack:
139 @
140 @ r0 - sp_svc
141 @ r1 - lr_svc
142 @ r2 - lr_<exception>, already fixed up for correct return/restart
143 @ r3 - spsr_<exception>
144 @ r4 - orig_r0 (see pt_regs definition in ptrace.h)
145 @
146 stmia r5, {r0 - r4}
147 .endm
149 .align 5
150 __dabt_svc:
151 svc_entry
153 @
154 @ get ready to re-enable interrupts if appropriate
155 @
156 mrs r9, cpsr
157 tst r3, #PSR_I_BIT
158 biceq r9, r9, #PSR_I_BIT
160 @
161 @ Call the processor-specific abort handler:
162 @
163 @ r2 - aborted context pc
164 @ r3 - aborted context cpsr
165 @
166 @ The abort handler must return the aborted address in r0, and
167 @ the fault status register in r1. r9 must be preserved.
168 @
169 #ifdef MULTI_DABORT
170 ldr r4, .LCprocfns
171 mov lr, pc
172 ldr pc, [r4, #PROCESSOR_DABT_FUNC]
173 #else
174 bl CPU_DABORT_HANDLER
175 #endif
177 @
178 @ set desired IRQ state, then call main handler
179 @
180 msr cpsr_c, r9
181 mov r2, sp
182 bl do_DataAbort
184 @
185 @ IRQs off again before pulling preserved data off the stack
186 @
187 disable_irq
189 @
190 @ restore SPSR and restart the instruction
191 @
192 ldr r0, [sp, #S_PSR]
193 msr spsr_cxsf, r0
194 ldmia sp, {r0 - pc}^ @ load r0 - pc, cpsr
196 .align 5
197 __irq_svc:
198 svc_entry
200 #ifdef CONFIG_TRACE_IRQFLAGS
201 bl trace_hardirqs_off
202 #endif
203 #ifdef CONFIG_PREEMPT
204 get_thread_info tsk
205 ldr r8, [tsk, #TI_PREEMPT] @ get preempt count
206 add r7, r8, #1 @ increment it
207 str r7, [tsk, #TI_PREEMPT]
208 #endif
210 irq_handler
211 #ifdef CONFIG_PREEMPT
212 str r8, [tsk, #TI_PREEMPT] @ restore preempt count
213 ldr r0, [tsk, #TI_FLAGS] @ get flags
214 teq r8, #0 @ if preempt count != 0
215 movne r0, #0 @ force flags to 0
216 tst r0, #_TIF_NEED_RESCHED
217 blne svc_preempt
218 #endif
219 ldr r0, [sp, #S_PSR] @ irqs are already disabled
220 msr spsr_cxsf, r0
221 #ifdef CONFIG_TRACE_IRQFLAGS
222 tst r0, #PSR_I_BIT
223 bleq trace_hardirqs_on
224 #endif
225 ldmia sp, {r0 - pc}^ @ load r0 - pc, cpsr
227 .ltorg
229 #ifdef CONFIG_PREEMPT
230 svc_preempt:
231 mov r8, lr
232 1: bl preempt_schedule_irq @ irq en/disable is done inside
233 ldr r0, [tsk, #TI_FLAGS] @ get new tasks TI_FLAGS
234 tst r0, #_TIF_NEED_RESCHED
235 moveq pc, r8 @ go again
236 b 1b
237 #endif
239 .align 5
240 __und_svc:
241 #ifdef CONFIG_KPROBES
242 @ If a kprobe is about to simulate a "stmdb sp..." instruction,
243 @ it obviously needs free stack space which then will belong to
244 @ the saved context.
245 svc_entry 64
246 #else
247 svc_entry
248 #endif
250 @
251 @ call emulation code, which returns using r9 if it has emulated
252 @ the instruction, or the more conventional lr if we are to treat
253 @ this as a real undefined instruction
254 @
255 @ r0 - instruction
256 @
257 ldr r0, [r2, #-4]
258 adr r9, 1f
259 bl call_fpe
261 mov r0, sp @ struct pt_regs *regs
262 bl do_undefinstr
264 @
265 @ IRQs off again before pulling preserved data off the stack
266 @
267 1: disable_irq
269 @
270 @ restore SPSR and restart the instruction
271 @
272 ldr lr, [sp, #S_PSR] @ Get SVC cpsr
273 msr spsr_cxsf, lr
274 ldmia sp, {r0 - pc}^ @ Restore SVC registers
276 .align 5
277 __pabt_svc:
278 svc_entry
280 @
281 @ re-enable interrupts if appropriate
282 @
283 mrs r9, cpsr
284 tst r3, #PSR_I_BIT
285 biceq r9, r9, #PSR_I_BIT
287 @
288 @ set args, then call main handler
289 @
290 @ r0 - address of faulting instruction
291 @ r1 - pointer to registers on stack
292 @
293 #ifdef MULTI_PABORT
294 mov r0, r2 @ pass address of aborted instruction.
295 ldr r4, .LCprocfns
296 mov lr, pc
297 ldr pc, [r4, #PROCESSOR_PABT_FUNC]
298 #else
299 CPU_PABORT_HANDLER(r0, r2)
300 #endif
301 msr cpsr_c, r9 @ Maybe enable interrupts
302 mov r1, sp @ regs
303 bl do_PrefetchAbort @ call abort handler
305 @
306 @ IRQs off again before pulling preserved data off the stack
307 @
308 disable_irq
310 @
311 @ restore SPSR and restart the instruction
312 @
313 ldr r0, [sp, #S_PSR]
314 msr spsr_cxsf, r0
315 ldmia sp, {r0 - pc}^ @ load r0 - pc, cpsr
317 .align 5
318 .LCcralign:
319 .word cr_alignment
320 #ifdef MULTI_DABORT
321 .LCprocfns:
322 .word processor
323 #endif
324 .LCfp:
325 .word fp_enter
327 /*
328 * User mode handlers
329 *
330 * EABI note: sp_svc is always 64-bit aligned here, so should S_FRAME_SIZE
331 */
333 #if defined(CONFIG_AEABI) && (__LINUX_ARM_ARCH__ >= 5) && (S_FRAME_SIZE & 7)
334 #error "sizeof(struct pt_regs) must be a multiple of 8"
335 #endif
337 .macro usr_entry
338 sub sp, sp, #S_FRAME_SIZE
339 stmib sp, {r1 - r12}
341 ldmia r0, {r1 - r3}
342 add r0, sp, #S_PC @ here for interlock avoidance
343 mov r4, #-1 @ "" "" "" ""
345 str r1, [sp] @ save the "real" r0 copied
346 @ from the exception stack
348 @
349 @ We are now ready to fill in the remaining blanks on the stack:
350 @
351 @ r2 - lr_<exception>, already fixed up for correct return/restart
352 @ r3 - spsr_<exception>
353 @ r4 - orig_r0 (see pt_regs definition in ptrace.h)
354 @
355 @ Also, separately save sp_usr and lr_usr
356 @
357 stmia r0, {r2 - r4}
358 stmdb r0, {sp, lr}^
360 @
361 @ Enable the alignment trap while in kernel mode
362 @
363 alignment_trap r0
365 @
366 @ Clear FP to mark the first stack frame
367 @
368 zero_fp
369 .endm
371 .macro kuser_cmpxchg_check
372 #if __LINUX_ARM_ARCH__ < 6 && !defined(CONFIG_NEEDS_SYSCALL_FOR_CMPXCHG)
373 #ifndef CONFIG_MMU
374 #warning "NPTL on non MMU needs fixing"
375 #else
376 @ Make sure our user space atomic helper is restarted
377 @ if it was interrupted in a critical region. Here we
378 @ perform a quick test inline since it should be false
379 @ 99.9999% of the time. The rest is done out of line.
380 cmp r2, #TASK_SIZE
381 blhs kuser_cmpxchg_fixup
382 #endif
383 #endif
384 .endm
386 .align 5
387 __dabt_usr:
388 usr_entry
389 kuser_cmpxchg_check
391 @
392 @ Call the processor-specific abort handler:
393 @
394 @ r2 - aborted context pc
395 @ r3 - aborted context cpsr
396 @
397 @ The abort handler must return the aborted address in r0, and
398 @ the fault status register in r1.
399 @
400 #ifdef MULTI_DABORT
401 ldr r4, .LCprocfns
402 mov lr, pc
403 ldr pc, [r4, #PROCESSOR_DABT_FUNC]
404 #else
405 bl CPU_DABORT_HANDLER
406 #endif
408 @
409 @ IRQs on, then call the main handler
410 @
411 enable_irq
412 mov r2, sp
413 adr lr, ret_from_exception
414 b do_DataAbort
416 .align 5
417 __irq_usr:
418 usr_entry
419 kuser_cmpxchg_check
421 #ifdef CONFIG_TRACE_IRQFLAGS
422 bl trace_hardirqs_off
423 #endif
424 get_thread_info tsk
425 #ifdef CONFIG_PREEMPT
426 ldr r8, [tsk, #TI_PREEMPT] @ get preempt count
427 add r7, r8, #1 @ increment it
428 str r7, [tsk, #TI_PREEMPT]
429 #endif
431 irq_handler
432 #ifdef CONFIG_PREEMPT
433 ldr r0, [tsk, #TI_PREEMPT]
434 str r8, [tsk, #TI_PREEMPT]
435 teq r0, r7
436 strne r0, [r0, -r0]
437 #endif
438 #ifdef CONFIG_TRACE_IRQFLAGS
439 bl trace_hardirqs_on
440 #endif
442 mov why, #0
443 b ret_to_user
445 .ltorg
447 .align 5
448 __und_usr:
449 usr_entry
451 @
452 @ fall through to the emulation code, which returns using r9 if
453 @ it has emulated the instruction, or the more conventional lr
454 @ if we are to treat this as a real undefined instruction
455 @
456 @ r0 - instruction
457 @
458 adr r9, ret_from_exception
459 adr lr, __und_usr_unknown
460 tst r3, #PSR_T_BIT @ Thumb mode?
461 subeq r4, r2, #4 @ ARM instr at LR - 4
462 subne r4, r2, #2 @ Thumb instr at LR - 2
463 1: ldreqt r0, [r4]
464 beq call_fpe
465 @ Thumb instruction
466 #if __LINUX_ARM_ARCH__ >= 7
467 2: ldrht r5, [r4], #2
468 and r0, r5, #0xf800 @ mask bits 111x x... .... ....
469 cmp r0, #0xe800 @ 32bit instruction if xx != 0
470 blo __und_usr_unknown
471 3: ldrht r0, [r4]
472 add r2, r2, #2 @ r2 is PC + 2, make it PC + 4
473 orr r0, r0, r5, lsl #16
474 #else
475 b __und_usr_unknown
476 #endif
478 @
479 @ fallthrough to call_fpe
480 @
482 /*
483 * The out of line fixup for the ldrt above.
484 */
485 .section .fixup, "ax"
486 4: mov pc, r9
487 .previous
488 .section __ex_table,"a"
489 .long 1b, 4b
490 #if __LINUX_ARM_ARCH__ >= 7
491 .long 2b, 4b
492 .long 3b, 4b
493 #endif
494 .previous
496 /*
497 * Check whether the instruction is a co-processor instruction.
498 * If yes, we need to call the relevant co-processor handler.
499 *
500 * Note that we don't do a full check here for the co-processor
501 * instructions; all instructions with bit 27 set are well
502 * defined. The only instructions that should fault are the
503 * co-processor instructions. However, we have to watch out
504 * for the ARM6/ARM7 SWI bug.
505 *
506 * NEON is a special case that has to be handled here. Not all
507 * NEON instructions are co-processor instructions, so we have
508 * to make a special case of checking for them. Plus, there's
509 * five groups of them, so we have a table of mask/opcode pairs
510 * to check against, and if any match then we branch off into the
511 * NEON handler code.
512 *
513 * Emulators may wish to make use of the following registers:
514 * r0 = instruction opcode.
515 * r2 = PC+4
516 * r9 = normal "successful" return address
517 * r10 = this threads thread_info structure.
518 * lr = unrecognised instruction return address
519 */
520 @
521 @ Fall-through from Thumb-2 __und_usr
522 @
523 #ifdef CONFIG_NEON
524 adr r6, .LCneon_thumb_opcodes
525 b 2f
526 #endif
527 call_fpe:
528 #ifdef CONFIG_NEON
529 adr r6, .LCneon_arm_opcodes
530 2:
531 ldr r7, [r6], #4 @ mask value
532 cmp r7, #0 @ end mask?
533 beq 1f
534 and r8, r0, r7
535 ldr r7, [r6], #4 @ opcode bits matching in mask
536 cmp r8, r7 @ NEON instruction?
537 bne 2b
538 get_thread_info r10
539 mov r7, #1
540 strb r7, [r10, #TI_USED_CP + 10] @ mark CP#10 as used
541 strb r7, [r10, #TI_USED_CP + 11] @ mark CP#11 as used
542 b do_vfp @ let VFP handler handle this
543 1:
544 #endif
545 tst r0, #0x08000000 @ only CDP/CPRT/LDC/STC have bit 27
546 tstne r0, #0x04000000 @ bit 26 set on both ARM and Thumb-2
547 #if defined(CONFIG_CPU_ARM610) || defined(CONFIG_CPU_ARM710)
548 and r8, r0, #0x0f000000 @ mask out op-code bits
549 teqne r8, #0x0f000000 @ SWI (ARM6/7 bug)?
550 #endif
551 moveq pc, lr
552 get_thread_info r10 @ get current thread
553 and r8, r0, #0x00000f00 @ mask out CP number
554 mov r7, #1
555 add r6, r10, #TI_USED_CP
556 strb r7, [r6, r8, lsr #8] @ set appropriate used_cp[]
557 #ifdef CONFIG_IWMMXT
558 @ Test if we need to give access to iWMMXt coprocessors
559 ldr r5, [r10, #TI_FLAGS]
560 rsbs r7, r8, #(1 << 8) @ CP 0 or 1 only
561 movcss r7, r5, lsr #(TIF_USING_IWMMXT + 1)
562 bcs iwmmxt_task_enable
563 #endif
564 add pc, pc, r8, lsr #6
565 mov r0, r0
567 mov pc, lr @ CP#0
568 b do_fpe @ CP#1 (FPE)
569 b do_fpe @ CP#2 (FPE)
570 mov pc, lr @ CP#3
571 #ifdef CONFIG_CRUNCH
572 b crunch_task_enable @ CP#4 (MaverickCrunch)
573 b crunch_task_enable @ CP#5 (MaverickCrunch)
574 b crunch_task_enable @ CP#6 (MaverickCrunch)
575 #else
576 mov pc, lr @ CP#4
577 mov pc, lr @ CP#5
578 mov pc, lr @ CP#6
579 #endif
580 mov pc, lr @ CP#7
581 mov pc, lr @ CP#8
582 mov pc, lr @ CP#9
583 #ifdef CONFIG_VFP
584 b do_vfp @ CP#10 (VFP)
585 b do_vfp @ CP#11 (VFP)
586 #else
587 mov pc, lr @ CP#10 (VFP)
588 mov pc, lr @ CP#11 (VFP)
589 #endif
590 mov pc, lr @ CP#12
591 mov pc, lr @ CP#13
592 mov pc, lr @ CP#14 (Debug)
593 mov pc, lr @ CP#15 (Control)
595 #ifdef CONFIG_NEON
596 .align 6
598 .LCneon_arm_opcodes:
599 .word 0xfe000000 @ mask
600 .word 0xf2000000 @ opcode
602 .word 0xff100000 @ mask
603 .word 0xf4000000 @ opcode
605 .word 0x00000000 @ mask
606 .word 0x00000000 @ opcode
608 .LCneon_thumb_opcodes:
609 .word 0xef000000 @ mask
610 .word 0xef000000 @ opcode
612 .word 0xff100000 @ mask
613 .word 0xf9000000 @ opcode
615 .word 0x00000000 @ mask
616 .word 0x00000000 @ opcode
617 #endif
619 do_fpe:
620 enable_irq
621 ldr r4, .LCfp
622 add r10, r10, #TI_FPSTATE @ r10 = workspace
623 ldr pc, [r4] @ Call FP module USR entry point
625 /*
626 * The FP module is called with these registers set:
627 * r0 = instruction
628 * r2 = PC+4
629 * r9 = normal "successful" return address
630 * r10 = FP workspace
631 * lr = unrecognised FP instruction return address
632 */
634 .data
635 ENTRY(fp_enter)
636 .word no_fp
637 .previous
639 no_fp: mov pc, lr
641 __und_usr_unknown:
642 mov r0, sp
643 adr lr, ret_from_exception
644 b do_undefinstr
646 .align 5
647 __pabt_usr:
648 usr_entry
650 #ifdef MULTI_PABORT
651 mov r0, r2 @ pass address of aborted instruction.
652 ldr r4, .LCprocfns
653 mov lr, pc
654 ldr pc, [r4, #PROCESSOR_PABT_FUNC]
655 #else
656 CPU_PABORT_HANDLER(r0, r2)
657 #endif
658 enable_irq @ Enable interrupts
659 mov r1, sp @ regs
660 bl do_PrefetchAbort @ call abort handler
661 /* fall through */
662 /*
663 * This is the return code to user mode for abort handlers
664 */
665 ENTRY(ret_from_exception)
666 get_thread_info tsk
667 mov why, #0
668 b ret_to_user
670 /*
671 * Register switch for ARMv3 and ARMv4 processors
672 * r0 = previous task_struct, r1 = previous thread_info, r2 = next thread_info
673 * previous and next are guaranteed not to be the same.
674 */
675 ENTRY(__switch_to)
676 add ip, r1, #TI_CPU_SAVE
677 ldr r3, [r2, #TI_TP_VALUE]
678 stmia ip!, {r4 - sl, fp, sp, lr} @ Store most regs on stack
679 #ifdef CONFIG_MMU
680 ldr r6, [r2, #TI_CPU_DOMAIN]
681 #endif
682 #if __LINUX_ARM_ARCH__ >= 6
683 #ifdef CONFIG_CPU_32v6K
684 clrex
685 #else
686 strex r5, r4, [ip] @ Clear exclusive monitor
687 #endif
688 #endif
689 #if defined(CONFIG_HAS_TLS_REG)
690 mcr p15, 0, r3, c13, c0, 3 @ set TLS register
691 #elif !defined(CONFIG_TLS_REG_EMUL)
692 mov r4, #0xffff0fff
693 str r3, [r4, #-15] @ TLS val at 0xffff0ff0
694 #endif
695 #ifdef CONFIG_MMU
696 mcr p15, 0, r6, c3, c0, 0 @ Set domain register
697 #endif
698 mov r5, r0
699 add r4, r2, #TI_CPU_SAVE
700 ldr r0, =thread_notify_head
701 mov r1, #THREAD_NOTIFY_SWITCH
702 bl atomic_notifier_call_chain
703 mov r0, r5
704 ldmia r4, {r4 - sl, fp, sp, pc} @ Load all regs saved previously
706 __INIT
708 /*
709 * User helpers.
710 *
711 * These are segment of kernel provided user code reachable from user space
712 * at a fixed address in kernel memory. This is used to provide user space
713 * with some operations which require kernel help because of unimplemented
714 * native feature and/or instructions in many ARM CPUs. The idea is for
715 * this code to be executed directly in user mode for best efficiency but
716 * which is too intimate with the kernel counter part to be left to user
717 * libraries. In fact this code might even differ from one CPU to another
718 * depending on the available instruction set and restrictions like on
719 * SMP systems. In other words, the kernel reserves the right to change
720 * this code as needed without warning. Only the entry points and their
721 * results are guaranteed to be stable.
722 *
723 * Each segment is 32-byte aligned and will be moved to the top of the high
724 * vector page. New segments (if ever needed) must be added in front of
725 * existing ones. This mechanism should be used only for things that are
726 * really small and justified, and not be abused freely.
727 *
728 * User space is expected to implement those things inline when optimizing
729 * for a processor that has the necessary native support, but only if such
730 * resulting binaries are already to be incompatible with earlier ARM
731 * processors due to the use of unsupported instructions other than what
732 * is provided here. In other words don't make binaries unable to run on
733 * earlier processors just for the sake of not using these kernel helpers
734 * if your compiled code is not going to use the new instructions for other
735 * purpose.
736 */
738 .macro usr_ret, reg
739 #ifdef CONFIG_ARM_THUMB
740 bx \reg
741 #else
742 mov pc, \reg
743 #endif
744 .endm
746 .align 5
747 .globl __kuser_helper_start
748 __kuser_helper_start:
750 /*
751 * Reference prototype:
752 *
753 * void __kernel_memory_barrier(void)
754 *
755 * Input:
756 *
757 * lr = return address
758 *
759 * Output:
760 *
761 * none
762 *
763 * Clobbered:
764 *
765 * none
766 *
767 * Definition and user space usage example:
768 *
769 * typedef void (__kernel_dmb_t)(void);
770 * #define __kernel_dmb (*(__kernel_dmb_t *)0xffff0fa0)
771 *
772 * Apply any needed memory barrier to preserve consistency with data modified
773 * manually and __kuser_cmpxchg usage.
774 *
775 * This could be used as follows:
776 *
777 * #define __kernel_dmb() \
778 * asm volatile ( "mov r0, #0xffff0fff; mov lr, pc; sub pc, r0, #95" \
779 * : : : "r0", "lr","cc" )
780 */
782 __kuser_memory_barrier: @ 0xffff0fa0
784 #if __LINUX_ARM_ARCH__ >= 6 && defined(CONFIG_SMP)
785 mcr p15, 0, r0, c7, c10, 5 @ dmb
786 #endif
787 usr_ret lr
789 .align 5
791 /*
792 * Reference prototype:
793 *
794 * int __kernel_cmpxchg(int oldval, int newval, int *ptr)
795 *
796 * Input:
797 *
798 * r0 = oldval
799 * r1 = newval
800 * r2 = ptr
801 * lr = return address
802 *
803 * Output:
804 *
805 * r0 = returned value (zero or non-zero)
806 * C flag = set if r0 == 0, clear if r0 != 0
807 *
808 * Clobbered:
809 *
810 * r3, ip, flags
811 *
812 * Definition and user space usage example:
813 *
814 * typedef int (__kernel_cmpxchg_t)(int oldval, int newval, int *ptr);
815 * #define __kernel_cmpxchg (*(__kernel_cmpxchg_t *)0xffff0fc0)
816 *
817 * Atomically store newval in *ptr if *ptr is equal to oldval for user space.
818 * Return zero if *ptr was changed or non-zero if no exchange happened.
819 * The C flag is also set if *ptr was changed to allow for assembly
820 * optimization in the calling code.
821 *
822 * Notes:
823 *
824 * - This routine already includes memory barriers as needed.
825 *
826 * For example, a user space atomic_add implementation could look like this:
827 *
828 * #define atomic_add(ptr, val) \
829 * ({ register unsigned int *__ptr asm("r2") = (ptr); \
830 * register unsigned int __result asm("r1"); \
831 * asm volatile ( \
832 * "1: @ atomic_add\n\t" \
833 * "ldr r0, [r2]\n\t" \
834 * "mov r3, #0xffff0fff\n\t" \
835 * "add lr, pc, #4\n\t" \
836 * "add r1, r0, %2\n\t" \
837 * "add pc, r3, #(0xffff0fc0 - 0xffff0fff)\n\t" \
838 * "bcc 1b" \
839 * : "=&r" (__result) \
840 * : "r" (__ptr), "rIL" (val) \
841 * : "r0","r3","ip","lr","cc","memory" ); \
842 * __result; })
843 */
845 __kuser_cmpxchg: @ 0xffff0fc0
847 #if defined(CONFIG_NEEDS_SYSCALL_FOR_CMPXCHG)
849 /*
850 * Poor you. No fast solution possible...
851 * The kernel itself must perform the operation.
852 * A special ghost syscall is used for that (see traps.c).
853 */
854 stmfd sp!, {r7, lr}
855 mov r7, #0xff00 @ 0xfff0 into r7 for EABI
856 orr r7, r7, #0xf0
857 swi #0x9ffff0
858 ldmfd sp!, {r7, pc}
860 #elif __LINUX_ARM_ARCH__ < 6
862 #ifdef CONFIG_MMU
864 /*
865 * The only thing that can break atomicity in this cmpxchg
866 * implementation is either an IRQ or a data abort exception
867 * causing another process/thread to be scheduled in the middle
868 * of the critical sequence. To prevent this, code is added to
869 * the IRQ and data abort exception handlers to set the pc back
870 * to the beginning of the critical section if it is found to be
871 * within that critical section (see kuser_cmpxchg_fixup).
872 */
873 1: ldr r3, [r2] @ load current val
874 subs r3, r3, r0 @ compare with oldval
875 2: streq r1, [r2] @ store newval if eq
876 rsbs r0, r3, #0 @ set return val and C flag
877 usr_ret lr
879 .text
880 kuser_cmpxchg_fixup:
881 @ Called from kuser_cmpxchg_check macro.
882 @ r2 = address of interrupted insn (must be preserved).
883 @ sp = saved regs. r7 and r8 are clobbered.
884 @ 1b = first critical insn, 2b = last critical insn.
885 @ If r2 >= 1b and r2 <= 2b then saved pc_usr is set to 1b.
886 mov r7, #0xffff0fff
887 sub r7, r7, #(0xffff0fff - (0xffff0fc0 + (1b - __kuser_cmpxchg)))
888 subs r8, r2, r7
889 rsbcss r8, r8, #(2b - 1b)
890 strcs r7, [sp, #S_PC]
891 mov pc, lr
892 .previous
894 #else
895 #warning "NPTL on non MMU needs fixing"
896 mov r0, #-1
897 adds r0, r0, #0
898 usr_ret lr
899 #endif
901 #else
903 #ifdef CONFIG_SMP
904 mcr p15, 0, r0, c7, c10, 5 @ dmb
905 #endif
906 1: ldrex r3, [r2]
907 subs r3, r3, r0
908 strexeq r3, r1, [r2]
909 teqeq r3, #1
910 beq 1b
911 rsbs r0, r3, #0
912 /* beware -- each __kuser slot must be 8 instructions max */
913 #ifdef CONFIG_SMP
914 b __kuser_memory_barrier
915 #else
916 usr_ret lr
917 #endif
919 #endif
921 .align 5
923 /*
924 * Reference prototype:
925 *
926 * int __kernel_get_tls(void)
927 *
928 * Input:
929 *
930 * lr = return address
931 *
932 * Output:
933 *
934 * r0 = TLS value
935 *
936 * Clobbered:
937 *
938 * none
939 *
940 * Definition and user space usage example:
941 *
942 * typedef int (__kernel_get_tls_t)(void);
943 * #define __kernel_get_tls (*(__kernel_get_tls_t *)0xffff0fe0)
944 *
945 * Get the TLS value as previously set via the __ARM_NR_set_tls syscall.
946 *
947 * This could be used as follows:
948 *
949 * #define __kernel_get_tls() \
950 * ({ register unsigned int __val asm("r0"); \
951 * asm( "mov r0, #0xffff0fff; mov lr, pc; sub pc, r0, #31" \
952 * : "=r" (__val) : : "lr","cc" ); \
953 * __val; })
954 */
956 __kuser_get_tls: @ 0xffff0fe0
958 #if !defined(CONFIG_HAS_TLS_REG) && !defined(CONFIG_TLS_REG_EMUL)
959 ldr r0, [pc, #(16 - 8)] @ TLS stored at 0xffff0ff0
960 #else
961 mrc p15, 0, r0, c13, c0, 3 @ read TLS register
962 #endif
963 usr_ret lr
965 .rep 5
966 .word 0 @ pad up to __kuser_helper_version
967 .endr
969 /*
970 * Reference declaration:
971 *
972 * extern unsigned int __kernel_helper_version;
973 *
974 * Definition and user space usage example:
975 *
976 * #define __kernel_helper_version (*(unsigned int *)0xffff0ffc)
977 *
978 * User space may read this to determine the curent number of helpers
979 * available.
980 */
982 __kuser_helper_version: @ 0xffff0ffc
983 .word ((__kuser_helper_end - __kuser_helper_start) >> 5)
985 .globl __kuser_helper_end
986 __kuser_helper_end:
989 /*
990 * Vector stubs.
991 *
992 * This code is copied to 0xffff0200 so we can use branches in the
993 * vectors, rather than ldr's. Note that this code must not
994 * exceed 0x300 bytes.
995 *
996 * Common stub entry macro:
997 * Enter in IRQ mode, spsr = SVC/USR CPSR, lr = SVC/USR PC
998 *
999 * SP points to a minimal amount of processor-private memory, the address
1000 * of which is copied into r0 for the mode specific abort handler.
1001 */
1002 .macro vector_stub, name, mode, correction=0
1003 .align 5
1005 vector_\name:
1006 .if \correction
1007 sub lr, lr, #\correction
1008 .endif
1010 @
1011 @ Save r0, lr_<exception> (parent PC) and spsr_<exception>
1012 @ (parent CPSR)
1013 @
1014 stmia sp, {r0, lr} @ save r0, lr
1015 mrs lr, spsr
1016 str lr, [sp, #8] @ save spsr
1018 @
1019 @ Prepare for SVC32 mode. IRQs remain disabled.
1020 @
1021 mrs r0, cpsr
1022 eor r0, r0, #(\mode ^ SVC_MODE)
1023 msr spsr_cxsf, r0
1025 @
1026 @ the branch table must immediately follow this code
1027 @
1028 and lr, lr, #0x0f
1029 mov r0, sp
1030 ldr lr, [pc, lr, lsl #2]
1031 movs pc, lr @ branch to handler in SVC mode
1032 .endm
1034 .globl __stubs_start
1035 __stubs_start:
1036 /*
1037 * Interrupt dispatcher
1038 */
1039 vector_stub irq, IRQ_MODE, 4
1041 .long __irq_usr @ 0 (USR_26 / USR_32)
1042 .long __irq_invalid @ 1 (FIQ_26 / FIQ_32)
1043 .long __irq_invalid @ 2 (IRQ_26 / IRQ_32)
1044 .long __irq_svc @ 3 (SVC_26 / SVC_32)
1045 .long __irq_invalid @ 4
1046 .long __irq_invalid @ 5
1047 .long __irq_invalid @ 6
1048 .long __irq_invalid @ 7
1049 .long __irq_invalid @ 8
1050 .long __irq_invalid @ 9
1051 .long __irq_invalid @ a
1052 .long __irq_invalid @ b
1053 .long __irq_invalid @ c
1054 .long __irq_invalid @ d
1055 .long __irq_invalid @ e
1056 .long __irq_invalid @ f
1058 /*
1059 * Data abort dispatcher
1060 * Enter in ABT mode, spsr = USR CPSR, lr = USR PC
1061 */
1062 vector_stub dabt, ABT_MODE, 8
1064 .long __dabt_usr @ 0 (USR_26 / USR_32)
1065 .long __dabt_invalid @ 1 (FIQ_26 / FIQ_32)
1066 .long __dabt_invalid @ 2 (IRQ_26 / IRQ_32)
1067 .long __dabt_svc @ 3 (SVC_26 / SVC_32)
1068 .long __dabt_invalid @ 4
1069 .long __dabt_invalid @ 5
1070 .long __dabt_invalid @ 6
1071 .long __dabt_invalid @ 7
1072 .long __dabt_invalid @ 8
1073 .long __dabt_invalid @ 9
1074 .long __dabt_invalid @ a
1075 .long __dabt_invalid @ b
1076 .long __dabt_invalid @ c
1077 .long __dabt_invalid @ d
1078 .long __dabt_invalid @ e
1079 .long __dabt_invalid @ f
1081 /*
1082 * Prefetch abort dispatcher
1083 * Enter in ABT mode, spsr = USR CPSR, lr = USR PC
1084 */
1085 vector_stub pabt, ABT_MODE, 4
1087 .long __pabt_usr @ 0 (USR_26 / USR_32)
1088 .long __pabt_invalid @ 1 (FIQ_26 / FIQ_32)
1089 .long __pabt_invalid @ 2 (IRQ_26 / IRQ_32)
1090 .long __pabt_svc @ 3 (SVC_26 / SVC_32)
1091 .long __pabt_invalid @ 4
1092 .long __pabt_invalid @ 5
1093 .long __pabt_invalid @ 6
1094 .long __pabt_invalid @ 7
1095 .long __pabt_invalid @ 8
1096 .long __pabt_invalid @ 9
1097 .long __pabt_invalid @ a
1098 .long __pabt_invalid @ b
1099 .long __pabt_invalid @ c
1100 .long __pabt_invalid @ d
1101 .long __pabt_invalid @ e
1102 .long __pabt_invalid @ f
1104 /*
1105 * Undef instr entry dispatcher
1106 * Enter in UND mode, spsr = SVC/USR CPSR, lr = SVC/USR PC
1107 */
1108 vector_stub und, UND_MODE
1110 .long __und_usr @ 0 (USR_26 / USR_32)
1111 .long __und_invalid @ 1 (FIQ_26 / FIQ_32)
1112 .long __und_invalid @ 2 (IRQ_26 / IRQ_32)
1113 .long __und_svc @ 3 (SVC_26 / SVC_32)
1114 .long __und_invalid @ 4
1115 .long __und_invalid @ 5
1116 .long __und_invalid @ 6
1117 .long __und_invalid @ 7
1118 .long __und_invalid @ 8
1119 .long __und_invalid @ 9
1120 .long __und_invalid @ a
1121 .long __und_invalid @ b
1122 .long __und_invalid @ c
1123 .long __und_invalid @ d
1124 .long __und_invalid @ e
1125 .long __und_invalid @ f
1127 .align 5
1129 /*=============================================================================
1130 * Undefined FIQs
1131 *-----------------------------------------------------------------------------
1132 * Enter in FIQ mode, spsr = ANY CPSR, lr = ANY PC
1133 * MUST PRESERVE SVC SPSR, but need to switch to SVC mode to show our msg.
1134 * Basically to switch modes, we *HAVE* to clobber one register... brain
1135 * damage alert! I don't think that we can execute any code in here in any
1136 * other mode than FIQ... Ok you can switch to another mode, but you can't
1137 * get out of that mode without clobbering one register.
1138 */
1139 vector_fiq:
1140 disable_fiq
1141 subs pc, lr, #4
1143 /*=============================================================================
1144 * Address exception handler
1145 *-----------------------------------------------------------------------------
1146 * These aren't too critical.
1147 * (they're not supposed to happen, and won't happen in 32-bit data mode).
1148 */
1150 vector_addrexcptn:
1151 b vector_addrexcptn
1153 /*
1154 * We group all the following data together to optimise
1155 * for CPUs with separate I & D caches.
1156 */
1157 .align 5
1159 .LCvswi:
1160 .word vector_swi
1162 .globl __stubs_end
1163 __stubs_end:
1165 .equ stubs_offset, __vectors_start + 0x200 - __stubs_start
1167 .globl __vectors_start
1168 __vectors_start:
1169 swi SYS_ERROR0
1170 b vector_und + stubs_offset
1171 ldr pc, .LCvswi + stubs_offset
1172 b vector_pabt + stubs_offset
1173 b vector_dabt + stubs_offset
1174 b vector_addrexcptn + stubs_offset
1175 b vector_irq + stubs_offset
1176 b vector_fiq + stubs_offset
1178 .globl __vectors_end
1179 __vectors_end:
1181 .data
1183 .globl cr_alignment
1184 .globl cr_no_alignment
1185 cr_alignment:
1186 .space 4
1187 cr_no_alignment:
1188 .space 4