| blob | bff4c6e90dd5458f1f71d2d70a5703ea394017c5 |
1 /*
2 * linux/arch/arm/kernel/head.S
3 *
4 * Copyright (C) 1994-2002 Russell King
5 * Copyright (c) 2003 ARM Limited
6 * All Rights Reserved
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 *
12 * Kernel startup code for all 32-bit CPUs
13 */
14 #include <linux/linkage.h>
15 #include <linux/init.h>
17 #include <asm/assembler.h>
18 #include <asm/domain.h>
19 #include <asm/ptrace.h>
20 #include <asm/asm-offsets.h>
21 #include <asm/memory.h>
22 #include <asm/thread_info.h>
23 #include <asm/system.h>
25 #if (PHYS_OFFSET & 0x001fffff)
26 #error "PHYS_OFFSET must be at an even 2MiB boundary!"
27 #endif
29 #define KERNEL_RAM_VADDR (PAGE_OFFSET + TEXT_OFFSET)
30 #define KERNEL_RAM_PADDR (PHYS_OFFSET + TEXT_OFFSET)
33 /*
34 * swapper_pg_dir is the virtual address of the initial page table.
35 * We place the page tables 16K below KERNEL_RAM_VADDR. Therefore, we must
36 * make sure that KERNEL_RAM_VADDR is correctly set. Currently, we expect
37 * the least significant 16 bits to be 0x8000, but we could probably
38 * relax this restriction to KERNEL_RAM_VADDR >= PAGE_OFFSET + 0x4000.
39 */
40 #if (KERNEL_RAM_VADDR & 0xffff) != 0x8000
41 #error KERNEL_RAM_VADDR must start at 0xXXXX8000
42 #endif
44 .globl swapper_pg_dir
45 .equ swapper_pg_dir, KERNEL_RAM_VADDR - 0x4000
47 .macro pgtbl, rd
48 ldr \rd, =(KERNEL_RAM_PADDR - 0x4000)
49 .endm
51 #ifdef CONFIG_XIP_KERNEL
52 #define KERNEL_START XIP_VIRT_ADDR(CONFIG_XIP_PHYS_ADDR)
53 #define KERNEL_END _edata_loc
54 #else
55 #define KERNEL_START KERNEL_RAM_VADDR
56 #define KERNEL_END _end
57 #endif
59 /*
60 * Kernel startup entry point.
61 * ---------------------------
62 *
63 * This is normally called from the decompressor code. The requirements
64 * are: MMU = off, D-cache = off, I-cache = dont care, r0 = 0,
65 * r1 = machine nr, r2 = atags pointer.
66 *
67 * This code is mostly position independent, so if you link the kernel at
68 * 0xc0008000, you call this at __pa(0xc0008000).
69 *
70 * See linux/arch/arm/tools/mach-types for the complete list of machine
71 * numbers for r1.
72 *
73 * We're trying to keep crap to a minimum; DO NOT add any machine specific
74 * crap here - that's what the boot loader (or in extreme, well justified
75 * circumstances, zImage) is for.
76 */
77 .section ".text.head", "ax"
78 .type stext, %function
79 ENTRY(stext)
80 msr cpsr_c, #PSR_F_BIT | PSR_I_BIT | SVC_MODE @ ensure svc mode
81 @ and irqs disabled
82 mrc p15, 0, r9, c0, c0 @ get processor id
83 bl __lookup_processor_type @ r5=procinfo r9=cpuid
84 movs r10, r5 @ invalid processor (r5=0)?
85 beq __error_p @ yes, error 'p'
86 bl __lookup_machine_type @ r5=machinfo
87 movs r8, r5 @ invalid machine (r5=0)?
88 beq __error_a @ yes, error 'a'
89 bl __vet_atags
90 bl __create_page_tables
92 /*
93 * The following calls CPU specific code in a position independent
94 * manner. See arch/arm/mm/proc-*.S for details. r10 = base of
95 * xxx_proc_info structure selected by __lookup_machine_type
96 * above. On return, the CPU will be ready for the MMU to be
97 * turned on, and r0 will hold the CPU control register value.
98 */
99 ldr r13, __switch_data @ address to jump to after
100 @ mmu has been enabled
101 adr lr, __enable_mmu @ return (PIC) address
102 add pc, r10, #PROCINFO_INITFUNC
104 #if defined(CONFIG_SMP)
105 .type secondary_startup, #function
106 ENTRY(secondary_startup)
107 /*
108 * Common entry point for secondary CPUs.
109 *
110 * Ensure that we're in SVC mode, and IRQs are disabled. Lookup
111 * the processor type - there is no need to check the machine type
112 * as it has already been validated by the primary processor.
113 */
114 msr cpsr_c, #PSR_F_BIT | PSR_I_BIT | SVC_MODE
115 mrc p15, 0, r9, c0, c0 @ get processor id
116 bl __lookup_processor_type
117 movs r10, r5 @ invalid processor?
118 moveq r0, #'p' @ yes, error 'p'
119 beq __error
121 /*
122 * Use the page tables supplied from __cpu_up.
123 */
124 adr r4, __secondary_data
125 ldmia r4, {r5, r7, r13} @ address to jump to after
126 sub r4, r4, r5 @ mmu has been enabled
127 ldr r4, [r7, r4] @ get secondary_data.pgdir
128 adr lr, __enable_mmu @ return address
129 add pc, r10, #PROCINFO_INITFUNC @ initialise processor
130 @ (return control reg)
132 /*
133 * r6 = &secondary_data
134 */
135 ENTRY(__secondary_switched)
136 ldr sp, [r7, #4] @ get secondary_data.stack
137 mov fp, #0
138 b secondary_start_kernel
140 .type __secondary_data, %object
141 __secondary_data:
142 .long .
143 .long secondary_data
144 .long __secondary_switched
145 #endif /* defined(CONFIG_SMP) */
149 /*
150 * Setup common bits before finally enabling the MMU. Essentially
151 * this is just loading the page table pointer and domain access
152 * registers.
153 */
154 .type __enable_mmu, %function
155 __enable_mmu:
156 #ifdef CONFIG_ALIGNMENT_TRAP
157 orr r0, r0, #CR_A
158 #else
159 bic r0, r0, #CR_A
160 #endif
161 #ifdef CONFIG_CPU_DCACHE_DISABLE
162 bic r0, r0, #CR_C
163 #endif
164 #ifdef CONFIG_CPU_BPREDICT_DISABLE
165 bic r0, r0, #CR_Z
166 #endif
167 #ifdef CONFIG_CPU_ICACHE_DISABLE
168 bic r0, r0, #CR_I
169 #endif
170 mov r5, #(domain_val(DOMAIN_USER, DOMAIN_MANAGER) | \
171 domain_val(DOMAIN_KERNEL, DOMAIN_MANAGER) | \
172 domain_val(DOMAIN_TABLE, DOMAIN_MANAGER) | \
173 domain_val(DOMAIN_IO, DOMAIN_CLIENT))
174 mcr p15, 0, r5, c3, c0, 0 @ load domain access register
175 mcr p15, 0, r4, c2, c0, 0 @ load page table pointer
176 b __turn_mmu_on
178 /*
179 * Enable the MMU. This completely changes the structure of the visible
180 * memory space. You will not be able to trace execution through this.
181 * If you have an enquiry about this, *please* check the linux-arm-kernel
182 * mailing list archives BEFORE sending another post to the list.
183 *
184 * r0 = cp#15 control register
185 * r13 = *virtual* address to jump to upon completion
186 *
187 * other registers depend on the function called upon completion
188 */
189 .align 5
190 .type __turn_mmu_on, %function
191 __turn_mmu_on:
192 mov r0, r0
193 mcr p15, 0, r0, c1, c0, 0 @ write control reg
194 mrc p15, 0, r3, c0, c0, 0 @ read id reg
195 mov r3, r3
196 mov r3, r3
197 mov pc, r13
201 /*
202 * Setup the initial page tables. We only setup the barest
203 * amount which are required to get the kernel running, which
204 * generally means mapping in the kernel code.
205 *
206 * r8 = machinfo
207 * r9 = cpuid
208 * r10 = procinfo
209 *
210 * Returns:
211 * r0, r3, r6, r7 corrupted
212 * r4 = physical page table address
213 */
214 .type __create_page_tables, %function
215 __create_page_tables:
216 pgtbl r4 @ page table address
218 /*
219 * Clear the 16K level 1 swapper page table
220 */
221 mov r0, r4
222 mov r3, #0
223 add r6, r0, #0x4000
224 1: str r3, [r0], #4
225 str r3, [r0], #4
226 str r3, [r0], #4
227 str r3, [r0], #4
228 teq r0, r6
229 bne 1b
231 ldr r7, [r10, #PROCINFO_MM_MMUFLAGS] @ mm_mmuflags
233 /*
234 * Create identity mapping for first MB of kernel to
235 * cater for the MMU enable. This identity mapping
236 * will be removed by paging_init(). We use our current program
237 * counter to determine corresponding section base address.
238 */
239 mov r6, pc, lsr #20 @ start of kernel section
240 orr r3, r7, r6, lsl #20 @ flags + kernel base
241 str r3, [r4, r6, lsl #2] @ identity mapping
243 /*
244 * Now setup the pagetables for our kernel direct
245 * mapped region.
246 */
247 add r0, r4, #(KERNEL_START & 0xff000000) >> 18
248 str r3, [r0, #(KERNEL_START & 0x00f00000) >> 18]!
249 ldr r6, =(KERNEL_END - 1)
250 add r0, r0, #4
251 add r6, r4, r6, lsr #18
252 1: cmp r0, r6
253 add r3, r3, #1 << 20
254 strls r3, [r0], #4
255 bls 1b
257 #ifdef CONFIG_XIP_KERNEL
258 /*
259 * Map some ram to cover our .data and .bss areas.
260 */
261 orr r3, r7, #(KERNEL_RAM_PADDR & 0xff000000)
262 .if (KERNEL_RAM_PADDR & 0x00f00000)
263 orr r3, r3, #(KERNEL_RAM_PADDR & 0x00f00000)
264 .endif
265 add r0, r4, #(KERNEL_RAM_VADDR & 0xff000000) >> 18
266 str r3, [r0, #(KERNEL_RAM_VADDR & 0x00f00000) >> 18]!
267 ldr r6, =(_end - 1)
268 add r0, r0, #4
269 add r6, r4, r6, lsr #18
270 1: cmp r0, r6
271 add r3, r3, #1 << 20
272 strls r3, [r0], #4
273 bls 1b
274 #endif
276 /*
277 * Then map first 1MB of ram in case it contains our boot params.
278 */
279 add r0, r4, #PAGE_OFFSET >> 18
280 orr r6, r7, #(PHYS_OFFSET & 0xff000000)
281 .if (PHYS_OFFSET & 0x00f00000)
282 orr r6, r6, #(PHYS_OFFSET & 0x00f00000)
283 .endif
284 str r6, [r0]
286 #ifdef CONFIG_DEBUG_LL
287 ldr r7, [r10, #PROCINFO_IO_MMUFLAGS] @ io_mmuflags
288 /*
289 * Map in IO space for serial debugging.
290 * This allows debug messages to be output
291 * via a serial console before paging_init.
292 */
293 ldr r3, [r8, #MACHINFO_PGOFFIO]
294 add r0, r4, r3
295 rsb r3, r3, #0x4000 @ PTRS_PER_PGD*sizeof(long)
296 cmp r3, #0x0800 @ limit to 512MB
297 movhi r3, #0x0800
298 add r6, r0, r3
299 ldr r3, [r8, #MACHINFO_PHYSIO]
300 orr r3, r3, r7
301 1: str r3, [r0], #4
302 add r3, r3, #1 << 20
303 teq r0, r6
304 bne 1b
305 #if defined(CONFIG_ARCH_NETWINDER) || defined(CONFIG_ARCH_CATS)
306 /*
307 * If we're using the NetWinder or CATS, we also need to map
308 * in the 16550-type serial port for the debug messages
309 */
310 add r0, r4, #0xff000000 >> 18
311 orr r3, r7, #0x7c000000
312 str r3, [r0]
313 #endif
314 #ifdef CONFIG_ARCH_RPC
315 /*
316 * Map in screen at 0x02000000 & SCREEN2_BASE
317 * Similar reasons here - for debug. This is
318 * only for Acorn RiscPC architectures.
319 */
320 add r0, r4, #0x02000000 >> 18
321 orr r3, r7, #0x02000000
322 str r3, [r0]
323 add r0, r4, #0xd8000000 >> 18
324 str r3, [r0]
325 #endif
326 #endif
327 mov pc, lr
328 .ltorg
330 #include "head-common.S"