arch/arm/mach-s3c2440/mach-anubis.c

   1 /* linux/arch/arm/mach-s3c2440/mach-anubis.c
   2  *
   3  * Copyright (c) 2003-2005 Simtec Electronics
   4  *      http://armlinux.simtec.co.uk/
   5  *      Ben Dooks <ben@simtec.co.uk>
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License version 2 as
   9  * published by the Free Software Foundation.
  10 */
  11
  12 #include <linux/kernel.h>
  13 #include <linux/types.h>
  14 #include <linux/interrupt.h>
  15 #include <linux/list.h>
  16 #include <linux/timer.h>
  17 #include <linux/init.h>
  18 #include <linux/serial_core.h>
  19 #include <linux/platform_device.h>
  20
  21 #include <linux/sm501.h>
  22 #include <linux/sm501-regs.h>
  23
  24 #include <asm/mach/arch.h>
  25 #include <asm/mach/map.h>
  26 #include <asm/mach/irq.h>
  27
  28 #include <asm/arch/anubis-map.h>
  29 #include <asm/arch/anubis-irq.h>
  30 #include <asm/arch/anubis-cpld.h>
  31
  32 #include <asm/hardware.h>
  33 #include <asm/io.h>
  34 #include <asm/irq.h>
  35 #include <asm/mach-types.h>
  36
  37 #include <asm/plat-s3c/regs-serial.h>
  38 #include <asm/arch/regs-gpio.h>
  39 #include <asm/arch/regs-mem.h>
  40 #include <asm/arch/regs-lcd.h>
  41 #include <asm/plat-s3c/nand.h>
  42
  43 #include <linux/mtd/mtd.h>
  44 #include <linux/mtd/nand.h>
  45 #include <linux/mtd/nand_ecc.h>
  46 #include <linux/mtd/partitions.h>
  47
  48 #include <net/ax88796.h>
  49
  50 #include <asm/plat-s3c24xx/clock.h>
  51 #include <asm/plat-s3c24xx/devs.h>
  52 #include <asm/plat-s3c24xx/cpu.h>
  53
  54 #define COPYRIGHT ", (c) 2005 Simtec Electronics"
  55
  56 static struct map_desc anubis_iodesc[] __initdata = {
  57   /* ISA IO areas */
  58
  59   {
  60         .virtual        = (u32)S3C24XX_VA_ISA_BYTE,
  61         .pfn            = __phys_to_pfn(0x0),
  62         .length         = SZ_4M,
  63         .type           = MT_DEVICE,
  64   }, {
  65         .virtual        = (u32)S3C24XX_VA_ISA_WORD,
  66         .pfn            = __phys_to_pfn(0x0),
  67         .length         = SZ_4M,
  68         .type           = MT_DEVICE,
  69   },
  70
  71   /* we could possibly compress the next set down into a set of smaller tables
  72    * pagetables, but that would mean using an L2 section, and it still means
  73    * we cannot actually feed the same register to an LDR due to 16K spacing
  74    */
  75
  76   /* CPLD control registers */
  77
  78   {
  79         .virtual        = (u32)ANUBIS_VA_CTRL1,
  80         .pfn            = __phys_to_pfn(ANUBIS_PA_CTRL1),
  81         .length         = SZ_4K,
  82         .type           = MT_DEVICE,
  83   }, {
  84         .virtual        = (u32)ANUBIS_VA_IDREG,
  85         .pfn            = __phys_to_pfn(ANUBIS_PA_IDREG),
  86         .length         = SZ_4K,
  87         .type           = MT_DEVICE,
  88   },
  89 };
  90
  91 #define UCON S3C2410_UCON_DEFAULT | S3C2410_UCON_UCLK
  92 #define ULCON S3C2410_LCON_CS8 | S3C2410_LCON_PNONE | S3C2410_LCON_STOPB
  93 #define UFCON S3C2410_UFCON_RXTRIG8 | S3C2410_UFCON_FIFOMODE
  94
  95 static struct s3c24xx_uart_clksrc anubis_serial_clocks[] = {
  96         [0] = {
  97                 .name           = "uclk",
  98                 .divisor        = 1,
  99                 .min_baud       = 0,
 100                 .max_baud       = 0,
 101         },
 102         [1] = {
 103                 .name           = "pclk",
 104                 .divisor        = 1,
 105                 .min_baud       = 0,
 106                 .max_baud       = 0,
 107         }
 108 };
 109
 110
 111 static struct s3c2410_uartcfg anubis_uartcfgs[] __initdata = {
 112         [0] = {
 113                 .hwport      = 0,
 114                 .flags       = 0,
 115                 .ucon        = UCON,
 116                 .ulcon       = ULCON,
 117                 .ufcon       = UFCON,
 118                 .clocks      = anubis_serial_clocks,
 119                 .clocks_size = ARRAY_SIZE(anubis_serial_clocks),
 120         },
 121         [1] = {
 122                 .hwport      = 2,
 123                 .flags       = 0,
 124                 .ucon        = UCON,
 125                 .ulcon       = ULCON,
 126                 .ufcon       = UFCON,
 127                 .clocks      = anubis_serial_clocks,
 128                 .clocks_size = ARRAY_SIZE(anubis_serial_clocks),
 129         },
 130 };
 131
 132 /* NAND Flash on Anubis board */
 133
 134 static int external_map[]   = { 2 };
 135 static int chip0_map[]      = { 0 };
 136 static int chip1_map[]      = { 1 };
 137
 138 static struct mtd_partition anubis_default_nand_part[] = {
 139         [0] = {
 140                 .name   = "Boot Agent",
 141                 .size   = SZ_16K,
 142                 .offset = 0,
 143         },
 144         [1] = {
 145                 .name   = "/boot",
 146                 .size   = SZ_4M - SZ_16K,
 147                 .offset = SZ_16K,
 148         },
 149         [2] = {
 150                 .name   = "user1",
 151                 .offset = SZ_4M,
 152                 .size   = SZ_32M - SZ_4M,
 153         },
 154         [3] = {
 155                 .name   = "user2",
 156                 .offset = SZ_32M,
 157                 .size   = MTDPART_SIZ_FULL,
 158         }
 159 };
 160
 161 static struct mtd_partition anubis_default_nand_part_large[] = {
 162         [0] = {
 163                 .name   = "Boot Agent",
 164                 .size   = SZ_128K,
 165                 .offset = 0,
 166         },
 167         [1] = {
 168                 .name   = "/boot",
 169                 .size   = SZ_4M - SZ_128K,
 170                 .offset = SZ_128K,
 171         },
 172         [2] = {
 173                 .name   = "user1",
 174                 .offset = SZ_4M,
 175                 .size   = SZ_32M - SZ_4M,
 176         },
 177         [3] = {
 178                 .name   = "user2",
 179                 .offset = SZ_32M,
 180                 .size   = MTDPART_SIZ_FULL,
 181         }
 182 };
 183
 184 /* the Anubis has 3 selectable slots for nand-flash, the two
 185  * on-board chip areas, as well as the external slot.
 186  *
 187  * Note, there is no current hot-plug support for the External
 188  * socket.
 189 */
 190
 191 static struct s3c2410_nand_set anubis_nand_sets[] = {
 192         [1] = {
 193                 .name           = "External",
 194                 .nr_chips       = 1,
 195                 .nr_map         = external_map,
 196                 .nr_partitions  = ARRAY_SIZE(anubis_default_nand_part),
 197                 .partitions     = anubis_default_nand_part,
 198         },
 199         [0] = {
 200                 .name           = "chip0",
 201                 .nr_chips       = 1,
 202                 .nr_map         = chip0_map,
 203                 .nr_partitions  = ARRAY_SIZE(anubis_default_nand_part),
 204                 .partitions     = anubis_default_nand_part,
 205         },
 206         [2] = {
 207                 .name           = "chip1",
 208                 .nr_chips       = 1,
 209                 .nr_map         = chip1_map,
 210                 .nr_partitions  = ARRAY_SIZE(anubis_default_nand_part),
 211                 .partitions     = anubis_default_nand_part,
 212         },
 213 };
 214
 215 static void anubis_nand_select(struct s3c2410_nand_set *set, int slot)
 216 {
 217         unsigned int tmp;
 218
 219         slot = set->nr_map[slot] & 3;
 220
 221         pr_debug("anubis_nand: selecting slot %d (set %p,%p)\n",
 222                  slot, set, set->nr_map);
 223
 224         tmp = __raw_readb(ANUBIS_VA_CTRL1);
 225         tmp &= ~ANUBIS_CTRL1_NANDSEL;
 226         tmp |= slot;
 227
 228         pr_debug("anubis_nand: ctrl1 now %02x\n", tmp);
 229
 230         __raw_writeb(tmp, ANUBIS_VA_CTRL1);
 231 }
 232
 233 static struct s3c2410_platform_nand anubis_nand_info = {
 234         .tacls          = 25,
 235         .twrph0         = 55,
 236         .twrph1         = 40,
 237         .nr_sets        = ARRAY_SIZE(anubis_nand_sets),
 238         .sets           = anubis_nand_sets,
 239         .select_chip    = anubis_nand_select,
 240 };
 241
 242 /* IDE channels */
 243
 244 static struct resource anubis_ide0_resource[] = {
 245         {
 246                 .start  = S3C2410_CS3,
 247                 .end    = S3C2410_CS3 + (8*32) - 1,
 248                 .flags  = IORESOURCE_MEM,
 249         }, {
 250                 .start  = S3C2410_CS3 + (1<<26),
 251                 .end    = S3C2410_CS3 + (1<<26) + (8*32) - 1,
 252                 .flags  = IORESOURCE_MEM,
 253         }, {
 254                 .start  = IRQ_IDE0,
 255                 .end    = IRQ_IDE0,
 256                 .flags  = IORESOURCE_IRQ,
 257         },
 258 };
 259
 260 static struct platform_device anubis_device_ide0 = {
 261         .name           = "simtec-ide",
 262         .id             = 0,
 263         .num_resources  = ARRAY_SIZE(anubis_ide0_resource),
 264         .resource       = anubis_ide0_resource,
 265 };
 266
 267 static struct resource anubis_ide1_resource[] = {
 268         {
 269                 .start  = S3C2410_CS4,
 270                 .end    = S3C2410_CS4 + (8*32) - 1,
 271                 .flags  = IORESOURCE_MEM,
 272         }, {
 273                 .start  = S3C2410_CS4 + (1<<26),
 274                 .end    = S3C2410_CS4 + (1<<26) + (8*32) - 1,
 275                 .flags  = IORESOURCE_MEM,
 276         }, {
 277                 .start  = IRQ_IDE0,
 278                 .end    = IRQ_IDE0,
 279                 .flags  = IORESOURCE_IRQ,
 280         },
 281 };
 282
 283
 284 static struct platform_device anubis_device_ide1 = {
 285         .name           = "simtec-ide",
 286         .id             = 1,
 287         .num_resources  = ARRAY_SIZE(anubis_ide1_resource),
 288         .resource       = anubis_ide1_resource,
 289 };
 290
 291 /* Asix AX88796 10/100 ethernet controller */
 292
 293 static struct ax_plat_data anubis_asix_platdata = {
 294         .flags          = AXFLG_MAC_FROMDEV,
 295         .wordlength     = 2,
 296         .dcr_val        = 0x48,
 297         .rcr_val        = 0x40,
 298 };
 299
 300 static struct resource anubis_asix_resource[] = {
 301         [0] = {
 302                 .start = S3C2410_CS5,
 303                 .end   = S3C2410_CS5 + (0x20 * 0x20) -1,
 304                 .flags = IORESOURCE_MEM
 305         },
 306         [1] = {
 307                 .start = IRQ_ASIX,
 308                 .end   = IRQ_ASIX,
 309                 .flags = IORESOURCE_IRQ
 310         }
 311 };
 312
 313 static struct platform_device anubis_device_asix = {
 314         .name           = "ax88796",
 315         .id             = 0,
 316         .num_resources  = ARRAY_SIZE(anubis_asix_resource),
 317         .resource       = anubis_asix_resource,
 318         .dev            = {
 319                 .platform_data = &anubis_asix_platdata,
 320         }
 321 };
 322
 323 /* SM501 */
 324
 325 static struct resource anubis_sm501_resource[] = {
 326         [0] = {
 327                 .start  = S3C2410_CS2,
 328                 .end    = S3C2410_CS2 + SZ_8M,
 329                 .flags  = IORESOURCE_MEM,
 330         },
 331         [1] = {
 332                 .start  = S3C2410_CS2 + SZ_64M - SZ_2M,
 333                 .end    = S3C2410_CS2 + SZ_64M - 1,
 334                 .flags  = IORESOURCE_MEM,
 335         },
 336         [2] = {
 337                 .start  = IRQ_EINT0,
 338                 .end    = IRQ_EINT0,
 339                 .flags  = IORESOURCE_IRQ,
 340         },
 341 };
 342
 343 static struct sm501_initdata anubis_sm501_initdata = {
 344         .gpio_high      = {
 345                 .set    = 0x3F000000,           /* 24bit panel */
 346                 .mask   = 0x0,
 347         },
 348         .misc_timing    = {
 349                 .set    = 0x010100,             /* SDRAM timing */
 350                 .mask   = 0x1F1F00,
 351         },
 352         .misc_control   = {
 353                 .set    = SM501_MISC_PNL_24BIT,
 354                 .mask   = 0,
 355         },
 356
 357         /* set the SDRAM and bus clocks */
 358         .mclk           = 72 * MHZ,
 359         .m1xclk         = 144 * MHZ,
 360 };
 361
 362 static struct sm501_platdata_gpio_i2c anubis_sm501_gpio_i2c[] = {
 363         [0] = {
 364                 .pin_scl        = 44,
 365                 .pin_sda        = 45,
 366         },
 367         [1] = {
 368                 .pin_scl        = 40,
 369                 .pin_sda        = 41,
 370         },
 371 };
 372
 373 static struct sm501_platdata anubis_sm501_platdata = {
 374         .init           = &anubis_sm501_initdata,
 375         .gpio_i2c       = anubis_sm501_gpio_i2c,
 376         .gpio_i2c_nr    = ARRAY_SIZE(anubis_sm501_gpio_i2c),
 377 };
 378
 379 static struct platform_device anubis_device_sm501 = {
 380         .name           = "sm501",
 381         .id             = 0,
 382         .num_resources  = ARRAY_SIZE(anubis_sm501_resource),
 383         .resource       = anubis_sm501_resource,
 384         .dev            = {
 385                 .platform_data = &anubis_sm501_platdata,
 386         },
 387 };
 388
 389 /* Standard Anubis devices */
 390
 391 static struct platform_device *anubis_devices[] __initdata = {
 392         &s3c_device_usb,
 393         &s3c_device_wdt,
 394         &s3c_device_adc,
 395         &s3c_device_i2c,
 396         &s3c_device_rtc,
 397         &s3c_device_nand,
 398         &anubis_device_ide0,
 399         &anubis_device_ide1,
 400         &anubis_device_asix,
 401         &anubis_device_sm501,
 402 };
 403
 404 static struct clk *anubis_clocks[] = {
 405         &s3c24xx_dclk0,
 406         &s3c24xx_dclk1,
 407         &s3c24xx_clkout0,
 408         &s3c24xx_clkout1,
 409         &s3c24xx_uclk,
 410 };
 411
 412 static void __init anubis_map_io(void)
 413 {
 414         /* initialise the clocks */
 415
 416         s3c24xx_dclk0.parent = &clk_upll;
 417         s3c24xx_dclk0.rate   = 12*1000*1000;
 418
 419         s3c24xx_dclk1.parent = &clk_upll;
 420         s3c24xx_dclk1.rate   = 24*1000*1000;
 421
 422         s3c24xx_clkout0.parent  = &s3c24xx_dclk0;
 423         s3c24xx_clkout1.parent  = &s3c24xx_dclk1;
 424
 425         s3c24xx_uclk.parent  = &s3c24xx_clkout1;
 426
 427         s3c24xx_register_clocks(anubis_clocks, ARRAY_SIZE(anubis_clocks));
 428
 429         s3c_device_nand.dev.platform_data = &anubis_nand_info;
 430
 431         s3c24xx_init_io(anubis_iodesc, ARRAY_SIZE(anubis_iodesc));
 432         s3c24xx_init_clocks(0);
 433         s3c24xx_init_uarts(anubis_uartcfgs, ARRAY_SIZE(anubis_uartcfgs));
 434
 435         /* check for the newer revision boards with large page nand */
 436
 437         if ((__raw_readb(ANUBIS_VA_IDREG) & ANUBIS_IDREG_REVMASK) >= 4) {
 438                 printk(KERN_INFO "ANUBIS-B detected (revision %d)\n",
 439                        __raw_readb(ANUBIS_VA_IDREG) & ANUBIS_IDREG_REVMASK);
 440                 anubis_nand_sets[0].partitions = anubis_default_nand_part_large;
 441                 anubis_nand_sets[0].nr_partitions = ARRAY_SIZE(anubis_default_nand_part_large);
 442         } else {
 443                 /* ensure that the GPIO is setup */
 444                 s3c2410_gpio_setpin(S3C2410_GPA0, 1);
 445         }
 446 }
 447
 448 static void __init anubis_init(void)
 449 {
 450         platform_add_devices(anubis_devices, ARRAY_SIZE(anubis_devices));
 451 }
 452
 453
 454 MACHINE_START(ANUBIS, "Simtec-Anubis")
 455         /* Maintainer: Ben Dooks <ben@simtec.co.uk> */
 456         .phys_io        = S3C2410_PA_UART,
 457         .io_pg_offst    = (((u32)S3C24XX_VA_UART) >> 18) & 0xfffc,
 458         .boot_params    = S3C2410_SDRAM_PA + 0x100,
 459         .map_io         = anubis_map_io,
 460         .init_machine   = anubis_init,
 461         .init_irq       = s3c24xx_init_irq,
 462         .timer          = &s3c24xx_timer,
 463 MACHINE_END