?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
ia64/kvm: compilation fix. export account_system_vtime.
[pv_ops_mirror.git] / arch / arm / plat-omap / gpio.c
blob1903a3491ee9ff7f330e90a3c9a7df5cd4897d22
1 /*
2 * linux/arch/arm/plat-omap/gpio.c
3 *
4 * Support functions for OMAP GPIO
5 *
6 * Copyright (C) 2003-2005 Nokia Corporation
7 * Written by Juha Yrjölä <juha.yrjola@nokia.com>
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 */
13
14 #include <linux/init.h>
15 #include <linux/module.h>
16 #include <linux/interrupt.h>
17 #include <linux/sysdev.h>
18 #include <linux/err.h>
19 #include <linux/clk.h>
20
21 #include <asm/hardware.h>
22 #include <asm/irq.h>
23 #include <asm/arch/irqs.h>
24 #include <asm/arch/gpio.h>
25 #include <asm/mach/irq.h>
26
27 #include <asm/io.h>
28
29 /*
30 * OMAP1510 GPIO registers
31 */
32 #define OMAP1510_GPIO_BASE (void __iomem *)0xfffce000
33 #define OMAP1510_GPIO_DATA_INPUT 0x00
34 #define OMAP1510_GPIO_DATA_OUTPUT 0x04
35 #define OMAP1510_GPIO_DIR_CONTROL 0x08
36 #define OMAP1510_GPIO_INT_CONTROL 0x0c
37 #define OMAP1510_GPIO_INT_MASK 0x10
38 #define OMAP1510_GPIO_INT_STATUS 0x14
39 #define OMAP1510_GPIO_PIN_CONTROL 0x18
40
41 #define OMAP1510_IH_GPIO_BASE 64
42
43 /*
44 * OMAP1610 specific GPIO registers
45 */
46 #define OMAP1610_GPIO1_BASE (void __iomem *)0xfffbe400
47 #define OMAP1610_GPIO2_BASE (void __iomem *)0xfffbec00
48 #define OMAP1610_GPIO3_BASE (void __iomem *)0xfffbb400
49 #define OMAP1610_GPIO4_BASE (void __iomem *)0xfffbbc00
50 #define OMAP1610_GPIO_REVISION 0x0000
51 #define OMAP1610_GPIO_SYSCONFIG 0x0010
52 #define OMAP1610_GPIO_SYSSTATUS 0x0014
53 #define OMAP1610_GPIO_IRQSTATUS1 0x0018
54 #define OMAP1610_GPIO_IRQENABLE1 0x001c
55 #define OMAP1610_GPIO_WAKEUPENABLE 0x0028
56 #define OMAP1610_GPIO_DATAIN 0x002c
57 #define OMAP1610_GPIO_DATAOUT 0x0030
58 #define OMAP1610_GPIO_DIRECTION 0x0034
59 #define OMAP1610_GPIO_EDGE_CTRL1 0x0038
60 #define OMAP1610_GPIO_EDGE_CTRL2 0x003c
61 #define OMAP1610_GPIO_CLEAR_IRQENABLE1 0x009c
62 #define OMAP1610_GPIO_CLEAR_WAKEUPENA 0x00a8
63 #define OMAP1610_GPIO_CLEAR_DATAOUT 0x00b0
64 #define OMAP1610_GPIO_SET_IRQENABLE1 0x00dc
65 #define OMAP1610_GPIO_SET_WAKEUPENA 0x00e8
66 #define OMAP1610_GPIO_SET_DATAOUT 0x00f0
67
68 /*
69 * OMAP730 specific GPIO registers
70 */
71 #define OMAP730_GPIO1_BASE (void __iomem *)0xfffbc000
72 #define OMAP730_GPIO2_BASE (void __iomem *)0xfffbc800
73 #define OMAP730_GPIO3_BASE (void __iomem *)0xfffbd000
74 #define OMAP730_GPIO4_BASE (void __iomem *)0xfffbd800
75 #define OMAP730_GPIO5_BASE (void __iomem *)0xfffbe000
76 #define OMAP730_GPIO6_BASE (void __iomem *)0xfffbe800
77 #define OMAP730_GPIO_DATA_INPUT 0x00
78 #define OMAP730_GPIO_DATA_OUTPUT 0x04
79 #define OMAP730_GPIO_DIR_CONTROL 0x08
80 #define OMAP730_GPIO_INT_CONTROL 0x0c
81 #define OMAP730_GPIO_INT_MASK 0x10
82 #define OMAP730_GPIO_INT_STATUS 0x14
83
84 /*
85 * omap24xx specific GPIO registers
86 */
87 #define OMAP242X_GPIO1_BASE (void __iomem *)0x48018000
88 #define OMAP242X_GPIO2_BASE (void __iomem *)0x4801a000
89 #define OMAP242X_GPIO3_BASE (void __iomem *)0x4801c000
90 #define OMAP242X_GPIO4_BASE (void __iomem *)0x4801e000
91
92 #define OMAP243X_GPIO1_BASE (void __iomem *)0x4900C000
93 #define OMAP243X_GPIO2_BASE (void __iomem *)0x4900E000
94 #define OMAP243X_GPIO3_BASE (void __iomem *)0x49010000
95 #define OMAP243X_GPIO4_BASE (void __iomem *)0x49012000
96 #define OMAP243X_GPIO5_BASE (void __iomem *)0x480B6000
97
98 #define OMAP24XX_GPIO_REVISION 0x0000
99 #define OMAP24XX_GPIO_SYSCONFIG 0x0010
100 #define OMAP24XX_GPIO_SYSSTATUS 0x0014
101 #define OMAP24XX_GPIO_IRQSTATUS1 0x0018
102 #define OMAP24XX_GPIO_IRQSTATUS2 0x0028
103 #define OMAP24XX_GPIO_IRQENABLE2 0x002c
104 #define OMAP24XX_GPIO_IRQENABLE1 0x001c
105 #define OMAP24XX_GPIO_CTRL 0x0030
106 #define OMAP24XX_GPIO_OE 0x0034
107 #define OMAP24XX_GPIO_DATAIN 0x0038
108 #define OMAP24XX_GPIO_DATAOUT 0x003c
109 #define OMAP24XX_GPIO_LEVELDETECT0 0x0040
110 #define OMAP24XX_GPIO_LEVELDETECT1 0x0044
111 #define OMAP24XX_GPIO_RISINGDETECT 0x0048
112 #define OMAP24XX_GPIO_FALLINGDETECT 0x004c
113 #define OMAP24XX_GPIO_DEBOUNCE_EN 0x0050
114 #define OMAP24XX_GPIO_DEBOUNCE_VAL 0x0054
115 #define OMAP24XX_GPIO_CLEARIRQENABLE1 0x0060
116 #define OMAP24XX_GPIO_SETIRQENABLE1 0x0064
117 #define OMAP24XX_GPIO_CLEARWKUENA 0x0080
118 #define OMAP24XX_GPIO_SETWKUENA 0x0084
119 #define OMAP24XX_GPIO_CLEARDATAOUT 0x0090
120 #define OMAP24XX_GPIO_SETDATAOUT 0x0094
121
122 /*
123 * omap34xx specific GPIO registers
124 */
125
126 #define OMAP34XX_GPIO1_BASE (void __iomem *)0x48310000
127 #define OMAP34XX_GPIO2_BASE (void __iomem *)0x49050000
128 #define OMAP34XX_GPIO3_BASE (void __iomem *)0x49052000
129 #define OMAP34XX_GPIO4_BASE (void __iomem *)0x49054000
130 #define OMAP34XX_GPIO5_BASE (void __iomem *)0x49056000
131 #define OMAP34XX_GPIO6_BASE (void __iomem *)0x49058000
132
133
134 struct gpio_bank {
135 void __iomem *base;
136 u16 irq;
137 u16 virtual_irq_start;
138 int method;
139 #if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
140 u32 suspend_wakeup;
141 u32 saved_wakeup;
142 #endif
143 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
144 u32 non_wakeup_gpios;
145 u32 enabled_non_wakeup_gpios;
146
147 u32 saved_datain;
148 u32 saved_fallingdetect;
149 u32 saved_risingdetect;
150 #endif
151 u32 level_mask;
152 spinlock_t lock;
153 struct gpio_chip chip;
154 };
155
156 #define METHOD_MPUIO 0
157 #define METHOD_GPIO_1510 1
158 #define METHOD_GPIO_1610 2
159 #define METHOD_GPIO_730 3
160 #define METHOD_GPIO_24XX 4
161
162 #ifdef CONFIG_ARCH_OMAP16XX
163 static struct gpio_bank gpio_bank_1610[5] = {
164 { OMAP_MPUIO_BASE, INT_MPUIO, IH_MPUIO_BASE, METHOD_MPUIO},
165 { OMAP1610_GPIO1_BASE, INT_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_1610 },
166 { OMAP1610_GPIO2_BASE, INT_1610_GPIO_BANK2, IH_GPIO_BASE + 16, METHOD_GPIO_1610 },
167 { OMAP1610_GPIO3_BASE, INT_1610_GPIO_BANK3, IH_GPIO_BASE + 32, METHOD_GPIO_1610 },
168 { OMAP1610_GPIO4_BASE, INT_1610_GPIO_BANK4, IH_GPIO_BASE + 48, METHOD_GPIO_1610 },
169 };
170 #endif
171
172 #ifdef CONFIG_ARCH_OMAP15XX
173 static struct gpio_bank gpio_bank_1510[2] = {
174 { OMAP_MPUIO_BASE, INT_MPUIO, IH_MPUIO_BASE, METHOD_MPUIO },
175 { OMAP1510_GPIO_BASE, INT_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_1510 }
176 };
177 #endif
178
179 #ifdef CONFIG_ARCH_OMAP730
180 static struct gpio_bank gpio_bank_730[7] = {
181 { OMAP_MPUIO_BASE, INT_730_MPUIO, IH_MPUIO_BASE, METHOD_MPUIO },
182 { OMAP730_GPIO1_BASE, INT_730_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_730 },
183 { OMAP730_GPIO2_BASE, INT_730_GPIO_BANK2, IH_GPIO_BASE + 32, METHOD_GPIO_730 },
184 { OMAP730_GPIO3_BASE, INT_730_GPIO_BANK3, IH_GPIO_BASE + 64, METHOD_GPIO_730 },
185 { OMAP730_GPIO4_BASE, INT_730_GPIO_BANK4, IH_GPIO_BASE + 96, METHOD_GPIO_730 },
186 { OMAP730_GPIO5_BASE, INT_730_GPIO_BANK5, IH_GPIO_BASE + 128, METHOD_GPIO_730 },
187 { OMAP730_GPIO6_BASE, INT_730_GPIO_BANK6, IH_GPIO_BASE + 160, METHOD_GPIO_730 },
188 };
189 #endif
190
191 #ifdef CONFIG_ARCH_OMAP24XX
192
193 static struct gpio_bank gpio_bank_242x[4] = {
194 { OMAP242X_GPIO1_BASE, INT_24XX_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_24XX },
195 { OMAP242X_GPIO2_BASE, INT_24XX_GPIO_BANK2, IH_GPIO_BASE + 32, METHOD_GPIO_24XX },
196 { OMAP242X_GPIO3_BASE, INT_24XX_GPIO_BANK3, IH_GPIO_BASE + 64, METHOD_GPIO_24XX },
197 { OMAP242X_GPIO4_BASE, INT_24XX_GPIO_BANK4, IH_GPIO_BASE + 96, METHOD_GPIO_24XX },
198 };
199
200 static struct gpio_bank gpio_bank_243x[5] = {
201 { OMAP243X_GPIO1_BASE, INT_24XX_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_24XX },
202 { OMAP243X_GPIO2_BASE, INT_24XX_GPIO_BANK2, IH_GPIO_BASE + 32, METHOD_GPIO_24XX },
203 { OMAP243X_GPIO3_BASE, INT_24XX_GPIO_BANK3, IH_GPIO_BASE + 64, METHOD_GPIO_24XX },
204 { OMAP243X_GPIO4_BASE, INT_24XX_GPIO_BANK4, IH_GPIO_BASE + 96, METHOD_GPIO_24XX },
205 { OMAP243X_GPIO5_BASE, INT_24XX_GPIO_BANK5, IH_GPIO_BASE + 128, METHOD_GPIO_24XX },
206 };
207
208 #endif
209
210 #ifdef CONFIG_ARCH_OMAP34XX
211 static struct gpio_bank gpio_bank_34xx[6] = {
212 { OMAP34XX_GPIO1_BASE, INT_34XX_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_24XX },
213 { OMAP34XX_GPIO2_BASE, INT_34XX_GPIO_BANK2, IH_GPIO_BASE + 32, METHOD_GPIO_24XX },
214 { OMAP34XX_GPIO3_BASE, INT_34XX_GPIO_BANK3, IH_GPIO_BASE + 64, METHOD_GPIO_24XX },
215 { OMAP34XX_GPIO4_BASE, INT_34XX_GPIO_BANK4, IH_GPIO_BASE + 96, METHOD_GPIO_24XX },
216 { OMAP34XX_GPIO5_BASE, INT_34XX_GPIO_BANK5, IH_GPIO_BASE + 128, METHOD_GPIO_24XX },
217 { OMAP34XX_GPIO6_BASE, INT_34XX_GPIO_BANK6, IH_GPIO_BASE + 160, METHOD_GPIO_24XX },
218 };
219
220 #endif
221
222 static struct gpio_bank *gpio_bank;
223 static int gpio_bank_count;
224
225 static inline struct gpio_bank *get_gpio_bank(int gpio)
226 {
227 if (cpu_is_omap15xx()) {
228 if (OMAP_GPIO_IS_MPUIO(gpio))
229 return &gpio_bank[0];
230 return &gpio_bank[1];
231 }
232 if (cpu_is_omap16xx()) {
233 if (OMAP_GPIO_IS_MPUIO(gpio))
234 return &gpio_bank[0];
235 return &gpio_bank[1 + (gpio >> 4)];
236 }
237 if (cpu_is_omap730()) {
238 if (OMAP_GPIO_IS_MPUIO(gpio))
239 return &gpio_bank[0];
240 return &gpio_bank[1 + (gpio >> 5)];
241 }
242 if (cpu_is_omap24xx())
243 return &gpio_bank[gpio >> 5];
244 if (cpu_is_omap34xx())
245 return &gpio_bank[gpio >> 5];
246 }
247
248 static inline int get_gpio_index(int gpio)
249 {
250 if (cpu_is_omap730())
251 return gpio & 0x1f;
252 if (cpu_is_omap24xx())
253 return gpio & 0x1f;
254 if (cpu_is_omap34xx())
255 return gpio & 0x1f;
256 return gpio & 0x0f;
257 }
258
259 static inline int gpio_valid(int gpio)
260 {
261 if (gpio < 0)
262 return -1;
263 if (cpu_class_is_omap1() && OMAP_GPIO_IS_MPUIO(gpio)) {
264 if (gpio >= OMAP_MAX_GPIO_LINES + 16)
265 return -1;
266 return 0;
267 }
268 if (cpu_is_omap15xx() && gpio < 16)
269 return 0;
270 if ((cpu_is_omap16xx()) && gpio < 64)
271 return 0;
272 if (cpu_is_omap730() && gpio < 192)
273 return 0;
274 if (cpu_is_omap24xx() && gpio < 128)
275 return 0;
276 if (cpu_is_omap34xx() && gpio < 160)
277 return 0;
278 return -1;
279 }
280
281 static int check_gpio(int gpio)
282 {
283 if (unlikely(gpio_valid(gpio)) < 0) {
284 printk(KERN_ERR "omap-gpio: invalid GPIO %d\n", gpio);
285 dump_stack();
286 return -1;
287 }
288 return 0;
289 }
290
291 static void _set_gpio_direction(struct gpio_bank *bank, int gpio, int is_input)
292 {
293 void __iomem *reg = bank->base;
294 u32 l;
295
296 switch (bank->method) {
297 #ifdef CONFIG_ARCH_OMAP1
298 case METHOD_MPUIO:
299 reg += OMAP_MPUIO_IO_CNTL;
300 break;
301 #endif
302 #ifdef CONFIG_ARCH_OMAP15XX
303 case METHOD_GPIO_1510:
304 reg += OMAP1510_GPIO_DIR_CONTROL;
305 break;
306 #endif
307 #ifdef CONFIG_ARCH_OMAP16XX
308 case METHOD_GPIO_1610:
309 reg += OMAP1610_GPIO_DIRECTION;
310 break;
311 #endif
312 #ifdef CONFIG_ARCH_OMAP730
313 case METHOD_GPIO_730:
314 reg += OMAP730_GPIO_DIR_CONTROL;
315 break;
316 #endif
317 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
318 case METHOD_GPIO_24XX:
319 reg += OMAP24XX_GPIO_OE;
320 break;
321 #endif
322 default:
323 WARN_ON(1);
324 return;
325 }
326 l = __raw_readl(reg);
327 if (is_input)
328 l |= 1 << gpio;
329 else
330 l &= ~(1 << gpio);
331 __raw_writel(l, reg);
332 }
333
334 void omap_set_gpio_direction(int gpio, int is_input)
335 {
336 struct gpio_bank *bank;
337 unsigned long flags;
338
339 if (check_gpio(gpio) < 0)
340 return;
341 bank = get_gpio_bank(gpio);
342 spin_lock_irqsave(&bank->lock, flags);
343 _set_gpio_direction(bank, get_gpio_index(gpio), is_input);
344 spin_unlock_irqrestore(&bank->lock, flags);
345 }
346
347 static void _set_gpio_dataout(struct gpio_bank *bank, int gpio, int enable)
348 {
349 void __iomem *reg = bank->base;
350 u32 l = 0;
351
352 switch (bank->method) {
353 #ifdef CONFIG_ARCH_OMAP1
354 case METHOD_MPUIO:
355 reg += OMAP_MPUIO_OUTPUT;
356 l = __raw_readl(reg);
357 if (enable)
358 l |= 1 << gpio;
359 else
360 l &= ~(1 << gpio);
361 break;
362 #endif
363 #ifdef CONFIG_ARCH_OMAP15XX
364 case METHOD_GPIO_1510:
365 reg += OMAP1510_GPIO_DATA_OUTPUT;
366 l = __raw_readl(reg);
367 if (enable)
368 l |= 1 << gpio;
369 else
370 l &= ~(1 << gpio);
371 break;
372 #endif
373 #ifdef CONFIG_ARCH_OMAP16XX
374 case METHOD_GPIO_1610:
375 if (enable)
376 reg += OMAP1610_GPIO_SET_DATAOUT;
377 else
378 reg += OMAP1610_GPIO_CLEAR_DATAOUT;
379 l = 1 << gpio;
380 break;
381 #endif
382 #ifdef CONFIG_ARCH_OMAP730
383 case METHOD_GPIO_730:
384 reg += OMAP730_GPIO_DATA_OUTPUT;
385 l = __raw_readl(reg);
386 if (enable)
387 l |= 1 << gpio;
388 else
389 l &= ~(1 << gpio);
390 break;
391 #endif
392 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
393 case METHOD_GPIO_24XX:
394 if (enable)
395 reg += OMAP24XX_GPIO_SETDATAOUT;
396 else
397 reg += OMAP24XX_GPIO_CLEARDATAOUT;
398 l = 1 << gpio;
399 break;
400 #endif
401 default:
402 WARN_ON(1);
403 return;
404 }
405 __raw_writel(l, reg);
406 }
407
408 void omap_set_gpio_dataout(int gpio, int enable)
409 {
410 struct gpio_bank *bank;
411 unsigned long flags;
412
413 if (check_gpio(gpio) < 0)
414 return;
415 bank = get_gpio_bank(gpio);
416 spin_lock_irqsave(&bank->lock, flags);
417 _set_gpio_dataout(bank, get_gpio_index(gpio), enable);
418 spin_unlock_irqrestore(&bank->lock, flags);
419 }
420
421 int omap_get_gpio_datain(int gpio)
422 {
423 struct gpio_bank *bank;
424 void __iomem *reg;
425
426 if (check_gpio(gpio) < 0)
427 return -EINVAL;
428 bank = get_gpio_bank(gpio);
429 reg = bank->base;
430 switch (bank->method) {
431 #ifdef CONFIG_ARCH_OMAP1
432 case METHOD_MPUIO:
433 reg += OMAP_MPUIO_INPUT_LATCH;
434 break;
435 #endif
436 #ifdef CONFIG_ARCH_OMAP15XX
437 case METHOD_GPIO_1510:
438 reg += OMAP1510_GPIO_DATA_INPUT;
439 break;
440 #endif
441 #ifdef CONFIG_ARCH_OMAP16XX
442 case METHOD_GPIO_1610:
443 reg += OMAP1610_GPIO_DATAIN;
444 break;
445 #endif
446 #ifdef CONFIG_ARCH_OMAP730
447 case METHOD_GPIO_730:
448 reg += OMAP730_GPIO_DATA_INPUT;
449 break;
450 #endif
451 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
452 case METHOD_GPIO_24XX:
453 reg += OMAP24XX_GPIO_DATAIN;
454 break;
455 #endif
456 default:
457 return -EINVAL;
458 }
459 return (__raw_readl(reg)
460 & (1 << get_gpio_index(gpio))) != 0;
461 }
462
463 #define MOD_REG_BIT(reg, bit_mask, set) \
464 do { \
465 int l = __raw_readl(base + reg); \
466 if (set) l |= bit_mask; \
467 else l &= ~bit_mask; \
468 __raw_writel(l, base + reg); \
469 } while(0)
470
471 void omap_set_gpio_debounce(int gpio, int enable)
472 {
473 struct gpio_bank *bank;
474 void __iomem *reg;
475 u32 val, l = 1 << get_gpio_index(gpio);
476
477 if (cpu_class_is_omap1())
478 return;
479
480 bank = get_gpio_bank(gpio);
481 reg = bank->base;
482
483 reg += OMAP24XX_GPIO_DEBOUNCE_EN;
484 val = __raw_readl(reg);
485
486 if (enable)
487 val |= l;
488 else
489 val &= ~l;
490
491 __raw_writel(val, reg);
492 }
493 EXPORT_SYMBOL(omap_set_gpio_debounce);
494
495 void omap_set_gpio_debounce_time(int gpio, int enc_time)
496 {
497 struct gpio_bank *bank;
498 void __iomem *reg;
499
500 if (cpu_class_is_omap1())
501 return;
502
503 bank = get_gpio_bank(gpio);
504 reg = bank->base;
505
506 enc_time &= 0xff;
507 reg += OMAP24XX_GPIO_DEBOUNCE_VAL;
508 __raw_writel(enc_time, reg);
509 }
510 EXPORT_SYMBOL(omap_set_gpio_debounce_time);
511
512 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
513 static inline void set_24xx_gpio_triggering(struct gpio_bank *bank, int gpio,
514 int trigger)
515 {
516 void __iomem *base = bank->base;
517 u32 gpio_bit = 1 << gpio;
518
519 MOD_REG_BIT(OMAP24XX_GPIO_LEVELDETECT0, gpio_bit,
520 trigger & __IRQT_LOWLVL);
521 MOD_REG_BIT(OMAP24XX_GPIO_LEVELDETECT1, gpio_bit,
522 trigger & __IRQT_HIGHLVL);
523 MOD_REG_BIT(OMAP24XX_GPIO_RISINGDETECT, gpio_bit,
524 trigger & __IRQT_RISEDGE);
525 MOD_REG_BIT(OMAP24XX_GPIO_FALLINGDETECT, gpio_bit,
526 trigger & __IRQT_FALEDGE);
527
528 if (likely(!(bank->non_wakeup_gpios & gpio_bit))) {
529 if (trigger != 0)
530 __raw_writel(1 << gpio, bank->base
531 + OMAP24XX_GPIO_SETWKUENA);
532 else
533 __raw_writel(1 << gpio, bank->base
534 + OMAP24XX_GPIO_CLEARWKUENA);
535 } else {
536 if (trigger != 0)
537 bank->enabled_non_wakeup_gpios |= gpio_bit;
538 else
539 bank->enabled_non_wakeup_gpios &= ~gpio_bit;
540 }
541
542 bank->level_mask =
543 __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT0) |
544 __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT1);
545 }
546 #endif
547
548 static int _set_gpio_triggering(struct gpio_bank *bank, int gpio, int trigger)
549 {
550 void __iomem *reg = bank->base;
551 u32 l = 0;
552
553 switch (bank->method) {
554 #ifdef CONFIG_ARCH_OMAP1
555 case METHOD_MPUIO:
556 reg += OMAP_MPUIO_GPIO_INT_EDGE;
557 l = __raw_readl(reg);
558 if (trigger & __IRQT_RISEDGE)
559 l |= 1 << gpio;
560 else if (trigger & __IRQT_FALEDGE)
561 l &= ~(1 << gpio);
562 else
563 goto bad;
564 break;
565 #endif
566 #ifdef CONFIG_ARCH_OMAP15XX
567 case METHOD_GPIO_1510:
568 reg += OMAP1510_GPIO_INT_CONTROL;
569 l = __raw_readl(reg);
570 if (trigger & __IRQT_RISEDGE)
571 l |= 1 << gpio;
572 else if (trigger & __IRQT_FALEDGE)
573 l &= ~(1 << gpio);
574 else
575 goto bad;
576 break;
577 #endif
578 #ifdef CONFIG_ARCH_OMAP16XX
579 case METHOD_GPIO_1610:
580 if (gpio & 0x08)
581 reg += OMAP1610_GPIO_EDGE_CTRL2;
582 else
583 reg += OMAP1610_GPIO_EDGE_CTRL1;
584 gpio &= 0x07;
585 l = __raw_readl(reg);
586 l &= ~(3 << (gpio << 1));
587 if (trigger & __IRQT_RISEDGE)
588 l |= 2 << (gpio << 1);
589 if (trigger & __IRQT_FALEDGE)
590 l |= 1 << (gpio << 1);
591 if (trigger)
592 /* Enable wake-up during idle for dynamic tick */
593 __raw_writel(1 << gpio, bank->base + OMAP1610_GPIO_SET_WAKEUPENA);
594 else
595 __raw_writel(1 << gpio, bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA);
596 break;
597 #endif
598 #ifdef CONFIG_ARCH_OMAP730
599 case METHOD_GPIO_730:
600 reg += OMAP730_GPIO_INT_CONTROL;
601 l = __raw_readl(reg);
602 if (trigger & __IRQT_RISEDGE)
603 l |= 1 << gpio;
604 else if (trigger & __IRQT_FALEDGE)
605 l &= ~(1 << gpio);
606 else
607 goto bad;
608 break;
609 #endif
610 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
611 case METHOD_GPIO_24XX:
612 set_24xx_gpio_triggering(bank, gpio, trigger);
613 break;
614 #endif
615 default:
616 goto bad;
617 }
618 __raw_writel(l, reg);
619 return 0;
620 bad:
621 return -EINVAL;
622 }
623
624 static int gpio_irq_type(unsigned irq, unsigned type)
625 {
626 struct gpio_bank *bank;
627 unsigned gpio;
628 int retval;
629 unsigned long flags;
630
631 if (!cpu_class_is_omap2() && irq > IH_MPUIO_BASE)
632 gpio = OMAP_MPUIO(irq - IH_MPUIO_BASE);
633 else
634 gpio = irq - IH_GPIO_BASE;
635
636 if (check_gpio(gpio) < 0)
637 return -EINVAL;
638
639 if (type & ~IRQ_TYPE_SENSE_MASK)
640 return -EINVAL;
641
642 /* OMAP1 allows only only edge triggering */
643 if (!cpu_class_is_omap2()
644 && (type & (IRQ_TYPE_LEVEL_LOW|IRQ_TYPE_LEVEL_HIGH)))
645 return -EINVAL;
646
647 bank = get_irq_chip_data(irq);
648 spin_lock_irqsave(&bank->lock, flags);
649 retval = _set_gpio_triggering(bank, get_gpio_index(gpio), type);
650 if (retval == 0) {
651 irq_desc[irq].status &= ~IRQ_TYPE_SENSE_MASK;
652 irq_desc[irq].status |= type;
653 }
654 spin_unlock_irqrestore(&bank->lock, flags);
655
656 if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH))
657 __set_irq_handler_unlocked(irq, handle_level_irq);
658 else if (type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
659 __set_irq_handler_unlocked(irq, handle_edge_irq);
660
661 return retval;
662 }
663
664 static void _clear_gpio_irqbank(struct gpio_bank *bank, int gpio_mask)
665 {
666 void __iomem *reg = bank->base;
667
668 switch (bank->method) {
669 #ifdef CONFIG_ARCH_OMAP1
670 case METHOD_MPUIO:
671 /* MPUIO irqstatus is reset by reading the status register,
672 * so do nothing here */
673 return;
674 #endif
675 #ifdef CONFIG_ARCH_OMAP15XX
676 case METHOD_GPIO_1510:
677 reg += OMAP1510_GPIO_INT_STATUS;
678 break;
679 #endif
680 #ifdef CONFIG_ARCH_OMAP16XX
681 case METHOD_GPIO_1610:
682 reg += OMAP1610_GPIO_IRQSTATUS1;
683 break;
684 #endif
685 #ifdef CONFIG_ARCH_OMAP730
686 case METHOD_GPIO_730:
687 reg += OMAP730_GPIO_INT_STATUS;
688 break;
689 #endif
690 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
691 case METHOD_GPIO_24XX:
692 reg += OMAP24XX_GPIO_IRQSTATUS1;
693 break;
694 #endif
695 default:
696 WARN_ON(1);
697 return;
698 }
699 __raw_writel(gpio_mask, reg);
700
701 /* Workaround for clearing DSP GPIO interrupts to allow retention */
702 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
703 if (cpu_is_omap24xx() || cpu_is_omap34xx())
704 __raw_writel(gpio_mask, bank->base + OMAP24XX_GPIO_IRQSTATUS2);
705 #endif
706 }
707
708 static inline void _clear_gpio_irqstatus(struct gpio_bank *bank, int gpio)
709 {
710 _clear_gpio_irqbank(bank, 1 << get_gpio_index(gpio));
711 }
712
713 static u32 _get_gpio_irqbank_mask(struct gpio_bank *bank)
714 {
715 void __iomem *reg = bank->base;
716 int inv = 0;
717 u32 l;
718 u32 mask;
719
720 switch (bank->method) {
721 #ifdef CONFIG_ARCH_OMAP1
722 case METHOD_MPUIO:
723 reg += OMAP_MPUIO_GPIO_MASKIT;
724 mask = 0xffff;
725 inv = 1;
726 break;
727 #endif
728 #ifdef CONFIG_ARCH_OMAP15XX
729 case METHOD_GPIO_1510:
730 reg += OMAP1510_GPIO_INT_MASK;
731 mask = 0xffff;
732 inv = 1;
733 break;
734 #endif
735 #ifdef CONFIG_ARCH_OMAP16XX
736 case METHOD_GPIO_1610:
737 reg += OMAP1610_GPIO_IRQENABLE1;
738 mask = 0xffff;
739 break;
740 #endif
741 #ifdef CONFIG_ARCH_OMAP730
742 case METHOD_GPIO_730:
743 reg += OMAP730_GPIO_INT_MASK;
744 mask = 0xffffffff;
745 inv = 1;
746 break;
747 #endif
748 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
749 case METHOD_GPIO_24XX:
750 reg += OMAP24XX_GPIO_IRQENABLE1;
751 mask = 0xffffffff;
752 break;
753 #endif
754 default:
755 WARN_ON(1);
756 return 0;
757 }
758
759 l = __raw_readl(reg);
760 if (inv)
761 l = ~l;
762 l &= mask;
763 return l;
764 }
765
766 static void _enable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask, int enable)
767 {
768 void __iomem *reg = bank->base;
769 u32 l;
770
771 switch (bank->method) {
772 #ifdef CONFIG_ARCH_OMAP1
773 case METHOD_MPUIO:
774 reg += OMAP_MPUIO_GPIO_MASKIT;
775 l = __raw_readl(reg);
776 if (enable)
777 l &= ~(gpio_mask);
778 else
779 l |= gpio_mask;
780 break;
781 #endif
782 #ifdef CONFIG_ARCH_OMAP15XX
783 case METHOD_GPIO_1510:
784 reg += OMAP1510_GPIO_INT_MASK;
785 l = __raw_readl(reg);
786 if (enable)
787 l &= ~(gpio_mask);
788 else
789 l |= gpio_mask;
790 break;
791 #endif
792 #ifdef CONFIG_ARCH_OMAP16XX
793 case METHOD_GPIO_1610:
794 if (enable)
795 reg += OMAP1610_GPIO_SET_IRQENABLE1;
796 else
797 reg += OMAP1610_GPIO_CLEAR_IRQENABLE1;
798 l = gpio_mask;
799 break;
800 #endif
801 #ifdef CONFIG_ARCH_OMAP730
802 case METHOD_GPIO_730:
803 reg += OMAP730_GPIO_INT_MASK;
804 l = __raw_readl(reg);
805 if (enable)
806 l &= ~(gpio_mask);
807 else
808 l |= gpio_mask;
809 break;
810 #endif
811 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
812 case METHOD_GPIO_24XX:
813 if (enable)
814 reg += OMAP24XX_GPIO_SETIRQENABLE1;
815 else
816 reg += OMAP24XX_GPIO_CLEARIRQENABLE1;
817 l = gpio_mask;
818 break;
819 #endif
820 default:
821 WARN_ON(1);
822 return;
823 }
824 __raw_writel(l, reg);
825 }
826
827 static inline void _set_gpio_irqenable(struct gpio_bank *bank, int gpio, int enable)
828 {
829 _enable_gpio_irqbank(bank, 1 << get_gpio_index(gpio), enable);
830 }
831
832 /*
833 * Note that ENAWAKEUP needs to be enabled in GPIO_SYSCONFIG register.
834 * 1510 does not seem to have a wake-up register. If JTAG is connected
835 * to the target, system will wake up always on GPIO events. While
836 * system is running all registered GPIO interrupts need to have wake-up
837 * enabled. When system is suspended, only selected GPIO interrupts need
838 * to have wake-up enabled.
839 */
840 static int _set_gpio_wakeup(struct gpio_bank *bank, int gpio, int enable)
841 {
842 unsigned long flags;
843
844 switch (bank->method) {
845 #ifdef CONFIG_ARCH_OMAP16XX
846 case METHOD_MPUIO:
847 case METHOD_GPIO_1610:
848 spin_lock_irqsave(&bank->lock, flags);
849 if (enable) {
850 bank->suspend_wakeup |= (1 << gpio);
851 enable_irq_wake(bank->irq);
852 } else {
853 disable_irq_wake(bank->irq);
854 bank->suspend_wakeup &= ~(1 << gpio);
855 }
856 spin_unlock_irqrestore(&bank->lock, flags);
857 return 0;
858 #endif
859 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
860 case METHOD_GPIO_24XX:
861 if (bank->non_wakeup_gpios & (1 << gpio)) {
862 printk(KERN_ERR "Unable to modify wakeup on "
863 "non-wakeup GPIO%d\n",
864 (bank - gpio_bank) * 32 + gpio);
865 return -EINVAL;
866 }
867 spin_lock_irqsave(&bank->lock, flags);
868 if (enable) {
869 bank->suspend_wakeup |= (1 << gpio);
870 enable_irq_wake(bank->irq);
871 } else {
872 disable_irq_wake(bank->irq);
873 bank->suspend_wakeup &= ~(1 << gpio);
874 }
875 spin_unlock_irqrestore(&bank->lock, flags);
876 return 0;
877 #endif
878 default:
879 printk(KERN_ERR "Can't enable GPIO wakeup for method %i\n",
880 bank->method);
881 return -EINVAL;
882 }
883 }
884
885 static void _reset_gpio(struct gpio_bank *bank, int gpio)
886 {
887 _set_gpio_direction(bank, get_gpio_index(gpio), 1);
888 _set_gpio_irqenable(bank, gpio, 0);
889 _clear_gpio_irqstatus(bank, gpio);
890 _set_gpio_triggering(bank, get_gpio_index(gpio), IRQT_NOEDGE);
891 }
892
893 /* Use disable_irq_wake() and enable_irq_wake() functions from drivers */
894 static int gpio_wake_enable(unsigned int irq, unsigned int enable)
895 {
896 unsigned int gpio = irq - IH_GPIO_BASE;
897 struct gpio_bank *bank;
898 int retval;
899
900 if (check_gpio(gpio) < 0)
901 return -ENODEV;
902 bank = get_irq_chip_data(irq);
903 retval = _set_gpio_wakeup(bank, get_gpio_index(gpio), enable);
904
905 return retval;
906 }
907
908 int omap_request_gpio(int gpio)
909 {
910 struct gpio_bank *bank;
911 unsigned long flags;
912 int status;
913
914 if (check_gpio(gpio) < 0)
915 return -EINVAL;
916
917 status = gpio_request(gpio, NULL);
918 if (status < 0)
919 return status;
920
921 bank = get_gpio_bank(gpio);
922 spin_lock_irqsave(&bank->lock, flags);
923
924 /* Set trigger to none. You need to enable the desired trigger with
925 * request_irq() or set_irq_type().
926 */
927 _set_gpio_triggering(bank, get_gpio_index(gpio), IRQT_NOEDGE);
928
929 #ifdef CONFIG_ARCH_OMAP15XX
930 if (bank->method == METHOD_GPIO_1510) {
931 void __iomem *reg;
932
933 /* Claim the pin for MPU */
934 reg = bank->base + OMAP1510_GPIO_PIN_CONTROL;
935 __raw_writel(__raw_readl(reg) | (1 << get_gpio_index(gpio)), reg);
936 }
937 #endif
938 spin_unlock_irqrestore(&bank->lock, flags);
939
940 return 0;
941 }
942
943 void omap_free_gpio(int gpio)
944 {
945 struct gpio_bank *bank;
946 unsigned long flags;
947
948 if (check_gpio(gpio) < 0)
949 return;
950 bank = get_gpio_bank(gpio);
951 spin_lock_irqsave(&bank->lock, flags);
952 if (unlikely(!gpiochip_is_requested(&bank->chip,
953 get_gpio_index(gpio)))) {
954 spin_unlock_irqrestore(&bank->lock, flags);
955 printk(KERN_ERR "omap-gpio: GPIO %d wasn't reserved!\n", gpio);
956 dump_stack();
957 return;
958 }
959 #ifdef CONFIG_ARCH_OMAP16XX
960 if (bank->method == METHOD_GPIO_1610) {
961 /* Disable wake-up during idle for dynamic tick */
962 void __iomem *reg = bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA;
963 __raw_writel(1 << get_gpio_index(gpio), reg);
964 }
965 #endif
966 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
967 if (bank->method == METHOD_GPIO_24XX) {
968 /* Disable wake-up during idle for dynamic tick */
969 void __iomem *reg = bank->base + OMAP24XX_GPIO_CLEARWKUENA;
970 __raw_writel(1 << get_gpio_index(gpio), reg);
971 }
972 #endif
973 _reset_gpio(bank, gpio);
974 spin_unlock_irqrestore(&bank->lock, flags);
975 gpio_free(gpio);
976 }
977
978 /*
979 * We need to unmask the GPIO bank interrupt as soon as possible to
980 * avoid missing GPIO interrupts for other lines in the bank.
981 * Then we need to mask-read-clear-unmask the triggered GPIO lines
982 * in the bank to avoid missing nested interrupts for a GPIO line.
983 * If we wait to unmask individual GPIO lines in the bank after the
984 * line's interrupt handler has been run, we may miss some nested
985 * interrupts.
986 */
987 static void gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
988 {
989 void __iomem *isr_reg = NULL;
990 u32 isr;
991 unsigned int gpio_irq;
992 struct gpio_bank *bank;
993 u32 retrigger = 0;
994 int unmasked = 0;
995
996 desc->chip->ack(irq);
997
998 bank = get_irq_data(irq);
999 #ifdef CONFIG_ARCH_OMAP1
1000 if (bank->method == METHOD_MPUIO)
1001 isr_reg = bank->base + OMAP_MPUIO_GPIO_INT;
1002 #endif
1003 #ifdef CONFIG_ARCH_OMAP15XX
1004 if (bank->method == METHOD_GPIO_1510)
1005 isr_reg = bank->base + OMAP1510_GPIO_INT_STATUS;
1006 #endif
1007 #if defined(CONFIG_ARCH_OMAP16XX)
1008 if (bank->method == METHOD_GPIO_1610)
1009 isr_reg = bank->base + OMAP1610_GPIO_IRQSTATUS1;
1010 #endif
1011 #ifdef CONFIG_ARCH_OMAP730
1012 if (bank->method == METHOD_GPIO_730)
1013 isr_reg = bank->base + OMAP730_GPIO_INT_STATUS;
1014 #endif
1015 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
1016 if (bank->method == METHOD_GPIO_24XX)
1017 isr_reg = bank->base + OMAP24XX_GPIO_IRQSTATUS1;
1018 #endif
1019 while(1) {
1020 u32 isr_saved, level_mask = 0;
1021 u32 enabled;
1022
1023 enabled = _get_gpio_irqbank_mask(bank);
1024 isr_saved = isr = __raw_readl(isr_reg) & enabled;
1025
1026 if (cpu_is_omap15xx() && (bank->method == METHOD_MPUIO))
1027 isr &= 0x0000ffff;
1028
1029 if (cpu_class_is_omap2()) {
1030 level_mask = bank->level_mask & enabled;
1031 }
1032
1033 /* clear edge sensitive interrupts before handler(s) are
1034 called so that we don't miss any interrupt occurred while
1035 executing them */
1036 _enable_gpio_irqbank(bank, isr_saved & ~level_mask, 0);
1037 _clear_gpio_irqbank(bank, isr_saved & ~level_mask);
1038 _enable_gpio_irqbank(bank, isr_saved & ~level_mask, 1);
1039
1040 /* if there is only edge sensitive GPIO pin interrupts
1041 configured, we could unmask GPIO bank interrupt immediately */
1042 if (!level_mask && !unmasked) {
1043 unmasked = 1;
1044 desc->chip->unmask(irq);
1045 }
1046
1047 isr |= retrigger;
1048 retrigger = 0;
1049 if (!isr)
1050 break;
1051
1052 gpio_irq = bank->virtual_irq_start;
1053 for (; isr != 0; isr >>= 1, gpio_irq++) {
1054 struct irq_desc *d;
1055
1056 if (!(isr & 1))
1057 continue;
1058 d = irq_desc + gpio_irq;
1059
1060 desc_handle_irq(gpio_irq, d);
1061 }
1062 }
1063 /* if bank has any level sensitive GPIO pin interrupt
1064 configured, we must unmask the bank interrupt only after
1065 handler(s) are executed in order to avoid spurious bank
1066 interrupt */
1067 if (!unmasked)
1068 desc->chip->unmask(irq);
1069
1070 }
1071
1072 static void gpio_irq_shutdown(unsigned int irq)
1073 {
1074 unsigned int gpio = irq - IH_GPIO_BASE;
1075 struct gpio_bank *bank = get_irq_chip_data(irq);
1076
1077 _reset_gpio(bank, gpio);
1078 }
1079
1080 static void gpio_ack_irq(unsigned int irq)
1081 {
1082 unsigned int gpio = irq - IH_GPIO_BASE;
1083 struct gpio_bank *bank = get_irq_chip_data(irq);
1084
1085 _clear_gpio_irqstatus(bank, gpio);
1086 }
1087
1088 static void gpio_mask_irq(unsigned int irq)
1089 {
1090 unsigned int gpio = irq - IH_GPIO_BASE;
1091 struct gpio_bank *bank = get_irq_chip_data(irq);
1092
1093 _set_gpio_irqenable(bank, gpio, 0);
1094 }
1095
1096 static void gpio_unmask_irq(unsigned int irq)
1097 {
1098 unsigned int gpio = irq - IH_GPIO_BASE;
1099 struct gpio_bank *bank = get_irq_chip_data(irq);
1100 unsigned int irq_mask = 1 << get_gpio_index(gpio);
1101
1102 /* For level-triggered GPIOs, the clearing must be done after
1103 * the HW source is cleared, thus after the handler has run */
1104 if (bank->level_mask & irq_mask) {
1105 _set_gpio_irqenable(bank, gpio, 0);
1106 _clear_gpio_irqstatus(bank, gpio);
1107 }
1108
1109 _set_gpio_irqenable(bank, gpio, 1);
1110 }
1111
1112 static struct irq_chip gpio_irq_chip = {
1113 .name = "GPIO",
1114 .shutdown = gpio_irq_shutdown,
1115 .ack = gpio_ack_irq,
1116 .mask = gpio_mask_irq,
1117 .unmask = gpio_unmask_irq,
1118 .set_type = gpio_irq_type,
1119 .set_wake = gpio_wake_enable,
1120 };
1121
1122 /*---------------------------------------------------------------------*/
1123
1124 #ifdef CONFIG_ARCH_OMAP1
1125
1126 /* MPUIO uses the always-on 32k clock */
1127
1128 static void mpuio_ack_irq(unsigned int irq)
1129 {
1130 /* The ISR is reset automatically, so do nothing here. */
1131 }
1132
1133 static void mpuio_mask_irq(unsigned int irq)
1134 {
1135 unsigned int gpio = OMAP_MPUIO(irq - IH_MPUIO_BASE);
1136 struct gpio_bank *bank = get_irq_chip_data(irq);
1137
1138 _set_gpio_irqenable(bank, gpio, 0);
1139 }
1140
1141 static void mpuio_unmask_irq(unsigned int irq)
1142 {
1143 unsigned int gpio = OMAP_MPUIO(irq - IH_MPUIO_BASE);
1144 struct gpio_bank *bank = get_irq_chip_data(irq);
1145
1146 _set_gpio_irqenable(bank, gpio, 1);
1147 }
1148
1149 static struct irq_chip mpuio_irq_chip = {
1150 .name = "MPUIO",
1151 .ack = mpuio_ack_irq,
1152 .mask = mpuio_mask_irq,
1153 .unmask = mpuio_unmask_irq,
1154 .set_type = gpio_irq_type,
1155 #ifdef CONFIG_ARCH_OMAP16XX
1156 /* REVISIT: assuming only 16xx supports MPUIO wake events */
1157 .set_wake = gpio_wake_enable,
1158 #endif
1159 };
1160
1161
1162 #define bank_is_mpuio(bank) ((bank)->method == METHOD_MPUIO)
1163
1164
1165 #ifdef CONFIG_ARCH_OMAP16XX
1166
1167 #include <linux/platform_device.h>
1168
1169 static int omap_mpuio_suspend_late(struct platform_device *pdev, pm_message_t mesg)
1170 {
1171 struct gpio_bank *bank = platform_get_drvdata(pdev);
1172 void __iomem *mask_reg = bank->base + OMAP_MPUIO_GPIO_MASKIT;
1173 unsigned long flags;
1174
1175 spin_lock_irqsave(&bank->lock, flags);
1176 bank->saved_wakeup = __raw_readl(mask_reg);
1177 __raw_writel(0xffff & ~bank->suspend_wakeup, mask_reg);
1178 spin_unlock_irqrestore(&bank->lock, flags);
1179
1180 return 0;
1181 }
1182
1183 static int omap_mpuio_resume_early(struct platform_device *pdev)
1184 {
1185 struct gpio_bank *bank = platform_get_drvdata(pdev);
1186 void __iomem *mask_reg = bank->base + OMAP_MPUIO_GPIO_MASKIT;
1187 unsigned long flags;
1188
1189 spin_lock_irqsave(&bank->lock, flags);
1190 __raw_writel(bank->saved_wakeup, mask_reg);
1191 spin_unlock_irqrestore(&bank->lock, flags);
1192
1193 return 0;
1194 }
1195
1196 /* use platform_driver for this, now that there's no longer any
1197 * point to sys_device (other than not disturbing old code).
1198 */
1199 static struct platform_driver omap_mpuio_driver = {
1200 .suspend_late = omap_mpuio_suspend_late,
1201 .resume_early = omap_mpuio_resume_early,
1202 .driver = {
1203 .name = "mpuio",
1204 },
1205 };
1206
1207 static struct platform_device omap_mpuio_device = {
1208 .name = "mpuio",
1209 .id = -1,
1210 .dev = {
1211 .driver = &omap_mpuio_driver.driver,
1212 }
1213 /* could list the /proc/iomem resources */
1214 };
1215
1216 static inline void mpuio_init(void)
1217 {
1218 platform_set_drvdata(&omap_mpuio_device, &gpio_bank_1610[0]);
1219
1220 if (platform_driver_register(&omap_mpuio_driver) == 0)
1221 (void) platform_device_register(&omap_mpuio_device);
1222 }
1223
1224 #else
1225 static inline void mpuio_init(void) {}
1226 #endif /* 16xx */
1227
1228 #else
1229
1230 extern struct irq_chip mpuio_irq_chip;
1231
1232 #define bank_is_mpuio(bank) 0
1233 static inline void mpuio_init(void) {}
1234
1235 #endif
1236
1237 /*---------------------------------------------------------------------*/
1238
1239 /* REVISIT these are stupid implementations! replace by ones that
1240 * don't switch on METHOD_* and which mostly avoid spinlocks
1241 */
1242
1243 static int gpio_input(struct gpio_chip *chip, unsigned offset)
1244 {
1245 struct gpio_bank *bank;
1246 unsigned long flags;
1247
1248 bank = container_of(chip, struct gpio_bank, chip);
1249 spin_lock_irqsave(&bank->lock, flags);
1250 _set_gpio_direction(bank, offset, 1);
1251 spin_unlock_irqrestore(&bank->lock, flags);
1252 return 0;
1253 }
1254
1255 static int gpio_get(struct gpio_chip *chip, unsigned offset)
1256 {
1257 return omap_get_gpio_datain(chip->base + offset);
1258 }
1259
1260 static int gpio_output(struct gpio_chip *chip, unsigned offset, int value)
1261 {
1262 struct gpio_bank *bank;
1263 unsigned long flags;
1264
1265 bank = container_of(chip, struct gpio_bank, chip);
1266 spin_lock_irqsave(&bank->lock, flags);
1267 _set_gpio_dataout(bank, offset, value);
1268 _set_gpio_direction(bank, offset, 0);
1269 spin_unlock_irqrestore(&bank->lock, flags);
1270 return 0;
1271 }
1272
1273 static void gpio_set(struct gpio_chip *chip, unsigned offset, int value)
1274 {
1275 struct gpio_bank *bank;
1276 unsigned long flags;
1277
1278 bank = container_of(chip, struct gpio_bank, chip);
1279 spin_lock_irqsave(&bank->lock, flags);
1280 _set_gpio_dataout(bank, offset, value);
1281 spin_unlock_irqrestore(&bank->lock, flags);
1282 }
1283
1284 /*---------------------------------------------------------------------*/
1285
1286 static int initialized;
1287 #if !defined(CONFIG_ARCH_OMAP3)
1288 static struct clk * gpio_ick;
1289 #endif
1290
1291 #if defined(CONFIG_ARCH_OMAP2)
1292 static struct clk * gpio_fck;
1293 #endif
1294
1295 #if defined(CONFIG_ARCH_OMAP2430)
1296 static struct clk * gpio5_ick;
1297 static struct clk * gpio5_fck;
1298 #endif
1299
1300 #if defined(CONFIG_ARCH_OMAP3)
1301 static struct clk *gpio_fclks[OMAP34XX_NR_GPIOS];
1302 static struct clk *gpio_iclks[OMAP34XX_NR_GPIOS];
1303 #endif
1304
1305 /* This lock class tells lockdep that GPIO irqs are in a different
1306 * category than their parents, so it won't report false recursion.
1307 */
1308 static struct lock_class_key gpio_lock_class;
1309
1310 static int __init _omap_gpio_init(void)
1311 {
1312 int i;
1313 int gpio = 0;
1314 struct gpio_bank *bank;
1315 #if defined(CONFIG_ARCH_OMAP3)
1316 char clk_name[11];
1317 #endif
1318
1319 initialized = 1;
1320
1321 #if defined(CONFIG_ARCH_OMAP1)
1322 if (cpu_is_omap15xx()) {
1323 gpio_ick = clk_get(NULL, "arm_gpio_ck");
1324 if (IS_ERR(gpio_ick))
1325 printk("Could not get arm_gpio_ck\n");
1326 else
1327 clk_enable(gpio_ick);
1328 }
1329 #endif
1330 #if defined(CONFIG_ARCH_OMAP2)
1331 if (cpu_class_is_omap2()) {
1332 gpio_ick = clk_get(NULL, "gpios_ick");
1333 if (IS_ERR(gpio_ick))
1334 printk("Could not get gpios_ick\n");
1335 else
1336 clk_enable(gpio_ick);
1337 gpio_fck = clk_get(NULL, "gpios_fck");
1338 if (IS_ERR(gpio_fck))
1339 printk("Could not get gpios_fck\n");
1340 else
1341 clk_enable(gpio_fck);
1342
1343 /*
1344 * On 2430 & 3430 GPIO 5 uses CORE L4 ICLK
1345 */
1346 #if defined(CONFIG_ARCH_OMAP2430)
1347 if (cpu_is_omap2430()) {
1348 gpio5_ick = clk_get(NULL, "gpio5_ick");
1349 if (IS_ERR(gpio5_ick))
1350 printk("Could not get gpio5_ick\n");
1351 else
1352 clk_enable(gpio5_ick);
1353 gpio5_fck = clk_get(NULL, "gpio5_fck");
1354 if (IS_ERR(gpio5_fck))
1355 printk("Could not get gpio5_fck\n");
1356 else
1357 clk_enable(gpio5_fck);
1358 }
1359 #endif
1360 }
1361 #endif
1362
1363 #if defined(CONFIG_ARCH_OMAP3)
1364 if (cpu_is_omap34xx()) {
1365 for (i = 0; i < OMAP34XX_NR_GPIOS; i++) {
1366 sprintf(clk_name, "gpio%d_ick", i + 1);
1367 gpio_iclks[i] = clk_get(NULL, clk_name);
1368 if (IS_ERR(gpio_iclks[i]))
1369 printk(KERN_ERR "Could not get %s\n", clk_name);
1370 else
1371 clk_enable(gpio_iclks[i]);
1372 sprintf(clk_name, "gpio%d_fck", i + 1);
1373 gpio_fclks[i] = clk_get(NULL, clk_name);
1374 if (IS_ERR(gpio_fclks[i]))
1375 printk(KERN_ERR "Could not get %s\n", clk_name);
1376 else
1377 clk_enable(gpio_fclks[i]);
1378 }
1379 }
1380 #endif
1381
1382
1383 #ifdef CONFIG_ARCH_OMAP15XX
1384 if (cpu_is_omap15xx()) {
1385 printk(KERN_INFO "OMAP1510 GPIO hardware\n");
1386 gpio_bank_count = 2;
1387 gpio_bank = gpio_bank_1510;
1388 }
1389 #endif
1390 #if defined(CONFIG_ARCH_OMAP16XX)
1391 if (cpu_is_omap16xx()) {
1392 u32 rev;
1393
1394 gpio_bank_count = 5;
1395 gpio_bank = gpio_bank_1610;
1396 rev = omap_readw(gpio_bank[1].base + OMAP1610_GPIO_REVISION);
1397 printk(KERN_INFO "OMAP GPIO hardware version %d.%d\n",
1398 (rev >> 4) & 0x0f, rev & 0x0f);
1399 }
1400 #endif
1401 #ifdef CONFIG_ARCH_OMAP730
1402 if (cpu_is_omap730()) {
1403 printk(KERN_INFO "OMAP730 GPIO hardware\n");
1404 gpio_bank_count = 7;
1405 gpio_bank = gpio_bank_730;
1406 }
1407 #endif
1408
1409 #ifdef CONFIG_ARCH_OMAP24XX
1410 if (cpu_is_omap242x()) {
1411 int rev;
1412
1413 gpio_bank_count = 4;
1414 gpio_bank = gpio_bank_242x;
1415 rev = omap_readl(gpio_bank[0].base + OMAP24XX_GPIO_REVISION);
1416 printk(KERN_INFO "OMAP242x GPIO hardware version %d.%d\n",
1417 (rev >> 4) & 0x0f, rev & 0x0f);
1418 }
1419 if (cpu_is_omap243x()) {
1420 int rev;
1421
1422 gpio_bank_count = 5;
1423 gpio_bank = gpio_bank_243x;
1424 rev = omap_readl(gpio_bank[0].base + OMAP24XX_GPIO_REVISION);
1425 printk(KERN_INFO "OMAP243x GPIO hardware version %d.%d\n",
1426 (rev >> 4) & 0x0f, rev & 0x0f);
1427 }
1428 #endif
1429 #ifdef CONFIG_ARCH_OMAP34XX
1430 if (cpu_is_omap34xx()) {
1431 int rev;
1432
1433 gpio_bank_count = OMAP34XX_NR_GPIOS;
1434 gpio_bank = gpio_bank_34xx;
1435 rev = omap_readl(gpio_bank[0].base + OMAP24XX_GPIO_REVISION);
1436 printk(KERN_INFO "OMAP34xx GPIO hardware version %d.%d\n",
1437 (rev >> 4) & 0x0f, rev & 0x0f);
1438 }
1439 #endif
1440 for (i = 0; i < gpio_bank_count; i++) {
1441 int j, gpio_count = 16;
1442
1443 bank = &gpio_bank[i];
1444 bank->base = IO_ADDRESS(bank->base);
1445 spin_lock_init(&bank->lock);
1446 if (bank_is_mpuio(bank))
1447 omap_writew(0xFFFF, OMAP_MPUIO_BASE + OMAP_MPUIO_GPIO_MASKIT);
1448 if (cpu_is_omap15xx() && bank->method == METHOD_GPIO_1510) {
1449 __raw_writew(0xffff, bank->base + OMAP1510_GPIO_INT_MASK);
1450 __raw_writew(0x0000, bank->base + OMAP1510_GPIO_INT_STATUS);
1451 }
1452 if (cpu_is_omap16xx() && bank->method == METHOD_GPIO_1610) {
1453 __raw_writew(0x0000, bank->base + OMAP1610_GPIO_IRQENABLE1);
1454 __raw_writew(0xffff, bank->base + OMAP1610_GPIO_IRQSTATUS1);
1455 __raw_writew(0x0014, bank->base + OMAP1610_GPIO_SYSCONFIG);
1456 }
1457 if (cpu_is_omap730() && bank->method == METHOD_GPIO_730) {
1458 __raw_writel(0xffffffff, bank->base + OMAP730_GPIO_INT_MASK);
1459 __raw_writel(0x00000000, bank->base + OMAP730_GPIO_INT_STATUS);
1460
1461 gpio_count = 32; /* 730 has 32-bit GPIOs */
1462 }
1463
1464 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
1465 if (bank->method == METHOD_GPIO_24XX) {
1466 static const u32 non_wakeup_gpios[] = {
1467 0xe203ffc0, 0x08700040
1468 };
1469
1470 __raw_writel(0x00000000, bank->base + OMAP24XX_GPIO_IRQENABLE1);
1471 __raw_writel(0xffffffff, bank->base + OMAP24XX_GPIO_IRQSTATUS1);
1472 __raw_writew(0x0015, bank->base + OMAP24XX_GPIO_SYSCONFIG);
1473
1474 /* Initialize interface clock ungated, module enabled */
1475 __raw_writel(0, bank->base + OMAP24XX_GPIO_CTRL);
1476 if (i < ARRAY_SIZE(non_wakeup_gpios))
1477 bank->non_wakeup_gpios = non_wakeup_gpios[i];
1478 gpio_count = 32;
1479 }
1480 #endif
1481
1482 /* REVISIT eventually switch from OMAP-specific gpio structs
1483 * over to the generic ones
1484 */
1485 bank->chip.direction_input = gpio_input;
1486 bank->chip.get = gpio_get;
1487 bank->chip.direction_output = gpio_output;
1488 bank->chip.set = gpio_set;
1489 if (bank_is_mpuio(bank)) {
1490 bank->chip.label = "mpuio";
1491 bank->chip.base = OMAP_MPUIO(0);
1492 } else {
1493 bank->chip.label = "gpio";
1494 bank->chip.base = gpio;
1495 gpio += gpio_count;
1496 }
1497 bank->chip.ngpio = gpio_count;
1498
1499 gpiochip_add(&bank->chip);
1500
1501 for (j = bank->virtual_irq_start;
1502 j < bank->virtual_irq_start + gpio_count; j++) {
1503 lockdep_set_class(&irq_desc[j].lock, &gpio_lock_class);
1504 set_irq_chip_data(j, bank);
1505 if (bank_is_mpuio(bank))
1506 set_irq_chip(j, &mpuio_irq_chip);
1507 else
1508 set_irq_chip(j, &gpio_irq_chip);
1509 set_irq_handler(j, handle_simple_irq);
1510 set_irq_flags(j, IRQF_VALID);
1511 }
1512 set_irq_chained_handler(bank->irq, gpio_irq_handler);
1513 set_irq_data(bank->irq, bank);
1514 }
1515
1516 /* Enable system clock for GPIO module.
1517 * The CAM_CLK_CTRL *is* really the right place. */
1518 if (cpu_is_omap16xx())
1519 omap_writel(omap_readl(ULPD_CAM_CLK_CTRL) | 0x04, ULPD_CAM_CLK_CTRL);
1520
1521 /* Enable autoidle for the OCP interface */
1522 if (cpu_is_omap24xx())
1523 omap_writel(1 << 0, 0x48019010);
1524 if (cpu_is_omap34xx())
1525 omap_writel(1 << 0, 0x48306814);
1526
1527 return 0;
1528 }
1529
1530 #if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
1531 static int omap_gpio_suspend(struct sys_device *dev, pm_message_t mesg)
1532 {
1533 int i;
1534
1535 if (!cpu_class_is_omap2() && !cpu_is_omap16xx())
1536 return 0;
1537
1538 for (i = 0; i < gpio_bank_count; i++) {
1539 struct gpio_bank *bank = &gpio_bank[i];
1540 void __iomem *wake_status;
1541 void __iomem *wake_clear;
1542 void __iomem *wake_set;
1543 unsigned long flags;
1544
1545 switch (bank->method) {
1546 #ifdef CONFIG_ARCH_OMAP16XX
1547 case METHOD_GPIO_1610:
1548 wake_status = bank->base + OMAP1610_GPIO_WAKEUPENABLE;
1549 wake_clear = bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA;
1550 wake_set = bank->base + OMAP1610_GPIO_SET_WAKEUPENA;
1551 break;
1552 #endif
1553 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
1554 case METHOD_GPIO_24XX:
1555 wake_status = bank->base + OMAP24XX_GPIO_SETWKUENA;
1556 wake_clear = bank->base + OMAP24XX_GPIO_CLEARWKUENA;
1557 wake_set = bank->base + OMAP24XX_GPIO_SETWKUENA;
1558 break;
1559 #endif
1560 default:
1561 continue;
1562 }
1563
1564 spin_lock_irqsave(&bank->lock, flags);
1565 bank->saved_wakeup = __raw_readl(wake_status);
1566 __raw_writel(0xffffffff, wake_clear);
1567 __raw_writel(bank->suspend_wakeup, wake_set);
1568 spin_unlock_irqrestore(&bank->lock, flags);
1569 }
1570
1571 return 0;
1572 }
1573
1574 static int omap_gpio_resume(struct sys_device *dev)
1575 {
1576 int i;
1577
1578 if (!cpu_is_omap24xx() && !cpu_is_omap16xx())
1579 return 0;
1580
1581 for (i = 0; i < gpio_bank_count; i++) {
1582 struct gpio_bank *bank = &gpio_bank[i];
1583 void __iomem *wake_clear;
1584 void __iomem *wake_set;
1585 unsigned long flags;
1586
1587 switch (bank->method) {
1588 #ifdef CONFIG_ARCH_OMAP16XX
1589 case METHOD_GPIO_1610:
1590 wake_clear = bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA;
1591 wake_set = bank->base + OMAP1610_GPIO_SET_WAKEUPENA;
1592 break;
1593 #endif
1594 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
1595 case METHOD_GPIO_24XX:
1596 wake_clear = bank->base + OMAP24XX_GPIO_CLEARWKUENA;
1597 wake_set = bank->base + OMAP24XX_GPIO_SETWKUENA;
1598 break;
1599 #endif
1600 default:
1601 continue;
1602 }
1603
1604 spin_lock_irqsave(&bank->lock, flags);
1605 __raw_writel(0xffffffff, wake_clear);
1606 __raw_writel(bank->saved_wakeup, wake_set);
1607 spin_unlock_irqrestore(&bank->lock, flags);
1608 }
1609
1610 return 0;
1611 }
1612
1613 static struct sysdev_class omap_gpio_sysclass = {
1614 .name = "gpio",
1615 .suspend = omap_gpio_suspend,
1616 .resume = omap_gpio_resume,
1617 };
1618
1619 static struct sys_device omap_gpio_device = {
1620 .id = 0,
1621 .cls = &omap_gpio_sysclass,
1622 };
1623
1624 #endif
1625
1626 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
1627
1628 static int workaround_enabled;
1629
1630 void omap2_gpio_prepare_for_retention(void)
1631 {
1632 int i, c = 0;
1633
1634 /* Remove triggering for all non-wakeup GPIOs. Otherwise spurious
1635 * IRQs will be generated. See OMAP2420 Errata item 1.101. */
1636 for (i = 0; i < gpio_bank_count; i++) {
1637 struct gpio_bank *bank = &gpio_bank[i];
1638 u32 l1, l2;
1639
1640 if (!(bank->enabled_non_wakeup_gpios))
1641 continue;
1642 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
1643 bank->saved_datain = __raw_readl(bank->base + OMAP24XX_GPIO_DATAIN);
1644 l1 = __raw_readl(bank->base + OMAP24XX_GPIO_FALLINGDETECT);
1645 l2 = __raw_readl(bank->base + OMAP24XX_GPIO_RISINGDETECT);
1646 #endif
1647 bank->saved_fallingdetect = l1;
1648 bank->saved_risingdetect = l2;
1649 l1 &= ~bank->enabled_non_wakeup_gpios;
1650 l2 &= ~bank->enabled_non_wakeup_gpios;
1651 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
1652 __raw_writel(l1, bank->base + OMAP24XX_GPIO_FALLINGDETECT);
1653 __raw_writel(l2, bank->base + OMAP24XX_GPIO_RISINGDETECT);
1654 #endif
1655 c++;
1656 }
1657 if (!c) {
1658 workaround_enabled = 0;
1659 return;
1660 }
1661 workaround_enabled = 1;
1662 }
1663
1664 void omap2_gpio_resume_after_retention(void)
1665 {
1666 int i;
1667
1668 if (!workaround_enabled)
1669 return;
1670 for (i = 0; i < gpio_bank_count; i++) {
1671 struct gpio_bank *bank = &gpio_bank[i];
1672 u32 l;
1673
1674 if (!(bank->enabled_non_wakeup_gpios))
1675 continue;
1676 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
1677 __raw_writel(bank->saved_fallingdetect,
1678 bank->base + OMAP24XX_GPIO_FALLINGDETECT);
1679 __raw_writel(bank->saved_risingdetect,
1680 bank->base + OMAP24XX_GPIO_RISINGDETECT);
1681 #endif
1682 /* Check if any of the non-wakeup interrupt GPIOs have changed
1683 * state. If so, generate an IRQ by software. This is
1684 * horribly racy, but it's the best we can do to work around
1685 * this silicon bug. */
1686 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
1687 l = __raw_readl(bank->base + OMAP24XX_GPIO_DATAIN);
1688 #endif
1689 l ^= bank->saved_datain;
1690 l &= bank->non_wakeup_gpios;
1691 if (l) {
1692 u32 old0, old1;
1693 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
1694 old0 = __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT0);
1695 old1 = __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT1);
1696 __raw_writel(old0 | l, bank->base + OMAP24XX_GPIO_LEVELDETECT0);
1697 __raw_writel(old1 | l, bank->base + OMAP24XX_GPIO_LEVELDETECT1);
1698 __raw_writel(old0, bank->base + OMAP24XX_GPIO_LEVELDETECT0);
1699 __raw_writel(old1, bank->base + OMAP24XX_GPIO_LEVELDETECT1);
1700 #endif
1701 }
1702 }
1703
1704 }
1705
1706 #endif
1707
1708 /*
1709 * This may get called early from board specific init
1710 * for boards that have interrupts routed via FPGA.
1711 */
1712 int __init omap_gpio_init(void)
1713 {
1714 if (!initialized)
1715 return _omap_gpio_init();
1716 else
1717 return 0;
1718 }
1719
1720 static int __init omap_gpio_sysinit(void)
1721 {
1722 int ret = 0;
1723
1724 if (!initialized)
1725 ret = _omap_gpio_init();
1726
1727 mpuio_init();
1728
1729 #if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
1730 if (cpu_is_omap16xx() || cpu_class_is_omap2()) {
1731 if (ret == 0) {
1732 ret = sysdev_class_register(&omap_gpio_sysclass);
1733 if (ret == 0)
1734 ret = sysdev_register(&omap_gpio_device);
1735 }
1736 }
1737 #endif
1738
1739 return ret;
1740 }
1741
1742 EXPORT_SYMBOL(omap_request_gpio);
1743 EXPORT_SYMBOL(omap_free_gpio);
1744 EXPORT_SYMBOL(omap_set_gpio_direction);
1745 EXPORT_SYMBOL(omap_set_gpio_dataout);
1746 EXPORT_SYMBOL(omap_get_gpio_datain);
1747
1748 arch_initcall(omap_gpio_sysinit);
1749
1750
1751 #ifdef CONFIG_DEBUG_FS
1752
1753 #include <linux/debugfs.h>
1754 #include <linux/seq_file.h>
1755
1756 static int gpio_is_input(struct gpio_bank *bank, int mask)
1757 {
1758 void __iomem *reg = bank->base;
1759
1760 switch (bank->method) {
1761 case METHOD_MPUIO:
1762 reg += OMAP_MPUIO_IO_CNTL;
1763 break;
1764 case METHOD_GPIO_1510:
1765 reg += OMAP1510_GPIO_DIR_CONTROL;
1766 break;
1767 case METHOD_GPIO_1610:
1768 reg += OMAP1610_GPIO_DIRECTION;
1769 break;
1770 case METHOD_GPIO_730:
1771 reg += OMAP730_GPIO_DIR_CONTROL;
1772 break;
1773 case METHOD_GPIO_24XX:
1774 reg += OMAP24XX_GPIO_OE;
1775 break;
1776 }
1777 return __raw_readl(reg) & mask;
1778 }
1779
1780
1781 static int dbg_gpio_show(struct seq_file *s, void *unused)
1782 {
1783 unsigned i, j, gpio;
1784
1785 for (i = 0, gpio = 0; i < gpio_bank_count; i++) {
1786 struct gpio_bank *bank = gpio_bank + i;
1787 unsigned bankwidth = 16;
1788 u32 mask = 1;
1789
1790 if (bank_is_mpuio(bank))
1791 gpio = OMAP_MPUIO(0);
1792 else if (cpu_class_is_omap2() || cpu_is_omap730())
1793 bankwidth = 32;
1794
1795 for (j = 0; j < bankwidth; j++, gpio++, mask <<= 1) {
1796 unsigned irq, value, is_in, irqstat;
1797 const char *label;
1798
1799 label = gpiochip_is_requested(&bank->chip, j);
1800 if (!label)
1801 continue;
1802
1803 irq = bank->virtual_irq_start + j;
1804 value = omap_get_gpio_datain(gpio);
1805 is_in = gpio_is_input(bank, mask);
1806
1807 if (bank_is_mpuio(bank))
1808 seq_printf(s, "MPUIO %2d ", j);
1809 else
1810 seq_printf(s, "GPIO %3d ", gpio);
1811 seq_printf(s, "(%10s): %s %s",
1812 label,
1813 is_in ? "in " : "out",
1814 value ? "hi" : "lo");
1815
1816 /* FIXME for at least omap2, show pullup/pulldown state */
1817
1818 irqstat = irq_desc[irq].status;
1819 if (is_in && ((bank->suspend_wakeup & mask)
1820 || irqstat & IRQ_TYPE_SENSE_MASK)) {
1821 char *trigger = NULL;
1822
1823 switch (irqstat & IRQ_TYPE_SENSE_MASK) {
1824 case IRQ_TYPE_EDGE_FALLING:
1825 trigger = "falling";
1826 break;
1827 case IRQ_TYPE_EDGE_RISING:
1828 trigger = "rising";
1829 break;
1830 case IRQ_TYPE_EDGE_BOTH:
1831 trigger = "bothedge";
1832 break;
1833 case IRQ_TYPE_LEVEL_LOW:
1834 trigger = "low";
1835 break;
1836 case IRQ_TYPE_LEVEL_HIGH:
1837 trigger = "high";
1838 break;
1839 case IRQ_TYPE_NONE:
1840 trigger = "(?)";
1841 break;
1842 }
1843 seq_printf(s, ", irq-%d %-8s%s",
1844 irq, trigger,
1845 (bank->suspend_wakeup & mask)
1846 ? " wakeup" : "");
1847 }
1848 seq_printf(s, "\n");
1849 }
1850
1851 if (bank_is_mpuio(bank)) {
1852 seq_printf(s, "\n");
1853 gpio = 0;
1854 }
1855 }
1856 return 0;
1857 }
1858
1859 static int dbg_gpio_open(struct inode *inode, struct file *file)
1860 {
1861 return single_open(file, dbg_gpio_show, &inode->i_private);
1862 }
1863
1864 static const struct file_operations debug_fops = {
1865 .open = dbg_gpio_open,
1866 .read = seq_read,
1867 .llseek = seq_lseek,
1868 .release = single_release,
1869 };
1870
1871 static int __init omap_gpio_debuginit(void)
1872 {
1873 (void) debugfs_create_file("omap_gpio", S_IRUGO,
1874 NULL, NULL, &debug_fops);
1875 return 0;
1876 }
1877 late_initcall(omap_gpio_debuginit);
1878 #endif
Mirror for ia64_pv_ops.git