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ia64/kvm: compilation fix. export account_system_vtime.
[pv_ops_mirror.git] / arch / mips / au1000 / common / dbdma.c
blob42d555236de15bbd4bc731554fb54a8ab305d6d1
1 /*
2 *
3 * BRIEF MODULE DESCRIPTION
4 * The Descriptor Based DMA channel manager that first appeared
5 * on the Au1550. I started with dma.c, but I think all that is
6 * left is this initial comment :-)
7 *
8 * Copyright 2004 Embedded Edge, LLC
9 * dan@embeddededge.com
10 *
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License as published by the
13 * Free Software Foundation; either version 2 of the License, or (at your
14 * option) any later version.
15 *
16 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
17 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
18 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
19 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
21 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
22 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
23 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
24 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
25 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26 *
27 * You should have received a copy of the GNU General Public License along
28 * with this program; if not, write to the Free Software Foundation, Inc.,
29 * 675 Mass Ave, Cambridge, MA 02139, USA.
30 *
31 */
32
33 #include <linux/kernel.h>
34 #include <linux/slab.h>
35 #include <linux/spinlock.h>
36 #include <linux/interrupt.h>
37 #include <linux/module.h>
38 #include <asm/mach-au1x00/au1000.h>
39 #include <asm/mach-au1x00/au1xxx_dbdma.h>
40
41 #if defined(CONFIG_SOC_AU1550) || defined(CONFIG_SOC_AU1200)
42
43 /*
44 * The Descriptor Based DMA supports up to 16 channels.
45 *
46 * There are 32 devices defined. We keep an internal structure
47 * of devices using these channels, along with additional
48 * information.
49 *
50 * We allocate the descriptors and allow access to them through various
51 * functions. The drivers allocate the data buffers and assign them
52 * to the descriptors.
53 */
54 static DEFINE_SPINLOCK(au1xxx_dbdma_spin_lock);
55
56 /* I couldn't find a macro that did this... */
57 #define ALIGN_ADDR(x, a) ((((u32)(x)) + (a-1)) & ~(a-1))
58
59 static dbdma_global_t *dbdma_gptr = (dbdma_global_t *)DDMA_GLOBAL_BASE;
60 static int dbdma_initialized;
61 static void au1xxx_dbdma_init(void);
62
63 static dbdev_tab_t dbdev_tab[] = {
64 #ifdef CONFIG_SOC_AU1550
65 /* UARTS */
66 { DSCR_CMD0_UART0_TX, DEV_FLAGS_OUT, 0, 8, 0x11100004, 0, 0 },
67 { DSCR_CMD0_UART0_RX, DEV_FLAGS_IN, 0, 8, 0x11100000, 0, 0 },
68 { DSCR_CMD0_UART3_TX, DEV_FLAGS_OUT, 0, 8, 0x11400004, 0, 0 },
69 { DSCR_CMD0_UART3_RX, DEV_FLAGS_IN, 0, 8, 0x11400000, 0, 0 },
70
71 /* EXT DMA */
72 { DSCR_CMD0_DMA_REQ0, 0, 0, 0, 0x00000000, 0, 0 },
73 { DSCR_CMD0_DMA_REQ1, 0, 0, 0, 0x00000000, 0, 0 },
74 { DSCR_CMD0_DMA_REQ2, 0, 0, 0, 0x00000000, 0, 0 },
75 { DSCR_CMD0_DMA_REQ3, 0, 0, 0, 0x00000000, 0, 0 },
76
77 /* USB DEV */
78 { DSCR_CMD0_USBDEV_RX0, DEV_FLAGS_IN, 4, 8, 0x10200000, 0, 0 },
79 { DSCR_CMD0_USBDEV_TX0, DEV_FLAGS_OUT, 4, 8, 0x10200004, 0, 0 },
80 { DSCR_CMD0_USBDEV_TX1, DEV_FLAGS_OUT, 4, 8, 0x10200008, 0, 0 },
81 { DSCR_CMD0_USBDEV_TX2, DEV_FLAGS_OUT, 4, 8, 0x1020000c, 0, 0 },
82 { DSCR_CMD0_USBDEV_RX3, DEV_FLAGS_IN, 4, 8, 0x10200010, 0, 0 },
83 { DSCR_CMD0_USBDEV_RX4, DEV_FLAGS_IN, 4, 8, 0x10200014, 0, 0 },
84
85 /* PSC 0 */
86 { DSCR_CMD0_PSC0_TX, DEV_FLAGS_OUT, 0, 0, 0x11a0001c, 0, 0 },
87 { DSCR_CMD0_PSC0_RX, DEV_FLAGS_IN, 0, 0, 0x11a0001c, 0, 0 },
88
89 /* PSC 1 */
90 { DSCR_CMD0_PSC1_TX, DEV_FLAGS_OUT, 0, 0, 0x11b0001c, 0, 0 },
91 { DSCR_CMD0_PSC1_RX, DEV_FLAGS_IN, 0, 0, 0x11b0001c, 0, 0 },
92
93 /* PSC 2 */
94 { DSCR_CMD0_PSC2_TX, DEV_FLAGS_OUT, 0, 0, 0x10a0001c, 0, 0 },
95 { DSCR_CMD0_PSC2_RX, DEV_FLAGS_IN, 0, 0, 0x10a0001c, 0, 0 },
96
97 /* PSC 3 */
98 { DSCR_CMD0_PSC3_TX, DEV_FLAGS_OUT, 0, 0, 0x10b0001c, 0, 0 },
99 { DSCR_CMD0_PSC3_RX, DEV_FLAGS_IN, 0, 0, 0x10b0001c, 0, 0 },
100
101 { DSCR_CMD0_PCI_WRITE, 0, 0, 0, 0x00000000, 0, 0 }, /* PCI */
102 { DSCR_CMD0_NAND_FLASH, 0, 0, 0, 0x00000000, 0, 0 }, /* NAND */
103
104 /* MAC 0 */
105 { DSCR_CMD0_MAC0_RX, DEV_FLAGS_IN, 0, 0, 0x00000000, 0, 0 },
106 { DSCR_CMD0_MAC0_TX, DEV_FLAGS_OUT, 0, 0, 0x00000000, 0, 0 },
107
108 /* MAC 1 */
109 { DSCR_CMD0_MAC1_RX, DEV_FLAGS_IN, 0, 0, 0x00000000, 0, 0 },
110 { DSCR_CMD0_MAC1_TX, DEV_FLAGS_OUT, 0, 0, 0x00000000, 0, 0 },
111
112 #endif /* CONFIG_SOC_AU1550 */
113
114 #ifdef CONFIG_SOC_AU1200
115 { DSCR_CMD0_UART0_TX, DEV_FLAGS_OUT, 0, 8, 0x11100004, 0, 0 },
116 { DSCR_CMD0_UART0_RX, DEV_FLAGS_IN, 0, 8, 0x11100000, 0, 0 },
117 { DSCR_CMD0_UART1_TX, DEV_FLAGS_OUT, 0, 8, 0x11200004, 0, 0 },
118 { DSCR_CMD0_UART1_RX, DEV_FLAGS_IN, 0, 8, 0x11200000, 0, 0 },
119
120 { DSCR_CMD0_DMA_REQ0, 0, 0, 0, 0x00000000, 0, 0 },
121 { DSCR_CMD0_DMA_REQ1, 0, 0, 0, 0x00000000, 0, 0 },
122
123 { DSCR_CMD0_MAE_BE, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 },
124 { DSCR_CMD0_MAE_FE, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 },
125 { DSCR_CMD0_MAE_BOTH, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 },
126 { DSCR_CMD0_LCD, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 },
127
128 { DSCR_CMD0_SDMS_TX0, DEV_FLAGS_OUT, 4, 8, 0x10600000, 0, 0 },
129 { DSCR_CMD0_SDMS_RX0, DEV_FLAGS_IN, 4, 8, 0x10600004, 0, 0 },
130 { DSCR_CMD0_SDMS_TX1, DEV_FLAGS_OUT, 4, 8, 0x10680000, 0, 0 },
131 { DSCR_CMD0_SDMS_RX1, DEV_FLAGS_IN, 4, 8, 0x10680004, 0, 0 },
132
133 { DSCR_CMD0_AES_RX, DEV_FLAGS_IN , 4, 32, 0x10300008, 0, 0 },
134 { DSCR_CMD0_AES_TX, DEV_FLAGS_OUT, 4, 32, 0x10300004, 0, 0 },
135
136 { DSCR_CMD0_PSC0_TX, DEV_FLAGS_OUT, 0, 16, 0x11a0001c, 0, 0 },
137 { DSCR_CMD0_PSC0_RX, DEV_FLAGS_IN, 0, 16, 0x11a0001c, 0, 0 },
138 { DSCR_CMD0_PSC0_SYNC, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 },
139
140 { DSCR_CMD0_PSC1_TX, DEV_FLAGS_OUT, 0, 16, 0x11b0001c, 0, 0 },
141 { DSCR_CMD0_PSC1_RX, DEV_FLAGS_IN, 0, 16, 0x11b0001c, 0, 0 },
142 { DSCR_CMD0_PSC1_SYNC, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 },
143
144 { DSCR_CMD0_CIM_RXA, DEV_FLAGS_IN, 0, 32, 0x14004020, 0, 0 },
145 { DSCR_CMD0_CIM_RXB, DEV_FLAGS_IN, 0, 32, 0x14004040, 0, 0 },
146 { DSCR_CMD0_CIM_RXC, DEV_FLAGS_IN, 0, 32, 0x14004060, 0, 0 },
147 { DSCR_CMD0_CIM_SYNC, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 },
148
149 { DSCR_CMD0_NAND_FLASH, DEV_FLAGS_IN, 0, 0, 0x00000000, 0, 0 },
150
151 #endif /* CONFIG_SOC_AU1200 */
152
153 { DSCR_CMD0_THROTTLE, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 },
154 { DSCR_CMD0_ALWAYS, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 },
155
156 /* Provide 16 user definable device types */
157 { ~0, 0, 0, 0, 0, 0, 0 },
158 { ~0, 0, 0, 0, 0, 0, 0 },
159 { ~0, 0, 0, 0, 0, 0, 0 },
160 { ~0, 0, 0, 0, 0, 0, 0 },
161 { ~0, 0, 0, 0, 0, 0, 0 },
162 { ~0, 0, 0, 0, 0, 0, 0 },
163 { ~0, 0, 0, 0, 0, 0, 0 },
164 { ~0, 0, 0, 0, 0, 0, 0 },
165 { ~0, 0, 0, 0, 0, 0, 0 },
166 { ~0, 0, 0, 0, 0, 0, 0 },
167 { ~0, 0, 0, 0, 0, 0, 0 },
168 { ~0, 0, 0, 0, 0, 0, 0 },
169 { ~0, 0, 0, 0, 0, 0, 0 },
170 { ~0, 0, 0, 0, 0, 0, 0 },
171 { ~0, 0, 0, 0, 0, 0, 0 },
172 { ~0, 0, 0, 0, 0, 0, 0 },
173 };
174
175 #define DBDEV_TAB_SIZE ARRAY_SIZE(dbdev_tab)
176
177 static chan_tab_t *chan_tab_ptr[NUM_DBDMA_CHANS];
178
179 static dbdev_tab_t *find_dbdev_id(u32 id)
180 {
181 int i;
182 dbdev_tab_t *p;
183 for (i = 0; i < DBDEV_TAB_SIZE; ++i) {
184 p = &dbdev_tab[i];
185 if (p->dev_id == id)
186 return p;
187 }
188 return NULL;
189 }
190
191 void *au1xxx_ddma_get_nextptr_virt(au1x_ddma_desc_t *dp)
192 {
193 return phys_to_virt(DSCR_GET_NXTPTR(dp->dscr_nxtptr));
194 }
195 EXPORT_SYMBOL(au1xxx_ddma_get_nextptr_virt);
196
197 u32 au1xxx_ddma_add_device(dbdev_tab_t *dev)
198 {
199 u32 ret = 0;
200 dbdev_tab_t *p;
201 static u16 new_id = 0x1000;
202
203 p = find_dbdev_id(~0);
204 if (NULL != p) {
205 memcpy(p, dev, sizeof(dbdev_tab_t));
206 p->dev_id = DSCR_DEV2CUSTOM_ID(new_id, dev->dev_id);
207 ret = p->dev_id;
208 new_id++;
209 #if 0
210 printk(KERN_DEBUG "add_device: id:%x flags:%x padd:%x\n",
211 p->dev_id, p->dev_flags, p->dev_physaddr);
212 #endif
213 }
214
215 return ret;
216 }
217 EXPORT_SYMBOL(au1xxx_ddma_add_device);
218
219 /* Allocate a channel and return a non-zero descriptor if successful. */
220 u32 au1xxx_dbdma_chan_alloc(u32 srcid, u32 destid,
221 void (*callback)(int, void *), void *callparam)
222 {
223 unsigned long flags;
224 u32 used, chan, rv;
225 u32 dcp;
226 int i;
227 dbdev_tab_t *stp, *dtp;
228 chan_tab_t *ctp;
229 au1x_dma_chan_t *cp;
230
231 /*
232 * We do the intialization on the first channel allocation.
233 * We have to wait because of the interrupt handler initialization
234 * which can't be done successfully during board set up.
235 */
236 if (!dbdma_initialized)
237 au1xxx_dbdma_init();
238 dbdma_initialized = 1;
239
240 stp = find_dbdev_id(srcid);
241 if (stp == NULL)
242 return 0;
243 dtp = find_dbdev_id(destid);
244 if (dtp == NULL)
245 return 0;
246
247 used = 0;
248 rv = 0;
249
250 /* Check to see if we can get both channels. */
251 spin_lock_irqsave(&au1xxx_dbdma_spin_lock, flags);
252 if (!(stp->dev_flags & DEV_FLAGS_INUSE) ||
253 (stp->dev_flags & DEV_FLAGS_ANYUSE)) {
254 /* Got source */
255 stp->dev_flags |= DEV_FLAGS_INUSE;
256 if (!(dtp->dev_flags & DEV_FLAGS_INUSE) ||
257 (dtp->dev_flags & DEV_FLAGS_ANYUSE)) {
258 /* Got destination */
259 dtp->dev_flags |= DEV_FLAGS_INUSE;
260 } else {
261 /* Can't get dest. Release src. */
262 stp->dev_flags &= ~DEV_FLAGS_INUSE;
263 used++;
264 }
265 } else
266 used++;
267 spin_unlock_irqrestore(&au1xxx_dbdma_spin_lock, flags);
268
269 if (!used) {
270 /* Let's see if we can allocate a channel for it. */
271 ctp = NULL;
272 chan = 0;
273 spin_lock_irqsave(&au1xxx_dbdma_spin_lock, flags);
274 for (i = 0; i < NUM_DBDMA_CHANS; i++)
275 if (chan_tab_ptr[i] == NULL) {
276 /*
277 * If kmalloc fails, it is caught below same
278 * as a channel not available.
279 */
280 ctp = kmalloc(sizeof(chan_tab_t), GFP_ATOMIC);
281 chan_tab_ptr[i] = ctp;
282 break;
283 }
284 spin_unlock_irqrestore(&au1xxx_dbdma_spin_lock, flags);
285
286 if (ctp != NULL) {
287 memset(ctp, 0, sizeof(chan_tab_t));
288 ctp->chan_index = chan = i;
289 dcp = DDMA_CHANNEL_BASE;
290 dcp += (0x0100 * chan);
291 ctp->chan_ptr = (au1x_dma_chan_t *)dcp;
292 cp = (au1x_dma_chan_t *)dcp;
293 ctp->chan_src = stp;
294 ctp->chan_dest = dtp;
295 ctp->chan_callback = callback;
296 ctp->chan_callparam = callparam;
297
298 /* Initialize channel configuration. */
299 i = 0;
300 if (stp->dev_intlevel)
301 i |= DDMA_CFG_SED;
302 if (stp->dev_intpolarity)
303 i |= DDMA_CFG_SP;
304 if (dtp->dev_intlevel)
305 i |= DDMA_CFG_DED;
306 if (dtp->dev_intpolarity)
307 i |= DDMA_CFG_DP;
308 if ((stp->dev_flags & DEV_FLAGS_SYNC) ||
309 (dtp->dev_flags & DEV_FLAGS_SYNC))
310 i |= DDMA_CFG_SYNC;
311 cp->ddma_cfg = i;
312 au_sync();
313
314 /* Return a non-zero value that can be used to
315 * find the channel information in subsequent
316 * operations.
317 */
318 rv = (u32)(&chan_tab_ptr[chan]);
319 } else {
320 /* Release devices */
321 stp->dev_flags &= ~DEV_FLAGS_INUSE;
322 dtp->dev_flags &= ~DEV_FLAGS_INUSE;
323 }
324 }
325 return rv;
326 }
327 EXPORT_SYMBOL(au1xxx_dbdma_chan_alloc);
328
329 /*
330 * Set the device width if source or destination is a FIFO.
331 * Should be 8, 16, or 32 bits.
332 */
333 u32 au1xxx_dbdma_set_devwidth(u32 chanid, int bits)
334 {
335 u32 rv;
336 chan_tab_t *ctp;
337 dbdev_tab_t *stp, *dtp;
338
339 ctp = *((chan_tab_t **)chanid);
340 stp = ctp->chan_src;
341 dtp = ctp->chan_dest;
342 rv = 0;
343
344 if (stp->dev_flags & DEV_FLAGS_IN) { /* Source in fifo */
345 rv = stp->dev_devwidth;
346 stp->dev_devwidth = bits;
347 }
348 if (dtp->dev_flags & DEV_FLAGS_OUT) { /* Destination out fifo */
349 rv = dtp->dev_devwidth;
350 dtp->dev_devwidth = bits;
351 }
352
353 return rv;
354 }
355 EXPORT_SYMBOL(au1xxx_dbdma_set_devwidth);
356
357 /* Allocate a descriptor ring, initializing as much as possible. */
358 u32 au1xxx_dbdma_ring_alloc(u32 chanid, int entries)
359 {
360 int i;
361 u32 desc_base, srcid, destid;
362 u32 cmd0, cmd1, src1, dest1;
363 u32 src0, dest0;
364 chan_tab_t *ctp;
365 dbdev_tab_t *stp, *dtp;
366 au1x_ddma_desc_t *dp;
367
368 /*
369 * I guess we could check this to be within the
370 * range of the table......
371 */
372 ctp = *((chan_tab_t **)chanid);
373 stp = ctp->chan_src;
374 dtp = ctp->chan_dest;
375
376 /*
377 * The descriptors must be 32-byte aligned. There is a
378 * possibility the allocation will give us such an address,
379 * and if we try that first we are likely to not waste larger
380 * slabs of memory.
381 */
382 desc_base = (u32)kmalloc(entries * sizeof(au1x_ddma_desc_t),
383 GFP_KERNEL|GFP_DMA);
384 if (desc_base == 0)
385 return 0;
386
387 if (desc_base & 0x1f) {
388 /*
389 * Lost....do it again, allocate extra, and round
390 * the address base.
391 */
392 kfree((const void *)desc_base);
393 i = entries * sizeof(au1x_ddma_desc_t);
394 i += (sizeof(au1x_ddma_desc_t) - 1);
395 desc_base = (u32)kmalloc(i, GFP_KERNEL|GFP_DMA);
396 if (desc_base == 0)
397 return 0;
398
399 desc_base = ALIGN_ADDR(desc_base, sizeof(au1x_ddma_desc_t));
400 }
401 dp = (au1x_ddma_desc_t *)desc_base;
402
403 /* Keep track of the base descriptor. */
404 ctp->chan_desc_base = dp;
405
406 /* Initialize the rings with as much information as we know. */
407 srcid = stp->dev_id;
408 destid = dtp->dev_id;
409
410 cmd0 = cmd1 = src1 = dest1 = 0;
411 src0 = dest0 = 0;
412
413 cmd0 |= DSCR_CMD0_SID(srcid);
414 cmd0 |= DSCR_CMD0_DID(destid);
415 cmd0 |= DSCR_CMD0_IE | DSCR_CMD0_CV;
416 cmd0 |= DSCR_CMD0_ST(DSCR_CMD0_ST_NOCHANGE);
417
418 /* Is it mem to mem transfer? */
419 if (((DSCR_CUSTOM2DEV_ID(srcid) == DSCR_CMD0_THROTTLE) ||
420 (DSCR_CUSTOM2DEV_ID(srcid) == DSCR_CMD0_ALWAYS)) &&
421 ((DSCR_CUSTOM2DEV_ID(destid) == DSCR_CMD0_THROTTLE) ||
422 (DSCR_CUSTOM2DEV_ID(destid) == DSCR_CMD0_ALWAYS)))
423 cmd0 |= DSCR_CMD0_MEM;
424
425 switch (stp->dev_devwidth) {
426 case 8:
427 cmd0 |= DSCR_CMD0_SW(DSCR_CMD0_BYTE);
428 break;
429 case 16:
430 cmd0 |= DSCR_CMD0_SW(DSCR_CMD0_HALFWORD);
431 break;
432 case 32:
433 default:
434 cmd0 |= DSCR_CMD0_SW(DSCR_CMD0_WORD);
435 break;
436 }
437
438 switch (dtp->dev_devwidth) {
439 case 8:
440 cmd0 |= DSCR_CMD0_DW(DSCR_CMD0_BYTE);
441 break;
442 case 16:
443 cmd0 |= DSCR_CMD0_DW(DSCR_CMD0_HALFWORD);
444 break;
445 case 32:
446 default:
447 cmd0 |= DSCR_CMD0_DW(DSCR_CMD0_WORD);
448 break;
449 }
450
451 /*
452 * If the device is marked as an in/out FIFO, ensure it is
453 * set non-coherent.
454 */
455 if (stp->dev_flags & DEV_FLAGS_IN)
456 cmd0 |= DSCR_CMD0_SN; /* Source in FIFO */
457 if (dtp->dev_flags & DEV_FLAGS_OUT)
458 cmd0 |= DSCR_CMD0_DN; /* Destination out FIFO */
459
460 /*
461 * Set up source1. For now, assume no stride and increment.
462 * A channel attribute update can change this later.
463 */
464 switch (stp->dev_tsize) {
465 case 1:
466 src1 |= DSCR_SRC1_STS(DSCR_xTS_SIZE1);
467 break;
468 case 2:
469 src1 |= DSCR_SRC1_STS(DSCR_xTS_SIZE2);
470 break;
471 case 4:
472 src1 |= DSCR_SRC1_STS(DSCR_xTS_SIZE4);
473 break;
474 case 8:
475 default:
476 src1 |= DSCR_SRC1_STS(DSCR_xTS_SIZE8);
477 break;
478 }
479
480 /* If source input is FIFO, set static address. */
481 if (stp->dev_flags & DEV_FLAGS_IN) {
482 if (stp->dev_flags & DEV_FLAGS_BURSTABLE)
483 src1 |= DSCR_SRC1_SAM(DSCR_xAM_BURST);
484 else
485 src1 |= DSCR_SRC1_SAM(DSCR_xAM_STATIC);
486 }
487
488 if (stp->dev_physaddr)
489 src0 = stp->dev_physaddr;
490
491 /*
492 * Set up dest1. For now, assume no stride and increment.
493 * A channel attribute update can change this later.
494 */
495 switch (dtp->dev_tsize) {
496 case 1:
497 dest1 |= DSCR_DEST1_DTS(DSCR_xTS_SIZE1);
498 break;
499 case 2:
500 dest1 |= DSCR_DEST1_DTS(DSCR_xTS_SIZE2);
501 break;
502 case 4:
503 dest1 |= DSCR_DEST1_DTS(DSCR_xTS_SIZE4);
504 break;
505 case 8:
506 default:
507 dest1 |= DSCR_DEST1_DTS(DSCR_xTS_SIZE8);
508 break;
509 }
510
511 /* If destination output is FIFO, set static address. */
512 if (dtp->dev_flags & DEV_FLAGS_OUT) {
513 if (dtp->dev_flags & DEV_FLAGS_BURSTABLE)
514 dest1 |= DSCR_DEST1_DAM(DSCR_xAM_BURST);
515 else
516 dest1 |= DSCR_DEST1_DAM(DSCR_xAM_STATIC);
517 }
518
519 if (dtp->dev_physaddr)
520 dest0 = dtp->dev_physaddr;
521
522 #if 0
523 printk(KERN_DEBUG "did:%x sid:%x cmd0:%x cmd1:%x source0:%x "
524 "source1:%x dest0:%x dest1:%x\n",
525 dtp->dev_id, stp->dev_id, cmd0, cmd1, src0,
526 src1, dest0, dest1);
527 #endif
528 for (i = 0; i < entries; i++) {
529 dp->dscr_cmd0 = cmd0;
530 dp->dscr_cmd1 = cmd1;
531 dp->dscr_source0 = src0;
532 dp->dscr_source1 = src1;
533 dp->dscr_dest0 = dest0;
534 dp->dscr_dest1 = dest1;
535 dp->dscr_stat = 0;
536 dp->sw_context = 0;
537 dp->sw_status = 0;
538 dp->dscr_nxtptr = DSCR_NXTPTR(virt_to_phys(dp + 1));
539 dp++;
540 }
541
542 /* Make last descrptor point to the first. */
543 dp--;
544 dp->dscr_nxtptr = DSCR_NXTPTR(virt_to_phys(ctp->chan_desc_base));
545 ctp->get_ptr = ctp->put_ptr = ctp->cur_ptr = ctp->chan_desc_base;
546
547 return (u32)ctp->chan_desc_base;
548 }
549 EXPORT_SYMBOL(au1xxx_dbdma_ring_alloc);
550
551 /*
552 * Put a source buffer into the DMA ring.
553 * This updates the source pointer and byte count. Normally used
554 * for memory to fifo transfers.
555 */
556 u32 _au1xxx_dbdma_put_source(u32 chanid, void *buf, int nbytes, u32 flags)
557 {
558 chan_tab_t *ctp;
559 au1x_ddma_desc_t *dp;
560
561 /*
562 * I guess we could check this to be within the
563 * range of the table......
564 */
565 ctp = *(chan_tab_t **)chanid;
566
567 /*
568 * We should have multiple callers for a particular channel,
569 * an interrupt doesn't affect this pointer nor the descriptor,
570 * so no locking should be needed.
571 */
572 dp = ctp->put_ptr;
573
574 /*
575 * If the descriptor is valid, we are way ahead of the DMA
576 * engine, so just return an error condition.
577 */
578 if (dp->dscr_cmd0 & DSCR_CMD0_V)
579 return 0;
580
581 /* Load up buffer address and byte count. */
582 dp->dscr_source0 = virt_to_phys(buf);
583 dp->dscr_cmd1 = nbytes;
584 /* Check flags */
585 if (flags & DDMA_FLAGS_IE)
586 dp->dscr_cmd0 |= DSCR_CMD0_IE;
587 if (flags & DDMA_FLAGS_NOIE)
588 dp->dscr_cmd0 &= ~DSCR_CMD0_IE;
589
590 /*
591 * There is an errata on the Au1200/Au1550 parts that could result
592 * in "stale" data being DMA'ed. It has to do with the snoop logic on
593 * the cache eviction buffer. DMA_NONCOHERENT is on by default for
594 * these parts. If it is fixed in the future, these dma_cache_inv will
595 * just be nothing more than empty macros. See io.h.
596 */
597 dma_cache_wback_inv((unsigned long)buf, nbytes);
598 dp->dscr_cmd0 |= DSCR_CMD0_V; /* Let it rip */
599 au_sync();
600 dma_cache_wback_inv((unsigned long)dp, sizeof(dp));
601 ctp->chan_ptr->ddma_dbell = 0;
602
603 /* Get next descriptor pointer. */
604 ctp->put_ptr = phys_to_virt(DSCR_GET_NXTPTR(dp->dscr_nxtptr));
605
606 /* Return something non-zero. */
607 return nbytes;
608 }
609 EXPORT_SYMBOL(_au1xxx_dbdma_put_source);
610
611 /* Put a destination buffer into the DMA ring.
612 * This updates the destination pointer and byte count. Normally used
613 * to place an empty buffer into the ring for fifo to memory transfers.
614 */
615 u32
616 _au1xxx_dbdma_put_dest(u32 chanid, void *buf, int nbytes, u32 flags)
617 {
618 chan_tab_t *ctp;
619 au1x_ddma_desc_t *dp;
620
621 /* I guess we could check this to be within the
622 * range of the table......
623 */
624 ctp = *((chan_tab_t **)chanid);
625
626 /* We should have multiple callers for a particular channel,
627 * an interrupt doesn't affect this pointer nor the descriptor,
628 * so no locking should be needed.
629 */
630 dp = ctp->put_ptr;
631
632 /* If the descriptor is valid, we are way ahead of the DMA
633 * engine, so just return an error condition.
634 */
635 if (dp->dscr_cmd0 & DSCR_CMD0_V)
636 return 0;
637
638 /* Load up buffer address and byte count */
639
640 /* Check flags */
641 if (flags & DDMA_FLAGS_IE)
642 dp->dscr_cmd0 |= DSCR_CMD0_IE;
643 if (flags & DDMA_FLAGS_NOIE)
644 dp->dscr_cmd0 &= ~DSCR_CMD0_IE;
645
646 dp->dscr_dest0 = virt_to_phys(buf);
647 dp->dscr_cmd1 = nbytes;
648 #if 0
649 printk(KERN_DEBUG "cmd0:%x cmd1:%x source0:%x source1:%x dest0:%x dest1:%x\n",
650 dp->dscr_cmd0, dp->dscr_cmd1, dp->dscr_source0,
651 dp->dscr_source1, dp->dscr_dest0, dp->dscr_dest1);
652 #endif
653 /*
654 * There is an errata on the Au1200/Au1550 parts that could result in
655 * "stale" data being DMA'ed. It has to do with the snoop logic on the
656 * cache eviction buffer. DMA_NONCOHERENT is on by default for these
657 * parts. If it is fixed in the future, these dma_cache_inv will just
658 * be nothing more than empty macros. See io.h.
659 */
660 dma_cache_inv((unsigned long)buf, nbytes);
661 dp->dscr_cmd0 |= DSCR_CMD0_V; /* Let it rip */
662 au_sync();
663 dma_cache_wback_inv((unsigned long)dp, sizeof(dp));
664 ctp->chan_ptr->ddma_dbell = 0;
665
666 /* Get next descriptor pointer. */
667 ctp->put_ptr = phys_to_virt(DSCR_GET_NXTPTR(dp->dscr_nxtptr));
668
669 /* Return something non-zero. */
670 return nbytes;
671 }
672 EXPORT_SYMBOL(_au1xxx_dbdma_put_dest);
673
674 /*
675 * Get a destination buffer into the DMA ring.
676 * Normally used to get a full buffer from the ring during fifo
677 * to memory transfers. This does not set the valid bit, you will
678 * have to put another destination buffer to keep the DMA going.
679 */
680 u32 au1xxx_dbdma_get_dest(u32 chanid, void **buf, int *nbytes)
681 {
682 chan_tab_t *ctp;
683 au1x_ddma_desc_t *dp;
684 u32 rv;
685
686 /*
687 * I guess we could check this to be within the
688 * range of the table......
689 */
690 ctp = *((chan_tab_t **)chanid);
691
692 /*
693 * We should have multiple callers for a particular channel,
694 * an interrupt doesn't affect this pointer nor the descriptor,
695 * so no locking should be needed.
696 */
697 dp = ctp->get_ptr;
698
699 /*
700 * If the descriptor is valid, we are way ahead of the DMA
701 * engine, so just return an error condition.
702 */
703 if (dp->dscr_cmd0 & DSCR_CMD0_V)
704 return 0;
705
706 /* Return buffer address and byte count. */
707 *buf = (void *)(phys_to_virt(dp->dscr_dest0));
708 *nbytes = dp->dscr_cmd1;
709 rv = dp->dscr_stat;
710
711 /* Get next descriptor pointer. */
712 ctp->get_ptr = phys_to_virt(DSCR_GET_NXTPTR(dp->dscr_nxtptr));
713
714 /* Return something non-zero. */
715 return rv;
716 }
717 EXPORT_SYMBOL_GPL(au1xxx_dbdma_get_dest);
718
719 void au1xxx_dbdma_stop(u32 chanid)
720 {
721 chan_tab_t *ctp;
722 au1x_dma_chan_t *cp;
723 int halt_timeout = 0;
724
725 ctp = *((chan_tab_t **)chanid);
726
727 cp = ctp->chan_ptr;
728 cp->ddma_cfg &= ~DDMA_CFG_EN; /* Disable channel */
729 au_sync();
730 while (!(cp->ddma_stat & DDMA_STAT_H)) {
731 udelay(1);
732 halt_timeout++;
733 if (halt_timeout > 100) {
734 printk(KERN_WARNING "warning: DMA channel won't halt\n");
735 break;
736 }
737 }
738 /* clear current desc valid and doorbell */
739 cp->ddma_stat |= (DDMA_STAT_DB | DDMA_STAT_V);
740 au_sync();
741 }
742 EXPORT_SYMBOL(au1xxx_dbdma_stop);
743
744 /*
745 * Start using the current descriptor pointer. If the DBDMA encounters
746 * a non-valid descriptor, it will stop. In this case, we can just
747 * continue by adding a buffer to the list and starting again.
748 */
749 void au1xxx_dbdma_start(u32 chanid)
750 {
751 chan_tab_t *ctp;
752 au1x_dma_chan_t *cp;
753
754 ctp = *((chan_tab_t **)chanid);
755 cp = ctp->chan_ptr;
756 cp->ddma_desptr = virt_to_phys(ctp->cur_ptr);
757 cp->ddma_cfg |= DDMA_CFG_EN; /* Enable channel */
758 au_sync();
759 cp->ddma_dbell = 0;
760 au_sync();
761 }
762 EXPORT_SYMBOL(au1xxx_dbdma_start);
763
764 void au1xxx_dbdma_reset(u32 chanid)
765 {
766 chan_tab_t *ctp;
767 au1x_ddma_desc_t *dp;
768
769 au1xxx_dbdma_stop(chanid);
770
771 ctp = *((chan_tab_t **)chanid);
772 ctp->get_ptr = ctp->put_ptr = ctp->cur_ptr = ctp->chan_desc_base;
773
774 /* Run through the descriptors and reset the valid indicator. */
775 dp = ctp->chan_desc_base;
776
777 do {
778 dp->dscr_cmd0 &= ~DSCR_CMD0_V;
779 /*
780 * Reset our software status -- this is used to determine
781 * if a descriptor is in use by upper level software. Since
782 * posting can reset 'V' bit.
783 */
784 dp->sw_status = 0;
785 dp = phys_to_virt(DSCR_GET_NXTPTR(dp->dscr_nxtptr));
786 } while (dp != ctp->chan_desc_base);
787 }
788 EXPORT_SYMBOL(au1xxx_dbdma_reset);
789
790 u32 au1xxx_get_dma_residue(u32 chanid)
791 {
792 chan_tab_t *ctp;
793 au1x_dma_chan_t *cp;
794 u32 rv;
795
796 ctp = *((chan_tab_t **)chanid);
797 cp = ctp->chan_ptr;
798
799 /* This is only valid if the channel is stopped. */
800 rv = cp->ddma_bytecnt;
801 au_sync();
802
803 return rv;
804 }
805 EXPORT_SYMBOL_GPL(au1xxx_get_dma_residue);
806
807 void au1xxx_dbdma_chan_free(u32 chanid)
808 {
809 chan_tab_t *ctp;
810 dbdev_tab_t *stp, *dtp;
811
812 ctp = *((chan_tab_t **)chanid);
813 stp = ctp->chan_src;
814 dtp = ctp->chan_dest;
815
816 au1xxx_dbdma_stop(chanid);
817
818 kfree((void *)ctp->chan_desc_base);
819
820 stp->dev_flags &= ~DEV_FLAGS_INUSE;
821 dtp->dev_flags &= ~DEV_FLAGS_INUSE;
822 chan_tab_ptr[ctp->chan_index] = NULL;
823
824 kfree(ctp);
825 }
826 EXPORT_SYMBOL(au1xxx_dbdma_chan_free);
827
828 static irqreturn_t dbdma_interrupt(int irq, void *dev_id)
829 {
830 u32 intstat;
831 u32 chan_index;
832 chan_tab_t *ctp;
833 au1x_ddma_desc_t *dp;
834 au1x_dma_chan_t *cp;
835
836 intstat = dbdma_gptr->ddma_intstat;
837 au_sync();
838 chan_index = __ffs(intstat);
839
840 ctp = chan_tab_ptr[chan_index];
841 cp = ctp->chan_ptr;
842 dp = ctp->cur_ptr;
843
844 /* Reset interrupt. */
845 cp->ddma_irq = 0;
846 au_sync();
847
848 if (ctp->chan_callback)
849 ctp->chan_callback(irq, ctp->chan_callparam);
850
851 ctp->cur_ptr = phys_to_virt(DSCR_GET_NXTPTR(dp->dscr_nxtptr));
852 return IRQ_RETVAL(1);
853 }
854
855 static void au1xxx_dbdma_init(void)
856 {
857 int irq_nr;
858
859 dbdma_gptr->ddma_config = 0;
860 dbdma_gptr->ddma_throttle = 0;
861 dbdma_gptr->ddma_inten = 0xffff;
862 au_sync();
863
864 #if defined(CONFIG_SOC_AU1550)
865 irq_nr = AU1550_DDMA_INT;
866 #elif defined(CONFIG_SOC_AU1200)
867 irq_nr = AU1200_DDMA_INT;
868 #else
869 #error Unknown Au1x00 SOC
870 #endif
871
872 if (request_irq(irq_nr, dbdma_interrupt, IRQF_DISABLED,
873 "Au1xxx dbdma", (void *)dbdma_gptr))
874 printk(KERN_ERR "Can't get 1550 dbdma irq");
875 }
876
877 void au1xxx_dbdma_dump(u32 chanid)
878 {
879 chan_tab_t *ctp;
880 au1x_ddma_desc_t *dp;
881 dbdev_tab_t *stp, *dtp;
882 au1x_dma_chan_t *cp;
883 u32 i = 0;
884
885 ctp = *((chan_tab_t **)chanid);
886 stp = ctp->chan_src;
887 dtp = ctp->chan_dest;
888 cp = ctp->chan_ptr;
889
890 printk(KERN_DEBUG "Chan %x, stp %x (dev %d) dtp %x (dev %d) \n",
891 (u32)ctp, (u32)stp, stp - dbdev_tab, (u32)dtp,
892 dtp - dbdev_tab);
893 printk(KERN_DEBUG "desc base %x, get %x, put %x, cur %x\n",
894 (u32)(ctp->chan_desc_base), (u32)(ctp->get_ptr),
895 (u32)(ctp->put_ptr), (u32)(ctp->cur_ptr));
896
897 printk(KERN_DEBUG "dbdma chan %x\n", (u32)cp);
898 printk(KERN_DEBUG "cfg %08x, desptr %08x, statptr %08x\n",
899 cp->ddma_cfg, cp->ddma_desptr, cp->ddma_statptr);
900 printk(KERN_DEBUG "dbell %08x, irq %08x, stat %08x, bytecnt %08x\n",
901 cp->ddma_dbell, cp->ddma_irq, cp->ddma_stat,
902 cp->ddma_bytecnt);
903
904 /* Run through the descriptors */
905 dp = ctp->chan_desc_base;
906
907 do {
908 printk(KERN_DEBUG "Dp[%d]= %08x, cmd0 %08x, cmd1 %08x\n",
909 i++, (u32)dp, dp->dscr_cmd0, dp->dscr_cmd1);
910 printk(KERN_DEBUG "src0 %08x, src1 %08x, dest0 %08x, dest1 %08x\n",
911 dp->dscr_source0, dp->dscr_source1,
912 dp->dscr_dest0, dp->dscr_dest1);
913 printk(KERN_DEBUG "stat %08x, nxtptr %08x\n",
914 dp->dscr_stat, dp->dscr_nxtptr);
915 dp = phys_to_virt(DSCR_GET_NXTPTR(dp->dscr_nxtptr));
916 } while (dp != ctp->chan_desc_base);
917 }
918
919 /* Put a descriptor into the DMA ring.
920 * This updates the source/destination pointers and byte count.
921 */
922 u32 au1xxx_dbdma_put_dscr(u32 chanid, au1x_ddma_desc_t *dscr)
923 {
924 chan_tab_t *ctp;
925 au1x_ddma_desc_t *dp;
926 u32 nbytes = 0;
927
928 /*
929 * I guess we could check this to be within the
930 * range of the table......
931 */
932 ctp = *((chan_tab_t **)chanid);
933
934 /*
935 * We should have multiple callers for a particular channel,
936 * an interrupt doesn't affect this pointer nor the descriptor,
937 * so no locking should be needed.
938 */
939 dp = ctp->put_ptr;
940
941 /*
942 * If the descriptor is valid, we are way ahead of the DMA
943 * engine, so just return an error condition.
944 */
945 if (dp->dscr_cmd0 & DSCR_CMD0_V)
946 return 0;
947
948 /* Load up buffer addresses and byte count. */
949 dp->dscr_dest0 = dscr->dscr_dest0;
950 dp->dscr_source0 = dscr->dscr_source0;
951 dp->dscr_dest1 = dscr->dscr_dest1;
952 dp->dscr_source1 = dscr->dscr_source1;
953 dp->dscr_cmd1 = dscr->dscr_cmd1;
954 nbytes = dscr->dscr_cmd1;
955 /* Allow the caller to specifiy if an interrupt is generated */
956 dp->dscr_cmd0 &= ~DSCR_CMD0_IE;
957 dp->dscr_cmd0 |= dscr->dscr_cmd0 | DSCR_CMD0_V;
958 ctp->chan_ptr->ddma_dbell = 0;
959
960 /* Get next descriptor pointer. */
961 ctp->put_ptr = phys_to_virt(DSCR_GET_NXTPTR(dp->dscr_nxtptr));
962
963 /* Return something non-zero. */
964 return nbytes;
965 }
966
967 #endif /* defined(CONFIG_SOC_AU1550) || defined(CONFIG_SOC_AU1200) */
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