arch/mips/mips-boards/generic/time.c

   1 /*
   2  * Carsten Langgaard, carstenl@mips.com
   3  * Copyright (C) 1999,2000 MIPS Technologies, Inc.  All rights reserved.
   4  *
   5  *  This program is free software; you can distribute it and/or modify it
   6  *  under the terms of the GNU General Public License (Version 2) as
   7  *  published by the Free Software Foundation.
   8  *
   9  *  This program is distributed in the hope it will be useful, but WITHOUT
  10  *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  12  *  for more details.
  13  *
  14  *  You should have received a copy of the GNU General Public License along
  15  *  with this program; if not, write to the Free Software Foundation, Inc.,
  16  *  59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
  17  *
  18  * Setting up the clock on the MIPS boards.
  19  */
  20
  21 #include <linux/types.h>
  22 #include <linux/init.h>
  23 #include <linux/kernel_stat.h>
  24 #include <linux/sched.h>
  25 #include <linux/spinlock.h>
  26 #include <linux/interrupt.h>
  27 #include <linux/time.h>
  28 #include <linux/timex.h>
  29 #include <linux/mc146818rtc.h>
  30
  31 #include <asm/mipsregs.h>
  32 #include <asm/mipsmtregs.h>
  33 #include <asm/hardirq.h>
  34 #include <asm/i8253.h>
  35 #include <asm/irq.h>
  36 #include <asm/div64.h>
  37 #include <asm/cpu.h>
  38 #include <asm/time.h>
  39 #include <asm/mc146818-time.h>
  40 #include <asm/msc01_ic.h>
  41
  42 #include <asm/mips-boards/generic.h>
  43 #include <asm/mips-boards/prom.h>
  44
  45 #ifdef CONFIG_MIPS_ATLAS
  46 #include <asm/mips-boards/atlasint.h>
  47 #endif
  48 #ifdef CONFIG_MIPS_MALTA
  49 #include <asm/mips-boards/maltaint.h>
  50 #endif
  51 #ifdef CONFIG_MIPS_SEAD
  52 #include <asm/mips-boards/seadint.h>
  53 #endif
  54
  55 unsigned long cpu_khz;
  56
  57 static int mips_cpu_timer_irq;
  58 static int mips_cpu_perf_irq;
  59 extern int cp0_perfcount_irq;
  60
  61 DEFINE_PER_CPU(unsigned int, tickcount);
  62 #define tickcount_this_cpu __get_cpu_var(tickcount)
  63 static unsigned long ledbitmask;
  64
  65 static void mips_timer_dispatch(void)
  66 {
  67 #if defined(CONFIG_MIPS_MALTA) || defined(CONFIG_MIPS_ATLAS)
  68         /*
  69          * Yes, this is very tacky, won't work as expected with SMTC and
  70          * dyntick will break it,
  71          * but it gives me a nice warm feeling during debug
  72          */
  73 #define LEDBAR 0xbf000408
  74         if (tickcount_this_cpu++ >= HZ) {
  75                 tickcount_this_cpu = 0;
  76                 change_bit(smp_processor_id(), &ledbitmask);
  77                 smp_wmb(); /* Make sure every one else sees the change */
  78                 /* This will pick up any recent changes made by other CPU's */
  79                 *(unsigned int *)LEDBAR = ledbitmask;
  80         }
  81 #endif
  82         do_IRQ(mips_cpu_timer_irq);
  83 }
  84
  85 static void mips_perf_dispatch(void)
  86 {
  87         do_IRQ(mips_cpu_perf_irq);
  88 }
  89
  90 /*
  91  * Estimate CPU frequency.  Sets mips_hpt_frequency as a side-effect
  92  */
  93 static unsigned int __init estimate_cpu_frequency(void)
  94 {
  95         unsigned int prid = read_c0_prid() & 0xffff00;
  96         unsigned int count;
  97
  98 #if defined(CONFIG_MIPS_SEAD) || defined(CONFIG_MIPS_SIM)
  99         /*
 100          * The SEAD board doesn't have a real time clock, so we can't
 101          * really calculate the timer frequency
 102          * For now we hardwire the SEAD board frequency to 12MHz.
 103          */
 104
 105         if ((prid == (PRID_COMP_MIPS | PRID_IMP_20KC)) ||
 106             (prid == (PRID_COMP_MIPS | PRID_IMP_25KF)))
 107                 count = 12000000;
 108         else
 109                 count = 6000000;
 110 #endif
 111 #if defined(CONFIG_MIPS_ATLAS) || defined(CONFIG_MIPS_MALTA)
 112         unsigned long flags;
 113         unsigned int start;
 114
 115         local_irq_save(flags);
 116
 117         /* Start counter exactly on falling edge of update flag */
 118         while (CMOS_READ(RTC_REG_A) & RTC_UIP);
 119         while (!(CMOS_READ(RTC_REG_A) & RTC_UIP));
 120
 121         /* Start r4k counter. */
 122         start = read_c0_count();
 123
 124         /* Read counter exactly on falling edge of update flag */
 125         while (CMOS_READ(RTC_REG_A) & RTC_UIP);
 126         while (!(CMOS_READ(RTC_REG_A) & RTC_UIP));
 127
 128         count = read_c0_count() - start;
 129
 130         /* restore interrupts */
 131         local_irq_restore(flags);
 132 #endif
 133
 134         mips_hpt_frequency = count;
 135         if ((prid != (PRID_COMP_MIPS | PRID_IMP_20KC)) &&
 136             (prid != (PRID_COMP_MIPS | PRID_IMP_25KF)))
 137                 count *= 2;
 138
 139         count += 5000;    /* round */
 140         count -= count%10000;
 141
 142         return count;
 143 }
 144
 145 unsigned long read_persistent_clock(void)
 146 {
 147         return mc146818_get_cmos_time();
 148 }
 149
 150 static void __init plat_perf_setup(void)
 151 {
 152 #ifdef MSC01E_INT_BASE
 153         if (cpu_has_veic) {
 154                 set_vi_handler(MSC01E_INT_PERFCTR, mips_perf_dispatch);
 155                 mips_cpu_perf_irq = MSC01E_INT_BASE + MSC01E_INT_PERFCTR;
 156         } else
 157 #endif
 158         if (cp0_perfcount_irq >= 0) {
 159                 if (cpu_has_vint)
 160                         set_vi_handler(cp0_perfcount_irq, mips_perf_dispatch);
 161                 mips_cpu_perf_irq = MIPS_CPU_IRQ_BASE + cp0_perfcount_irq;
 162 #ifdef CONFIG_SMP
 163                 set_irq_handler(mips_cpu_perf_irq, handle_percpu_irq);
 164 #endif
 165         }
 166 }
 167
 168 unsigned int __cpuinit get_c0_compare_int(void)
 169 {
 170 #ifdef MSC01E_INT_BASE
 171         if (cpu_has_veic) {
 172                 set_vi_handler(MSC01E_INT_CPUCTR, mips_timer_dispatch);
 173                 mips_cpu_timer_irq = MSC01E_INT_BASE + MSC01E_INT_CPUCTR;
 174         } else
 175 #endif
 176         {
 177                 if (cpu_has_vint)
 178                         set_vi_handler(cp0_compare_irq, mips_timer_dispatch);
 179                 mips_cpu_timer_irq = MIPS_CPU_IRQ_BASE + cp0_compare_irq;
 180         }
 181
 182         return mips_cpu_timer_irq;
 183 }
 184
 185 void __init plat_time_init(void)
 186 {
 187         unsigned int est_freq;
 188
 189         /* Set Data mode - binary. */
 190         CMOS_WRITE(CMOS_READ(RTC_CONTROL) | RTC_DM_BINARY, RTC_CONTROL);
 191
 192         est_freq = estimate_cpu_frequency();
 193
 194         printk("CPU frequency %d.%02d MHz\n", est_freq/1000000,
 195                (est_freq%1000000)*100/1000000);
 196
 197         cpu_khz = est_freq / 1000;
 198
 199         mips_scroll_message();
 200 #ifdef CONFIG_I8253             /* Only Malta has a PIT */
 201         setup_pit_timer();
 202 #endif
 203
 204         plat_perf_setup();
 205 }