arch/powerpc/sysdev/fsl_rio.c

   1 /*
   2  * Freescale MPC85xx/MPC86xx RapidIO support
   3  *
   4  * Copyright (C) 2007, 2008 Freescale Semiconductor, Inc.
   5  * Zhang Wei <wei.zhang@freescale.com>
   6  *
   7  * Copyright 2005 MontaVista Software, Inc.
   8  * Matt Porter <mporter@kernel.crashing.org>
   9  *
  10  * This program is free software; you can redistribute  it and/or modify it
  11  * under  the terms of  the GNU General  Public License as published by the
  12  * Free Software Foundation;  either version 2 of the  License, or (at your
  13  * option) any later version.
  14  */
  15
  16 #include <linux/init.h>
  17 #include <linux/module.h>
  18 #include <linux/types.h>
  19 #include <linux/dma-mapping.h>
  20 #include <linux/interrupt.h>
  21 #include <linux/rio.h>
  22 #include <linux/rio_drv.h>
  23 #include <linux/of_platform.h>
  24 #include <linux/delay.h>
  25
  26 #include <asm/io.h>
  27
  28 /* RapidIO definition irq, which read from OF-tree */
  29 #define IRQ_RIO_BELL(m)         (((struct rio_priv *)(m->priv))->bellirq)
  30 #define IRQ_RIO_TX(m)           (((struct rio_priv *)(m->priv))->txirq)
  31 #define IRQ_RIO_RX(m)           (((struct rio_priv *)(m->priv))->rxirq)
  32
  33 #define RIO_ATMU_REGS_OFFSET    0x10c00
  34 #define RIO_P_MSG_REGS_OFFSET   0x11000
  35 #define RIO_S_MSG_REGS_OFFSET   0x13000
  36 #define RIO_ESCSR               0x158
  37 #define RIO_CCSR                0x15c
  38 #define RIO_ISR_AACR            0x10120
  39 #define RIO_ISR_AACR_AA         0x1     /* Accept All ID */
  40 #define RIO_MAINT_WIN_SIZE      0x400000
  41 #define RIO_DBELL_WIN_SIZE      0x1000
  42
  43 #define RIO_MSG_OMR_MUI         0x00000002
  44 #define RIO_MSG_OSR_TE          0x00000080
  45 #define RIO_MSG_OSR_QOI         0x00000020
  46 #define RIO_MSG_OSR_QFI         0x00000010
  47 #define RIO_MSG_OSR_MUB         0x00000004
  48 #define RIO_MSG_OSR_EOMI        0x00000002
  49 #define RIO_MSG_OSR_QEI         0x00000001
  50
  51 #define RIO_MSG_IMR_MI          0x00000002
  52 #define RIO_MSG_ISR_TE          0x00000080
  53 #define RIO_MSG_ISR_QFI         0x00000010
  54 #define RIO_MSG_ISR_DIQI        0x00000001
  55
  56 #define RIO_MSG_DESC_SIZE       32
  57 #define RIO_MSG_BUFFER_SIZE     4096
  58 #define RIO_MIN_TX_RING_SIZE    2
  59 #define RIO_MAX_TX_RING_SIZE    2048
  60 #define RIO_MIN_RX_RING_SIZE    2
  61 #define RIO_MAX_RX_RING_SIZE    2048
  62
  63 #define DOORBELL_DMR_DI         0x00000002
  64 #define DOORBELL_DSR_TE         0x00000080
  65 #define DOORBELL_DSR_QFI        0x00000010
  66 #define DOORBELL_DSR_DIQI       0x00000001
  67 #define DOORBELL_TID_OFFSET     0x02
  68 #define DOORBELL_SID_OFFSET     0x04
  69 #define DOORBELL_INFO_OFFSET    0x06
  70
  71 #define DOORBELL_MESSAGE_SIZE   0x08
  72 #define DBELL_SID(x)            (*(u16 *)(x + DOORBELL_SID_OFFSET))
  73 #define DBELL_TID(x)            (*(u16 *)(x + DOORBELL_TID_OFFSET))
  74 #define DBELL_INF(x)            (*(u16 *)(x + DOORBELL_INFO_OFFSET))
  75
  76 struct rio_atmu_regs {
  77         u32 rowtar;
  78         u32 rowtear;
  79         u32 rowbar;
  80         u32 pad2;
  81         u32 rowar;
  82         u32 pad3[3];
  83 };
  84
  85 struct rio_msg_regs {
  86         u32 omr;
  87         u32 osr;
  88         u32 pad1;
  89         u32 odqdpar;
  90         u32 pad2;
  91         u32 osar;
  92         u32 odpr;
  93         u32 odatr;
  94         u32 odcr;
  95         u32 pad3;
  96         u32 odqepar;
  97         u32 pad4[13];
  98         u32 imr;
  99         u32 isr;
 100         u32 pad5;
 101         u32 ifqdpar;
 102         u32 pad6;
 103         u32 ifqepar;
 104         u32 pad7[226];
 105         u32 odmr;
 106         u32 odsr;
 107         u32 res0[4];
 108         u32 oddpr;
 109         u32 oddatr;
 110         u32 res1[3];
 111         u32 odretcr;
 112         u32 res2[12];
 113         u32 dmr;
 114         u32 dsr;
 115         u32 pad8;
 116         u32 dqdpar;
 117         u32 pad9;
 118         u32 dqepar;
 119         u32 pad10[26];
 120         u32 pwmr;
 121         u32 pwsr;
 122         u32 pad11;
 123         u32 pwqbar;
 124 };
 125
 126 struct rio_tx_desc {
 127         u32 res1;
 128         u32 saddr;
 129         u32 dport;
 130         u32 dattr;
 131         u32 res2;
 132         u32 res3;
 133         u32 dwcnt;
 134         u32 res4;
 135 };
 136
 137 struct rio_dbell_ring {
 138         void *virt;
 139         dma_addr_t phys;
 140 };
 141
 142 struct rio_msg_tx_ring {
 143         void *virt;
 144         dma_addr_t phys;
 145         void *virt_buffer[RIO_MAX_TX_RING_SIZE];
 146         dma_addr_t phys_buffer[RIO_MAX_TX_RING_SIZE];
 147         int tx_slot;
 148         int size;
 149         void *dev_id;
 150 };
 151
 152 struct rio_msg_rx_ring {
 153         void *virt;
 154         dma_addr_t phys;
 155         void *virt_buffer[RIO_MAX_RX_RING_SIZE];
 156         int rx_slot;
 157         int size;
 158         void *dev_id;
 159 };
 160
 161 struct rio_priv {
 162         void __iomem *regs_win;
 163         struct rio_atmu_regs __iomem *atmu_regs;
 164         struct rio_atmu_regs __iomem *maint_atmu_regs;
 165         struct rio_atmu_regs __iomem *dbell_atmu_regs;
 166         void __iomem *dbell_win;
 167         void __iomem *maint_win;
 168         struct rio_msg_regs __iomem *msg_regs;
 169         struct rio_dbell_ring dbell_ring;
 170         struct rio_msg_tx_ring msg_tx_ring;
 171         struct rio_msg_rx_ring msg_rx_ring;
 172         int bellirq;
 173         int txirq;
 174         int rxirq;
 175 };
 176
 177 /**
 178  * fsl_rio_doorbell_send - Send a MPC85xx doorbell message
 179  * @mport: RapidIO master port info
 180  * @index: ID of RapidIO interface
 181  * @destid: Destination ID of target device
 182  * @data: 16-bit info field of RapidIO doorbell message
 183  *
 184  * Sends a MPC85xx doorbell message. Returns %0 on success or
 185  * %-EINVAL on failure.
 186  */
 187 static int fsl_rio_doorbell_send(struct rio_mport *mport,
 188                                 int index, u16 destid, u16 data)
 189 {
 190         struct rio_priv *priv = mport->priv;
 191         pr_debug("fsl_doorbell_send: index %d destid %4.4x data %4.4x\n",
 192                  index, destid, data);
 193         switch (mport->phy_type) {
 194         case RIO_PHY_PARALLEL:
 195                 out_be32(&priv->dbell_atmu_regs->rowtar, destid << 22);
 196                 out_be16(priv->dbell_win, data);
 197                 break;
 198         case RIO_PHY_SERIAL:
 199                 /* In the serial version silicons, such as MPC8548, MPC8641,
 200                  * below operations is must be.
 201                  */
 202                 out_be32(&priv->msg_regs->odmr, 0x00000000);
 203                 out_be32(&priv->msg_regs->odretcr, 0x00000004);
 204                 out_be32(&priv->msg_regs->oddpr, destid << 16);
 205                 out_be32(&priv->msg_regs->oddatr, data);
 206                 out_be32(&priv->msg_regs->odmr, 0x00000001);
 207                 break;
 208         }
 209
 210         return 0;
 211 }
 212
 213 /**
 214  * fsl_local_config_read - Generate a MPC85xx local config space read
 215  * @mport: RapidIO master port info
 216  * @index: ID of RapdiIO interface
 217  * @offset: Offset into configuration space
 218  * @len: Length (in bytes) of the maintenance transaction
 219  * @data: Value to be read into
 220  *
 221  * Generates a MPC85xx local configuration space read. Returns %0 on
 222  * success or %-EINVAL on failure.
 223  */
 224 static int fsl_local_config_read(struct rio_mport *mport,
 225                                 int index, u32 offset, int len, u32 *data)
 226 {
 227         struct rio_priv *priv = mport->priv;
 228         pr_debug("fsl_local_config_read: index %d offset %8.8x\n", index,
 229                  offset);
 230         *data = in_be32(priv->regs_win + offset);
 231
 232         return 0;
 233 }
 234
 235 /**
 236  * fsl_local_config_write - Generate a MPC85xx local config space write
 237  * @mport: RapidIO master port info
 238  * @index: ID of RapdiIO interface
 239  * @offset: Offset into configuration space
 240  * @len: Length (in bytes) of the maintenance transaction
 241  * @data: Value to be written
 242  *
 243  * Generates a MPC85xx local configuration space write. Returns %0 on
 244  * success or %-EINVAL on failure.
 245  */
 246 static int fsl_local_config_write(struct rio_mport *mport,
 247                                 int index, u32 offset, int len, u32 data)
 248 {
 249         struct rio_priv *priv = mport->priv;
 250         pr_debug
 251             ("fsl_local_config_write: index %d offset %8.8x data %8.8x\n",
 252              index, offset, data);
 253         out_be32(priv->regs_win + offset, data);
 254
 255         return 0;
 256 }
 257
 258 /**
 259  * fsl_rio_config_read - Generate a MPC85xx read maintenance transaction
 260  * @mport: RapidIO master port info
 261  * @index: ID of RapdiIO interface
 262  * @destid: Destination ID of transaction
 263  * @hopcount: Number of hops to target device
 264  * @offset: Offset into configuration space
 265  * @len: Length (in bytes) of the maintenance transaction
 266  * @val: Location to be read into
 267  *
 268  * Generates a MPC85xx read maintenance transaction. Returns %0 on
 269  * success or %-EINVAL on failure.
 270  */
 271 static int
 272 fsl_rio_config_read(struct rio_mport *mport, int index, u16 destid,
 273                         u8 hopcount, u32 offset, int len, u32 *val)
 274 {
 275         struct rio_priv *priv = mport->priv;
 276         u8 *data;
 277
 278         pr_debug
 279             ("fsl_rio_config_read: index %d destid %d hopcount %d offset %8.8x len %d\n",
 280              index, destid, hopcount, offset, len);
 281         out_be32(&priv->maint_atmu_regs->rowtar,
 282                  (destid << 22) | (hopcount << 12) | ((offset & ~0x3) >> 9));
 283
 284         data = (u8 *) priv->maint_win + offset;
 285         switch (len) {
 286         case 1:
 287                 *val = in_8((u8 *) data);
 288                 break;
 289         case 2:
 290                 *val = in_be16((u16 *) data);
 291                 break;
 292         default:
 293                 *val = in_be32((u32 *) data);
 294                 break;
 295         }
 296
 297         return 0;
 298 }
 299
 300 /**
 301  * fsl_rio_config_write - Generate a MPC85xx write maintenance transaction
 302  * @mport: RapidIO master port info
 303  * @index: ID of RapdiIO interface
 304  * @destid: Destination ID of transaction
 305  * @hopcount: Number of hops to target device
 306  * @offset: Offset into configuration space
 307  * @len: Length (in bytes) of the maintenance transaction
 308  * @val: Value to be written
 309  *
 310  * Generates an MPC85xx write maintenance transaction. Returns %0 on
 311  * success or %-EINVAL on failure.
 312  */
 313 static int
 314 fsl_rio_config_write(struct rio_mport *mport, int index, u16 destid,
 315                         u8 hopcount, u32 offset, int len, u32 val)
 316 {
 317         struct rio_priv *priv = mport->priv;
 318         u8 *data;
 319         pr_debug
 320             ("fsl_rio_config_write: index %d destid %d hopcount %d offset %8.8x len %d val %8.8x\n",
 321              index, destid, hopcount, offset, len, val);
 322         out_be32(&priv->maint_atmu_regs->rowtar,
 323                  (destid << 22) | (hopcount << 12) | ((offset & ~0x3) >> 9));
 324
 325         data = (u8 *) priv->maint_win + offset;
 326         switch (len) {
 327         case 1:
 328                 out_8((u8 *) data, val);
 329                 break;
 330         case 2:
 331                 out_be16((u16 *) data, val);
 332                 break;
 333         default:
 334                 out_be32((u32 *) data, val);
 335                 break;
 336         }
 337
 338         return 0;
 339 }
 340
 341 /**
 342  * rio_hw_add_outb_message - Add message to the MPC85xx outbound message queue
 343  * @mport: Master port with outbound message queue
 344  * @rdev: Target of outbound message
 345  * @mbox: Outbound mailbox
 346  * @buffer: Message to add to outbound queue
 347  * @len: Length of message
 348  *
 349  * Adds the @buffer message to the MPC85xx outbound message queue. Returns
 350  * %0 on success or %-EINVAL on failure.
 351  */
 352 int
 353 rio_hw_add_outb_message(struct rio_mport *mport, struct rio_dev *rdev, int mbox,
 354                         void *buffer, size_t len)
 355 {
 356         struct rio_priv *priv = mport->priv;
 357         u32 omr;
 358         struct rio_tx_desc *desc = (struct rio_tx_desc *)priv->msg_tx_ring.virt
 359                                         + priv->msg_tx_ring.tx_slot;
 360         int ret = 0;
 361
 362         pr_debug
 363             ("RIO: rio_hw_add_outb_message(): destid %4.4x mbox %d buffer %8.8x len %8.8x\n",
 364              rdev->destid, mbox, (int)buffer, len);
 365
 366         if ((len < 8) || (len > RIO_MAX_MSG_SIZE)) {
 367                 ret = -EINVAL;
 368                 goto out;
 369         }
 370
 371         /* Copy and clear rest of buffer */
 372         memcpy(priv->msg_tx_ring.virt_buffer[priv->msg_tx_ring.tx_slot], buffer,
 373                         len);
 374         if (len < (RIO_MAX_MSG_SIZE - 4))
 375                 memset(priv->msg_tx_ring.virt_buffer[priv->msg_tx_ring.tx_slot]
 376                                 + len, 0, RIO_MAX_MSG_SIZE - len);
 377
 378         switch (mport->phy_type) {
 379         case RIO_PHY_PARALLEL:
 380                 /* Set mbox field for message */
 381                 desc->dport = mbox & 0x3;
 382
 383                 /* Enable EOMI interrupt, set priority, and set destid */
 384                 desc->dattr = 0x28000000 | (rdev->destid << 2);
 385                 break;
 386         case RIO_PHY_SERIAL:
 387                 /* Set mbox field for message, and set destid */
 388                 desc->dport = (rdev->destid << 16) | (mbox & 0x3);
 389
 390                 /* Enable EOMI interrupt and priority */
 391                 desc->dattr = 0x28000000;
 392                 break;
 393         }
 394
 395         /* Set transfer size aligned to next power of 2 (in double words) */
 396         desc->dwcnt = is_power_of_2(len) ? len : 1 << get_bitmask_order(len);
 397
 398         /* Set snooping and source buffer address */
 399         desc->saddr = 0x00000004
 400                 | priv->msg_tx_ring.phys_buffer[priv->msg_tx_ring.tx_slot];
 401
 402         /* Increment enqueue pointer */
 403         omr = in_be32(&priv->msg_regs->omr);
 404         out_be32(&priv->msg_regs->omr, omr | RIO_MSG_OMR_MUI);
 405
 406         /* Go to next descriptor */
 407         if (++priv->msg_tx_ring.tx_slot == priv->msg_tx_ring.size)
 408                 priv->msg_tx_ring.tx_slot = 0;
 409
 410       out:
 411         return ret;
 412 }
 413
 414 EXPORT_SYMBOL_GPL(rio_hw_add_outb_message);
 415
 416 /**
 417  * fsl_rio_tx_handler - MPC85xx outbound message interrupt handler
 418  * @irq: Linux interrupt number
 419  * @dev_instance: Pointer to interrupt-specific data
 420  *
 421  * Handles outbound message interrupts. Executes a register outbound
 422  * mailbox event handler and acks the interrupt occurrence.
 423  */
 424 static irqreturn_t
 425 fsl_rio_tx_handler(int irq, void *dev_instance)
 426 {
 427         int osr;
 428         struct rio_mport *port = (struct rio_mport *)dev_instance;
 429         struct rio_priv *priv = port->priv;
 430
 431         osr = in_be32(&priv->msg_regs->osr);
 432
 433         if (osr & RIO_MSG_OSR_TE) {
 434                 pr_info("RIO: outbound message transmission error\n");
 435                 out_be32(&priv->msg_regs->osr, RIO_MSG_OSR_TE);
 436                 goto out;
 437         }
 438
 439         if (osr & RIO_MSG_OSR_QOI) {
 440                 pr_info("RIO: outbound message queue overflow\n");
 441                 out_be32(&priv->msg_regs->osr, RIO_MSG_OSR_QOI);
 442                 goto out;
 443         }
 444
 445         if (osr & RIO_MSG_OSR_EOMI) {
 446                 u32 dqp = in_be32(&priv->msg_regs->odqdpar);
 447                 int slot = (dqp - priv->msg_tx_ring.phys) >> 5;
 448                 port->outb_msg[0].mcback(port, priv->msg_tx_ring.dev_id, -1,
 449                                 slot);
 450
 451                 /* Ack the end-of-message interrupt */
 452                 out_be32(&priv->msg_regs->osr, RIO_MSG_OSR_EOMI);
 453         }
 454
 455       out:
 456         return IRQ_HANDLED;
 457 }
 458
 459 /**
 460  * rio_open_outb_mbox - Initialize MPC85xx outbound mailbox
 461  * @mport: Master port implementing the outbound message unit
 462  * @dev_id: Device specific pointer to pass on event
 463  * @mbox: Mailbox to open
 464  * @entries: Number of entries in the outbound mailbox ring
 465  *
 466  * Initializes buffer ring, request the outbound message interrupt,
 467  * and enables the outbound message unit. Returns %0 on success and
 468  * %-EINVAL or %-ENOMEM on failure.
 469  */
 470 int rio_open_outb_mbox(struct rio_mport *mport, void *dev_id, int mbox, int entries)
 471 {
 472         int i, j, rc = 0;
 473         struct rio_priv *priv = mport->priv;
 474
 475         if ((entries < RIO_MIN_TX_RING_SIZE) ||
 476             (entries > RIO_MAX_TX_RING_SIZE) || (!is_power_of_2(entries))) {
 477                 rc = -EINVAL;
 478                 goto out;
 479         }
 480
 481         /* Initialize shadow copy ring */
 482         priv->msg_tx_ring.dev_id = dev_id;
 483         priv->msg_tx_ring.size = entries;
 484
 485         for (i = 0; i < priv->msg_tx_ring.size; i++) {
 486                 priv->msg_tx_ring.virt_buffer[i] =
 487                         dma_alloc_coherent(NULL, RIO_MSG_BUFFER_SIZE,
 488                                 &priv->msg_tx_ring.phys_buffer[i], GFP_KERNEL);
 489                 if (!priv->msg_tx_ring.virt_buffer[i]) {
 490                         rc = -ENOMEM;
 491                         for (j = 0; j < priv->msg_tx_ring.size; j++)
 492                                 if (priv->msg_tx_ring.virt_buffer[j])
 493                                         dma_free_coherent(NULL,
 494                                                         RIO_MSG_BUFFER_SIZE,
 495                                                         priv->msg_tx_ring.
 496                                                         virt_buffer[j],
 497                                                         priv->msg_tx_ring.
 498                                                         phys_buffer[j]);
 499                         goto out;
 500                 }
 501         }
 502
 503         /* Initialize outbound message descriptor ring */
 504         priv->msg_tx_ring.virt = dma_alloc_coherent(NULL,
 505                                 priv->msg_tx_ring.size * RIO_MSG_DESC_SIZE,
 506                                 &priv->msg_tx_ring.phys, GFP_KERNEL);
 507         if (!priv->msg_tx_ring.virt) {
 508                 rc = -ENOMEM;
 509                 goto out_dma;
 510         }
 511         memset(priv->msg_tx_ring.virt, 0,
 512                         priv->msg_tx_ring.size * RIO_MSG_DESC_SIZE);
 513         priv->msg_tx_ring.tx_slot = 0;
 514
 515         /* Point dequeue/enqueue pointers at first entry in ring */
 516         out_be32(&priv->msg_regs->odqdpar, priv->msg_tx_ring.phys);
 517         out_be32(&priv->msg_regs->odqepar, priv->msg_tx_ring.phys);
 518
 519         /* Configure for snooping */
 520         out_be32(&priv->msg_regs->osar, 0x00000004);
 521
 522         /* Clear interrupt status */
 523         out_be32(&priv->msg_regs->osr, 0x000000b3);
 524
 525         /* Hook up outbound message handler */
 526         rc = request_irq(IRQ_RIO_TX(mport), fsl_rio_tx_handler, 0,
 527                          "msg_tx", (void *)mport);
 528         if (rc < 0)
 529                 goto out_irq;
 530
 531         /*
 532          * Configure outbound message unit
 533          *      Snooping
 534          *      Interrupts (all enabled, except QEIE)
 535          *      Chaining mode
 536          *      Disable
 537          */
 538         out_be32(&priv->msg_regs->omr, 0x00100220);
 539
 540         /* Set number of entries */
 541         out_be32(&priv->msg_regs->omr,
 542                  in_be32(&priv->msg_regs->omr) |
 543                  ((get_bitmask_order(entries) - 2) << 12));
 544
 545         /* Now enable the unit */
 546         out_be32(&priv->msg_regs->omr, in_be32(&priv->msg_regs->omr) | 0x1);
 547
 548       out:
 549         return rc;
 550
 551       out_irq:
 552         dma_free_coherent(NULL, priv->msg_tx_ring.size * RIO_MSG_DESC_SIZE,
 553                           priv->msg_tx_ring.virt, priv->msg_tx_ring.phys);
 554
 555       out_dma:
 556         for (i = 0; i < priv->msg_tx_ring.size; i++)
 557                 dma_free_coherent(NULL, RIO_MSG_BUFFER_SIZE,
 558                                   priv->msg_tx_ring.virt_buffer[i],
 559                                   priv->msg_tx_ring.phys_buffer[i]);
 560
 561         return rc;
 562 }
 563
 564 /**
 565  * rio_close_outb_mbox - Shut down MPC85xx outbound mailbox
 566  * @mport: Master port implementing the outbound message unit
 567  * @mbox: Mailbox to close
 568  *
 569  * Disables the outbound message unit, free all buffers, and
 570  * frees the outbound message interrupt.
 571  */
 572 void rio_close_outb_mbox(struct rio_mport *mport, int mbox)
 573 {
 574         struct rio_priv *priv = mport->priv;
 575         /* Disable inbound message unit */
 576         out_be32(&priv->msg_regs->omr, 0);
 577
 578         /* Free ring */
 579         dma_free_coherent(NULL, priv->msg_tx_ring.size * RIO_MSG_DESC_SIZE,
 580                           priv->msg_tx_ring.virt, priv->msg_tx_ring.phys);
 581
 582         /* Free interrupt */
 583         free_irq(IRQ_RIO_TX(mport), (void *)mport);
 584 }
 585
 586 /**
 587  * fsl_rio_rx_handler - MPC85xx inbound message interrupt handler
 588  * @irq: Linux interrupt number
 589  * @dev_instance: Pointer to interrupt-specific data
 590  *
 591  * Handles inbound message interrupts. Executes a registered inbound
 592  * mailbox event handler and acks the interrupt occurrence.
 593  */
 594 static irqreturn_t
 595 fsl_rio_rx_handler(int irq, void *dev_instance)
 596 {
 597         int isr;
 598         struct rio_mport *port = (struct rio_mport *)dev_instance;
 599         struct rio_priv *priv = port->priv;
 600
 601         isr = in_be32(&priv->msg_regs->isr);
 602
 603         if (isr & RIO_MSG_ISR_TE) {
 604                 pr_info("RIO: inbound message reception error\n");
 605                 out_be32((void *)&priv->msg_regs->isr, RIO_MSG_ISR_TE);
 606                 goto out;
 607         }
 608
 609         /* XXX Need to check/dispatch until queue empty */
 610         if (isr & RIO_MSG_ISR_DIQI) {
 611                 /*
 612                  * We implement *only* mailbox 0, but can receive messages
 613                  * for any mailbox/letter to that mailbox destination. So,
 614                  * make the callback with an unknown/invalid mailbox number
 615                  * argument.
 616                  */
 617                 port->inb_msg[0].mcback(port, priv->msg_rx_ring.dev_id, -1, -1);
 618
 619                 /* Ack the queueing interrupt */
 620                 out_be32(&priv->msg_regs->isr, RIO_MSG_ISR_DIQI);
 621         }
 622
 623       out:
 624         return IRQ_HANDLED;
 625 }
 626
 627 /**
 628  * rio_open_inb_mbox - Initialize MPC85xx inbound mailbox
 629  * @mport: Master port implementing the inbound message unit
 630  * @dev_id: Device specific pointer to pass on event
 631  * @mbox: Mailbox to open
 632  * @entries: Number of entries in the inbound mailbox ring
 633  *
 634  * Initializes buffer ring, request the inbound message interrupt,
 635  * and enables the inbound message unit. Returns %0 on success
 636  * and %-EINVAL or %-ENOMEM on failure.
 637  */
 638 int rio_open_inb_mbox(struct rio_mport *mport, void *dev_id, int mbox, int entries)
 639 {
 640         int i, rc = 0;
 641         struct rio_priv *priv = mport->priv;
 642
 643         if ((entries < RIO_MIN_RX_RING_SIZE) ||
 644             (entries > RIO_MAX_RX_RING_SIZE) || (!is_power_of_2(entries))) {
 645                 rc = -EINVAL;
 646                 goto out;
 647         }
 648
 649         /* Initialize client buffer ring */
 650         priv->msg_rx_ring.dev_id = dev_id;
 651         priv->msg_rx_ring.size = entries;
 652         priv->msg_rx_ring.rx_slot = 0;
 653         for (i = 0; i < priv->msg_rx_ring.size; i++)
 654                 priv->msg_rx_ring.virt_buffer[i] = NULL;
 655
 656         /* Initialize inbound message ring */
 657         priv->msg_rx_ring.virt = dma_alloc_coherent(NULL,
 658                                 priv->msg_rx_ring.size * RIO_MAX_MSG_SIZE,
 659                                 &priv->msg_rx_ring.phys, GFP_KERNEL);
 660         if (!priv->msg_rx_ring.virt) {
 661                 rc = -ENOMEM;
 662                 goto out;
 663         }
 664
 665         /* Point dequeue/enqueue pointers at first entry in ring */
 666         out_be32(&priv->msg_regs->ifqdpar, (u32) priv->msg_rx_ring.phys);
 667         out_be32(&priv->msg_regs->ifqepar, (u32) priv->msg_rx_ring.phys);
 668
 669         /* Clear interrupt status */
 670         out_be32(&priv->msg_regs->isr, 0x00000091);
 671
 672         /* Hook up inbound message handler */
 673         rc = request_irq(IRQ_RIO_RX(mport), fsl_rio_rx_handler, 0,
 674                          "msg_rx", (void *)mport);
 675         if (rc < 0) {
 676                 dma_free_coherent(NULL, RIO_MSG_BUFFER_SIZE,
 677                                   priv->msg_tx_ring.virt_buffer[i],
 678                                   priv->msg_tx_ring.phys_buffer[i]);
 679                 goto out;
 680         }
 681
 682         /*
 683          * Configure inbound message unit:
 684          *      Snooping
 685          *      4KB max message size
 686          *      Unmask all interrupt sources
 687          *      Disable
 688          */
 689         out_be32(&priv->msg_regs->imr, 0x001b0060);
 690
 691         /* Set number of queue entries */
 692         setbits32(&priv->msg_regs->imr, (get_bitmask_order(entries) - 2) << 12);
 693
 694         /* Now enable the unit */
 695         setbits32(&priv->msg_regs->imr, 0x1);
 696
 697       out:
 698         return rc;
 699 }
 700
 701 /**
 702  * rio_close_inb_mbox - Shut down MPC85xx inbound mailbox
 703  * @mport: Master port implementing the inbound message unit
 704  * @mbox: Mailbox to close
 705  *
 706  * Disables the inbound message unit, free all buffers, and
 707  * frees the inbound message interrupt.
 708  */
 709 void rio_close_inb_mbox(struct rio_mport *mport, int mbox)
 710 {
 711         struct rio_priv *priv = mport->priv;
 712         /* Disable inbound message unit */
 713         out_be32(&priv->msg_regs->imr, 0);
 714
 715         /* Free ring */
 716         dma_free_coherent(NULL, priv->msg_rx_ring.size * RIO_MAX_MSG_SIZE,
 717                           priv->msg_rx_ring.virt, priv->msg_rx_ring.phys);
 718
 719         /* Free interrupt */
 720         free_irq(IRQ_RIO_RX(mport), (void *)mport);
 721 }
 722
 723 /**
 724  * rio_hw_add_inb_buffer - Add buffer to the MPC85xx inbound message queue
 725  * @mport: Master port implementing the inbound message unit
 726  * @mbox: Inbound mailbox number
 727  * @buf: Buffer to add to inbound queue
 728  *
 729  * Adds the @buf buffer to the MPC85xx inbound message queue. Returns
 730  * %0 on success or %-EINVAL on failure.
 731  */
 732 int rio_hw_add_inb_buffer(struct rio_mport *mport, int mbox, void *buf)
 733 {
 734         int rc = 0;
 735         struct rio_priv *priv = mport->priv;
 736
 737         pr_debug("RIO: rio_hw_add_inb_buffer(), msg_rx_ring.rx_slot %d\n",
 738                  priv->msg_rx_ring.rx_slot);
 739
 740         if (priv->msg_rx_ring.virt_buffer[priv->msg_rx_ring.rx_slot]) {
 741                 printk(KERN_ERR
 742                        "RIO: error adding inbound buffer %d, buffer exists\n",
 743                        priv->msg_rx_ring.rx_slot);
 744                 rc = -EINVAL;
 745                 goto out;
 746         }
 747
 748         priv->msg_rx_ring.virt_buffer[priv->msg_rx_ring.rx_slot] = buf;
 749         if (++priv->msg_rx_ring.rx_slot == priv->msg_rx_ring.size)
 750                 priv->msg_rx_ring.rx_slot = 0;
 751
 752       out:
 753         return rc;
 754 }
 755
 756 EXPORT_SYMBOL_GPL(rio_hw_add_inb_buffer);
 757
 758 /**
 759  * rio_hw_get_inb_message - Fetch inbound message from the MPC85xx message unit
 760  * @mport: Master port implementing the inbound message unit
 761  * @mbox: Inbound mailbox number
 762  *
 763  * Gets the next available inbound message from the inbound message queue.
 764  * A pointer to the message is returned on success or NULL on failure.
 765  */
 766 void *rio_hw_get_inb_message(struct rio_mport *mport, int mbox)
 767 {
 768         struct rio_priv *priv = mport->priv;
 769         u32 phys_buf, virt_buf;
 770         void *buf = NULL;
 771         int buf_idx;
 772
 773         phys_buf = in_be32(&priv->msg_regs->ifqdpar);
 774
 775         /* If no more messages, then bail out */
 776         if (phys_buf == in_be32(&priv->msg_regs->ifqepar))
 777                 goto out2;
 778
 779         virt_buf = (u32) priv->msg_rx_ring.virt + (phys_buf
 780                                                 - priv->msg_rx_ring.phys);
 781         buf_idx = (phys_buf - priv->msg_rx_ring.phys) / RIO_MAX_MSG_SIZE;
 782         buf = priv->msg_rx_ring.virt_buffer[buf_idx];
 783
 784         if (!buf) {
 785                 printk(KERN_ERR
 786                        "RIO: inbound message copy failed, no buffers\n");
 787                 goto out1;
 788         }
 789
 790         /* Copy max message size, caller is expected to allocate that big */
 791         memcpy(buf, (void *)virt_buf, RIO_MAX_MSG_SIZE);
 792
 793         /* Clear the available buffer */
 794         priv->msg_rx_ring.virt_buffer[buf_idx] = NULL;
 795
 796       out1:
 797         setbits32(&priv->msg_regs->imr, RIO_MSG_IMR_MI);
 798
 799       out2:
 800         return buf;
 801 }
 802
 803 EXPORT_SYMBOL_GPL(rio_hw_get_inb_message);
 804
 805 /**
 806  * fsl_rio_dbell_handler - MPC85xx doorbell interrupt handler
 807  * @irq: Linux interrupt number
 808  * @dev_instance: Pointer to interrupt-specific data
 809  *
 810  * Handles doorbell interrupts. Parses a list of registered
 811  * doorbell event handlers and executes a matching event handler.
 812  */
 813 static irqreturn_t
 814 fsl_rio_dbell_handler(int irq, void *dev_instance)
 815 {
 816         int dsr;
 817         struct rio_mport *port = (struct rio_mport *)dev_instance;
 818         struct rio_priv *priv = port->priv;
 819
 820         dsr = in_be32(&priv->msg_regs->dsr);
 821
 822         if (dsr & DOORBELL_DSR_TE) {
 823                 pr_info("RIO: doorbell reception error\n");
 824                 out_be32(&priv->msg_regs->dsr, DOORBELL_DSR_TE);
 825                 goto out;
 826         }
 827
 828         if (dsr & DOORBELL_DSR_QFI) {
 829                 pr_info("RIO: doorbell queue full\n");
 830                 out_be32(&priv->msg_regs->dsr, DOORBELL_DSR_QFI);
 831                 goto out;
 832         }
 833
 834         /* XXX Need to check/dispatch until queue empty */
 835         if (dsr & DOORBELL_DSR_DIQI) {
 836                 u32 dmsg =
 837                     (u32) priv->dbell_ring.virt +
 838                     (in_be32(&priv->msg_regs->dqdpar) & 0xfff);
 839                 struct rio_dbell *dbell;
 840                 int found = 0;
 841
 842                 pr_debug
 843                     ("RIO: processing doorbell, sid %2.2x tid %2.2x info %4.4x\n",
 844                      DBELL_SID(dmsg), DBELL_TID(dmsg), DBELL_INF(dmsg));
 845
 846                 list_for_each_entry(dbell, &port->dbells, node) {
 847                         if ((dbell->res->start <= DBELL_INF(dmsg)) &&
 848                             (dbell->res->end >= DBELL_INF(dmsg))) {
 849                                 found = 1;
 850                                 break;
 851                         }
 852                 }
 853                 if (found) {
 854                         dbell->dinb(port, dbell->dev_id, DBELL_SID(dmsg), DBELL_TID(dmsg),
 855                                     DBELL_INF(dmsg));
 856                 } else {
 857                         pr_debug
 858                             ("RIO: spurious doorbell, sid %2.2x tid %2.2x info %4.4x\n",
 859                              DBELL_SID(dmsg), DBELL_TID(dmsg), DBELL_INF(dmsg));
 860                 }
 861                 setbits32(&priv->msg_regs->dmr, DOORBELL_DMR_DI);
 862                 out_be32(&priv->msg_regs->dsr, DOORBELL_DSR_DIQI);
 863         }
 864
 865       out:
 866         return IRQ_HANDLED;
 867 }
 868
 869 /**
 870  * fsl_rio_doorbell_init - MPC85xx doorbell interface init
 871  * @mport: Master port implementing the inbound doorbell unit
 872  *
 873  * Initializes doorbell unit hardware and inbound DMA buffer
 874  * ring. Called from fsl_rio_setup(). Returns %0 on success
 875  * or %-ENOMEM on failure.
 876  */
 877 static int fsl_rio_doorbell_init(struct rio_mport *mport)
 878 {
 879         struct rio_priv *priv = mport->priv;
 880         int rc = 0;
 881
 882         /* Map outbound doorbell window immediately after maintenance window */
 883         priv->dbell_win = ioremap(mport->iores.start + RIO_MAINT_WIN_SIZE,
 884                             RIO_DBELL_WIN_SIZE);
 885         if (!priv->dbell_win) {
 886                 printk(KERN_ERR
 887                        "RIO: unable to map outbound doorbell window\n");
 888                 rc = -ENOMEM;
 889                 goto out;
 890         }
 891
 892         /* Initialize inbound doorbells */
 893         priv->dbell_ring.virt = dma_alloc_coherent(NULL, 512 *
 894                     DOORBELL_MESSAGE_SIZE, &priv->dbell_ring.phys, GFP_KERNEL);
 895         if (!priv->dbell_ring.virt) {
 896                 printk(KERN_ERR "RIO: unable allocate inbound doorbell ring\n");
 897                 rc = -ENOMEM;
 898                 iounmap(priv->dbell_win);
 899                 goto out;
 900         }
 901
 902         /* Point dequeue/enqueue pointers at first entry in ring */
 903         out_be32(&priv->msg_regs->dqdpar, (u32) priv->dbell_ring.phys);
 904         out_be32(&priv->msg_regs->dqepar, (u32) priv->dbell_ring.phys);
 905
 906         /* Clear interrupt status */
 907         out_be32(&priv->msg_regs->dsr, 0x00000091);
 908
 909         /* Hook up doorbell handler */
 910         rc = request_irq(IRQ_RIO_BELL(mport), fsl_rio_dbell_handler, 0,
 911                          "dbell_rx", (void *)mport);
 912         if (rc < 0) {
 913                 iounmap(priv->dbell_win);
 914                 dma_free_coherent(NULL, 512 * DOORBELL_MESSAGE_SIZE,
 915                                   priv->dbell_ring.virt, priv->dbell_ring.phys);
 916                 printk(KERN_ERR
 917                        "MPC85xx RIO: unable to request inbound doorbell irq");
 918                 goto out;
 919         }
 920
 921         /* Configure doorbells for snooping, 512 entries, and enable */
 922         out_be32(&priv->msg_regs->dmr, 0x00108161);
 923
 924       out:
 925         return rc;
 926 }
 927
 928 static char *cmdline = NULL;
 929
 930 static int fsl_rio_get_hdid(int index)
 931 {
 932         /* XXX Need to parse multiple entries in some format */
 933         if (!cmdline)
 934                 return -1;
 935
 936         return simple_strtol(cmdline, NULL, 0);
 937 }
 938
 939 static int fsl_rio_get_cmdline(char *s)
 940 {
 941         if (!s)
 942                 return 0;
 943
 944         cmdline = s;
 945         return 1;
 946 }
 947
 948 __setup("riohdid=", fsl_rio_get_cmdline);
 949
 950 static inline void fsl_rio_info(struct device *dev, u32 ccsr)
 951 {
 952         const char *str;
 953         if (ccsr & 1) {
 954                 /* Serial phy */
 955                 switch (ccsr >> 30) {
 956                 case 0:
 957                         str = "1";
 958                         break;
 959                 case 1:
 960                         str = "4";
 961                         break;
 962                 default:
 963                         str = "Unknown";
 964                         break;;
 965                 }
 966                 dev_info(dev, "Hardware port width: %s\n", str);
 967
 968                 switch ((ccsr >> 27) & 7) {
 969                 case 0:
 970                         str = "Single-lane 0";
 971                         break;
 972                 case 1:
 973                         str = "Single-lane 2";
 974                         break;
 975                 case 2:
 976                         str = "Four-lane";
 977                         break;
 978                 default:
 979                         str = "Unknown";
 980                         break;
 981                 }
 982                 dev_info(dev, "Training connection status: %s\n", str);
 983         } else {
 984                 /* Parallel phy */
 985                 if (!(ccsr & 0x80000000))
 986                         dev_info(dev, "Output port operating in 8-bit mode\n");
 987                 if (!(ccsr & 0x08000000))
 988                         dev_info(dev, "Input port operating in 8-bit mode\n");
 989         }
 990 }
 991
 992 /**
 993  * fsl_rio_setup - Setup Freescale PowerPC RapidIO interface
 994  * @dev: of_device pointer
 995  *
 996  * Initializes MPC85xx RapidIO hardware interface, configures
 997  * master port with system-specific info, and registers the
 998  * master port with the RapidIO subsystem.
 999  */
1000 int fsl_rio_setup(struct of_device *dev)
1001 {
1002         struct rio_ops *ops;
1003         struct rio_mport *port;
1004         struct rio_priv *priv;
1005         int rc = 0;
1006         const u32 *dt_range, *cell;
1007         struct resource regs;
1008         int rlen;
1009         u32 ccsr;
1010         u64 law_start, law_size;
1011         int paw, aw, sw;
1012
1013         if (!dev->node) {
1014                 dev_err(&dev->dev, "Device OF-Node is NULL");
1015                 return -EFAULT;
1016         }
1017
1018         rc = of_address_to_resource(dev->node, 0, &regs);
1019         if (rc) {
1020                 dev_err(&dev->dev, "Can't get %s property 'reg'\n",
1021                                 dev->node->full_name);
1022                 return -EFAULT;
1023         }
1024         dev_info(&dev->dev, "Of-device full name %s\n", dev->node->full_name);
1025         dev_info(&dev->dev, "Regs start 0x%08x size 0x%08x\n",  regs.start,
1026                                                 regs.end - regs.start + 1);
1027
1028         dt_range = of_get_property(dev->node, "ranges", &rlen);
1029         if (!dt_range) {
1030                 dev_err(&dev->dev, "Can't get %s property 'ranges'\n",
1031                                 dev->node->full_name);
1032                 return -EFAULT;
1033         }
1034
1035         /* Get node address wide */
1036         cell = of_get_property(dev->node, "#address-cells", NULL);
1037         if (cell)
1038                 aw = *cell;
1039         else
1040                 aw = of_n_addr_cells(dev->node);
1041         /* Get node size wide */
1042         cell = of_get_property(dev->node, "#size-cells", NULL);
1043         if (cell)
1044                 sw = *cell;
1045         else
1046                 sw = of_n_size_cells(dev->node);
1047         /* Get parent address wide wide */
1048         paw = of_n_addr_cells(dev->node);
1049
1050         law_start = of_read_number(dt_range + aw, paw);
1051         law_size = of_read_number(dt_range + aw + paw, sw);
1052
1053         dev_info(&dev->dev, "LAW start 0x%016llx, size 0x%016llx.\n",
1054                         law_start, law_size);
1055
1056         ops = kmalloc(sizeof(struct rio_ops), GFP_KERNEL);
1057         ops->lcread = fsl_local_config_read;
1058         ops->lcwrite = fsl_local_config_write;
1059         ops->cread = fsl_rio_config_read;
1060         ops->cwrite = fsl_rio_config_write;
1061         ops->dsend = fsl_rio_doorbell_send;
1062
1063         port = kzalloc(sizeof(struct rio_mport), GFP_KERNEL);
1064         port->id = 0;
1065         port->index = 0;
1066
1067         priv = kzalloc(sizeof(struct rio_priv), GFP_KERNEL);
1068         if (!priv) {
1069                 printk(KERN_ERR "Can't alloc memory for 'priv'\n");
1070                 rc = -ENOMEM;
1071                 goto err;
1072         }
1073
1074         INIT_LIST_HEAD(&port->dbells);
1075         port->iores.start = law_start;
1076         port->iores.end = law_start + law_size;
1077         port->iores.flags = IORESOURCE_MEM;
1078
1079         priv->bellirq = irq_of_parse_and_map(dev->node, 2);
1080         priv->txirq = irq_of_parse_and_map(dev->node, 3);
1081         priv->rxirq = irq_of_parse_and_map(dev->node, 4);
1082         dev_info(&dev->dev, "bellirq: %d, txirq: %d, rxirq %d\n", priv->bellirq,
1083                                 priv->txirq, priv->rxirq);
1084
1085         rio_init_dbell_res(&port->riores[RIO_DOORBELL_RESOURCE], 0, 0xffff);
1086         rio_init_mbox_res(&port->riores[RIO_INB_MBOX_RESOURCE], 0, 0);
1087         rio_init_mbox_res(&port->riores[RIO_OUTB_MBOX_RESOURCE], 0, 0);
1088         strcpy(port->name, "RIO0 mport");
1089
1090         port->ops = ops;
1091         port->host_deviceid = fsl_rio_get_hdid(port->id);
1092
1093         port->priv = priv;
1094         rio_register_mport(port);
1095
1096         priv->regs_win = ioremap(regs.start, regs.end - regs.start + 1);
1097
1098         /* Probe the master port phy type */
1099         ccsr = in_be32(priv->regs_win + RIO_CCSR);
1100         port->phy_type = (ccsr & 1) ? RIO_PHY_SERIAL : RIO_PHY_PARALLEL;
1101         dev_info(&dev->dev, "RapidIO PHY type: %s\n",
1102                         (port->phy_type == RIO_PHY_PARALLEL) ? "parallel" :
1103                         ((port->phy_type == RIO_PHY_SERIAL) ? "serial" :
1104                          "unknown"));
1105         /* Checking the port training status */
1106         if (in_be32((priv->regs_win + RIO_ESCSR)) & 1) {
1107                 dev_err(&dev->dev, "Port is not ready. "
1108                                    "Try to restart connection...\n");
1109                 switch (port->phy_type) {
1110                 case RIO_PHY_SERIAL:
1111                         /* Disable ports */
1112                         out_be32(priv->regs_win + RIO_CCSR, 0);
1113                         /* Set 1x lane */
1114                         setbits32(priv->regs_win + RIO_CCSR, 0x02000000);
1115                         /* Enable ports */
1116                         setbits32(priv->regs_win + RIO_CCSR, 0x00600000);
1117                         break;
1118                 case RIO_PHY_PARALLEL:
1119                         /* Disable ports */
1120                         out_be32(priv->regs_win + RIO_CCSR, 0x22000000);
1121                         /* Enable ports */
1122                         out_be32(priv->regs_win + RIO_CCSR, 0x44000000);
1123                         break;
1124                 }
1125                 msleep(100);
1126                 if (in_be32((priv->regs_win + RIO_ESCSR)) & 1) {
1127                         dev_err(&dev->dev, "Port restart failed.\n");
1128                         rc = -ENOLINK;
1129                         goto err;
1130                 }
1131                 dev_info(&dev->dev, "Port restart success!\n");
1132         }
1133         fsl_rio_info(&dev->dev, ccsr);
1134
1135         port->sys_size = (in_be32((priv->regs_win + RIO_PEF_CAR))
1136                                         & RIO_PEF_CTLS) >> 4;
1137         dev_info(&dev->dev, "RapidIO Common Transport System size: %d\n",
1138                         port->sys_size ? 65536 : 256);
1139
1140         priv->atmu_regs = (struct rio_atmu_regs *)(priv->regs_win
1141                                         + RIO_ATMU_REGS_OFFSET);
1142         priv->maint_atmu_regs = priv->atmu_regs + 1;
1143         priv->dbell_atmu_regs = priv->atmu_regs + 2;
1144         priv->msg_regs = (struct rio_msg_regs *)(priv->regs_win +
1145                                 ((port->phy_type == RIO_PHY_SERIAL) ?
1146                                 RIO_S_MSG_REGS_OFFSET : RIO_P_MSG_REGS_OFFSET));
1147
1148         /* Set to receive any dist ID for serial RapidIO controller. */
1149         if (port->phy_type == RIO_PHY_SERIAL)
1150                 out_be32((priv->regs_win + RIO_ISR_AACR), RIO_ISR_AACR_AA);
1151
1152         /* Configure maintenance transaction window */
1153         out_be32(&priv->maint_atmu_regs->rowbar, 0x000c0000);
1154         out_be32(&priv->maint_atmu_regs->rowar, 0x80077015);
1155
1156         priv->maint_win = ioremap(law_start, RIO_MAINT_WIN_SIZE);
1157
1158         /* Configure outbound doorbell window */
1159         out_be32(&priv->dbell_atmu_regs->rowbar, 0x000c0400);
1160         out_be32(&priv->dbell_atmu_regs->rowar, 0x8004200b);
1161         fsl_rio_doorbell_init(port);
1162
1163         return 0;
1164 err:
1165         if (priv)
1166                 iounmap(priv->regs_win);
1167         kfree(ops);
1168         kfree(priv);
1169         kfree(port);
1170         return rc;
1171 }
1172
1173 /* The probe function for RapidIO peer-to-peer network.
1174  */
1175 static int __devinit fsl_of_rio_rpn_probe(struct of_device *dev,
1176                                      const struct of_device_id *match)
1177 {
1178         int rc;
1179         printk(KERN_INFO "Setting up RapidIO peer-to-peer network %s\n",
1180                         dev->node->full_name);
1181
1182         rc = fsl_rio_setup(dev);
1183         if (rc)
1184                 goto out;
1185
1186         /* Enumerate all registered ports */
1187         rc = rio_init_mports();
1188 out:
1189         return rc;
1190 };
1191
1192 static const struct of_device_id fsl_of_rio_rpn_ids[] = {
1193         {
1194                 .compatible = "fsl,rapidio-delta",
1195         },
1196         {},
1197 };
1198
1199 static struct of_platform_driver fsl_of_rio_rpn_driver = {
1200         .name = "fsl-of-rio",
1201         .match_table = fsl_of_rio_rpn_ids,
1202         .probe = fsl_of_rio_rpn_probe,
1203 };
1204
1205 static __init int fsl_of_rio_rpn_init(void)
1206 {
1207         return of_register_platform_driver(&fsl_of_rio_rpn_driver);
1208 }
1209
1210 subsys_initcall(fsl_of_rio_rpn_init);