| blob | 321bda2de2cb8a40ab0600bb75da4676556edda3 |
1 /*
2 * PowerPC version
3 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
4 * Rewritten by Cort Dougan (cort@cs.nmt.edu) for PReP
5 * Copyright (C) 1996 Cort Dougan <cort@cs.nmt.edu>
6 * Low-level exception handlers and MMU support
7 * rewritten by Paul Mackerras.
8 * Copyright (C) 1996 Paul Mackerras.
9 * MPC8xx modifications by Dan Malek
10 * Copyright (C) 1997 Dan Malek (dmalek@jlc.net).
11 *
12 * This file contains low-level support and setup for PowerPC 8xx
13 * embedded processors, including trap and interrupt dispatch.
14 *
15 * This program is free software; you can redistribute it and/or
16 * modify it under the terms of the GNU General Public License
17 * as published by the Free Software Foundation; either version
18 * 2 of the License, or (at your option) any later version.
19 *
20 */
22 #include <asm/processor.h>
23 #include <asm/page.h>
24 #include <asm/mmu.h>
25 #include <asm/cache.h>
26 #include <asm/pgtable.h>
27 #include <asm/cputable.h>
28 #include <asm/thread_info.h>
29 #include <asm/ppc_asm.h>
30 #include <asm/asm-offsets.h>
32 /* Macro to make the code more readable. */
33 #ifdef CONFIG_8xx_CPU6
34 #define DO_8xx_CPU6(val, reg) \
35 li reg, val; \
36 stw reg, 12(r0); \
37 lwz reg, 12(r0);
38 #else
39 #define DO_8xx_CPU6(val, reg)
40 #endif
41 .text
42 .globl _stext
43 _stext:
44 .text
45 .globl _start
46 _start:
48 /* MPC8xx
49 * This port was done on an MBX board with an 860. Right now I only
50 * support an ELF compressed (zImage) boot from EPPC-Bug because the
51 * code there loads up some registers before calling us:
52 * r3: ptr to board info data
53 * r4: initrd_start or if no initrd then 0
54 * r5: initrd_end - unused if r4 is 0
55 * r6: Start of command line string
56 * r7: End of command line string
57 *
58 * I decided to use conditional compilation instead of checking PVR and
59 * adding more processor specific branches around code I don't need.
60 * Since this is an embedded processor, I also appreciate any memory
61 * savings I can get.
62 *
63 * The MPC8xx does not have any BATs, but it supports large page sizes.
64 * We first initialize the MMU to support 8M byte pages, then load one
65 * entry into each of the instruction and data TLBs to map the first
66 * 8M 1:1. I also mapped an additional I/O space 1:1 so we can get to
67 * the "internal" processor registers before MMU_init is called.
68 *
69 * The TLB code currently contains a major hack. Since I use the condition
70 * code register, I have to save and restore it. I am out of registers, so
71 * I just store it in memory location 0 (the TLB handlers are not reentrant).
72 * To avoid making any decisions, I need to use the "segment" valid bit
73 * in the first level table, but that would require many changes to the
74 * Linux page directory/table functions that I don't want to do right now.
75 *
76 * I used to use SPRG2 for a temporary register in the TLB handler, but it
77 * has since been put to other uses. I now use a hack to save a register
78 * and the CCR at memory location 0.....Someday I'll fix this.....
79 * -- Dan
80 */
81 .globl __start
82 __start:
83 mr r31,r3 /* save parameters */
84 mr r30,r4
85 mr r29,r5
86 mr r28,r6
87 mr r27,r7
89 /* We have to turn on the MMU right away so we get cache modes
90 * set correctly.
91 */
92 bl initial_mmu
94 /* We now have the lower 8 Meg mapped into TLB entries, and the caches
95 * ready to work.
96 */
98 turn_on_mmu:
99 mfmsr r0
100 ori r0,r0,MSR_DR|MSR_IR
101 mtspr SPRN_SRR1,r0
102 lis r0,start_here@h
103 ori r0,r0,start_here@l
104 mtspr SPRN_SRR0,r0
105 SYNC
106 rfi /* enables MMU */
108 /*
109 * Exception entry code. This code runs with address translation
110 * turned off, i.e. using physical addresses.
111 * We assume sprg3 has the physical address of the current
112 * task's thread_struct.
113 */
114 #define EXCEPTION_PROLOG \
115 mtspr SPRN_SPRG0,r10; \
116 mtspr SPRN_SPRG1,r11; \
117 mfcr r10; \
118 EXCEPTION_PROLOG_1; \
119 EXCEPTION_PROLOG_2
121 #define EXCEPTION_PROLOG_1 \
122 mfspr r11,SPRN_SRR1; /* check whether user or kernel */ \
123 andi. r11,r11,MSR_PR; \
124 tophys(r11,r1); /* use tophys(r1) if kernel */ \
125 beq 1f; \
126 mfspr r11,SPRN_SPRG3; \
127 lwz r11,THREAD_INFO-THREAD(r11); \
128 addi r11,r11,THREAD_SIZE; \
129 tophys(r11,r11); \
130 1: subi r11,r11,INT_FRAME_SIZE /* alloc exc. frame */
133 #define EXCEPTION_PROLOG_2 \
134 CLR_TOP32(r11); \
135 stw r10,_CCR(r11); /* save registers */ \
136 stw r12,GPR12(r11); \
137 stw r9,GPR9(r11); \
138 mfspr r10,SPRN_SPRG0; \
139 stw r10,GPR10(r11); \
140 mfspr r12,SPRN_SPRG1; \
141 stw r12,GPR11(r11); \
142 mflr r10; \
143 stw r10,_LINK(r11); \
144 mfspr r12,SPRN_SRR0; \
145 mfspr r9,SPRN_SRR1; \
146 stw r1,GPR1(r11); \
147 stw r1,0(r11); \
148 tovirt(r1,r11); /* set new kernel sp */ \
149 li r10,MSR_KERNEL & ~(MSR_IR|MSR_DR); /* can take exceptions */ \
150 MTMSRD(r10); /* (except for mach check in rtas) */ \
151 stw r0,GPR0(r11); \
152 SAVE_4GPRS(3, r11); \
153 SAVE_2GPRS(7, r11)
155 /*
156 * Note: code which follows this uses cr0.eq (set if from kernel),
157 * r11, r12 (SRR0), and r9 (SRR1).
158 *
159 * Note2: once we have set r1 we are in a position to take exceptions
160 * again, and we could thus set MSR:RI at that point.
161 */
163 /*
164 * Exception vectors.
165 */
166 #define EXCEPTION(n, label, hdlr, xfer) \
167 . = n; \
168 label: \
169 EXCEPTION_PROLOG; \
170 addi r3,r1,STACK_FRAME_OVERHEAD; \
171 xfer(n, hdlr)
173 #define EXC_XFER_TEMPLATE(n, hdlr, trap, copyee, tfer, ret) \
174 li r10,trap; \
175 stw r10,TRAP(r11); \
176 li r10,MSR_KERNEL; \
177 copyee(r10, r9); \
178 bl tfer; \
179 i##n: \
180 .long hdlr; \
181 .long ret
183 #define COPY_EE(d, s) rlwimi d,s,0,16,16
184 #define NOCOPY(d, s)
186 #define EXC_XFER_STD(n, hdlr) \
187 EXC_XFER_TEMPLATE(n, hdlr, n, NOCOPY, transfer_to_handler_full, \
188 ret_from_except_full)
190 #define EXC_XFER_LITE(n, hdlr) \
191 EXC_XFER_TEMPLATE(n, hdlr, n+1, NOCOPY, transfer_to_handler, \
192 ret_from_except)
194 #define EXC_XFER_EE(n, hdlr) \
195 EXC_XFER_TEMPLATE(n, hdlr, n, COPY_EE, transfer_to_handler_full, \
196 ret_from_except_full)
198 #define EXC_XFER_EE_LITE(n, hdlr) \
199 EXC_XFER_TEMPLATE(n, hdlr, n+1, COPY_EE, transfer_to_handler, \
200 ret_from_except)
202 /* System reset */
203 EXCEPTION(0x100, Reset, unknown_exception, EXC_XFER_STD)
205 /* Machine check */
206 . = 0x200
207 MachineCheck:
208 EXCEPTION_PROLOG
209 mfspr r4,SPRN_DAR
210 stw r4,_DAR(r11)
211 mfspr r5,SPRN_DSISR
212 stw r5,_DSISR(r11)
213 addi r3,r1,STACK_FRAME_OVERHEAD
214 EXC_XFER_STD(0x200, machine_check_exception)
216 /* Data access exception.
217 * This is "never generated" by the MPC8xx. We jump to it for other
218 * translation errors.
219 */
220 . = 0x300
221 DataAccess:
222 EXCEPTION_PROLOG
223 mfspr r10,SPRN_DSISR
224 stw r10,_DSISR(r11)
225 mr r5,r10
226 mfspr r4,SPRN_DAR
227 EXC_XFER_EE_LITE(0x300, handle_page_fault)
229 /* Instruction access exception.
230 * This is "never generated" by the MPC8xx. We jump to it for other
231 * translation errors.
232 */
233 . = 0x400
234 InstructionAccess:
235 EXCEPTION_PROLOG
236 mr r4,r12
237 mr r5,r9
238 EXC_XFER_EE_LITE(0x400, handle_page_fault)
240 /* External interrupt */
241 EXCEPTION(0x500, HardwareInterrupt, do_IRQ, EXC_XFER_LITE)
243 /* Alignment exception */
244 . = 0x600
245 Alignment:
246 EXCEPTION_PROLOG
247 mfspr r4,SPRN_DAR
248 stw r4,_DAR(r11)
249 mfspr r5,SPRN_DSISR
250 stw r5,_DSISR(r11)
251 addi r3,r1,STACK_FRAME_OVERHEAD
252 EXC_XFER_EE(0x600, alignment_exception)
254 /* Program check exception */
255 EXCEPTION(0x700, ProgramCheck, program_check_exception, EXC_XFER_STD)
257 /* No FPU on MPC8xx. This exception is not supposed to happen.
258 */
259 EXCEPTION(0x800, FPUnavailable, unknown_exception, EXC_XFER_STD)
261 /* Decrementer */
262 EXCEPTION(0x900, Decrementer, timer_interrupt, EXC_XFER_LITE)
264 EXCEPTION(0xa00, Trap_0a, unknown_exception, EXC_XFER_EE)
265 EXCEPTION(0xb00, Trap_0b, unknown_exception, EXC_XFER_EE)
267 /* System call */
268 . = 0xc00
269 SystemCall:
270 EXCEPTION_PROLOG
271 EXC_XFER_EE_LITE(0xc00, DoSyscall)
273 /* Single step - not used on 601 */
274 EXCEPTION(0xd00, SingleStep, single_step_exception, EXC_XFER_STD)
275 EXCEPTION(0xe00, Trap_0e, unknown_exception, EXC_XFER_EE)
276 EXCEPTION(0xf00, Trap_0f, unknown_exception, EXC_XFER_EE)
278 /* On the MPC8xx, this is a software emulation interrupt. It occurs
279 * for all unimplemented and illegal instructions.
280 */
281 EXCEPTION(0x1000, SoftEmu, SoftwareEmulation, EXC_XFER_STD)
283 . = 0x1100
284 /*
285 * For the MPC8xx, this is a software tablewalk to load the instruction
286 * TLB. It is modelled after the example in the Motorola manual. The task
287 * switch loads the M_TWB register with the pointer to the first level table.
288 * If we discover there is no second level table (value is zero) or if there
289 * is an invalid pte, we load that into the TLB, which causes another fault
290 * into the TLB Error interrupt where we can handle such problems.
291 * We have to use the MD_xxx registers for the tablewalk because the
292 * equivalent MI_xxx registers only perform the attribute functions.
293 */
294 InstructionTLBMiss:
295 #ifdef CONFIG_8xx_CPU6
296 stw r3, 8(r0)
297 #endif
298 DO_8xx_CPU6(0x3f80, r3)
299 mtspr SPRN_M_TW, r10 /* Save a couple of working registers */
300 mfcr r10
301 stw r10, 0(r0)
302 stw r11, 4(r0)
303 mfspr r10, SPRN_SRR0 /* Get effective address of fault */
304 DO_8xx_CPU6(0x3780, r3)
305 mtspr SPRN_MD_EPN, r10 /* Have to use MD_EPN for walk, MI_EPN can't */
306 mfspr r10, SPRN_M_TWB /* Get level 1 table entry address */
308 /* If we are faulting a kernel address, we have to use the
309 * kernel page tables.
310 */
311 andi. r11, r10, 0x0800 /* Address >= 0x80000000 */
312 beq 3f
313 lis r11, swapper_pg_dir@h
314 ori r11, r11, swapper_pg_dir@l
315 rlwimi r10, r11, 0, 2, 19
316 3:
317 lwz r11, 0(r10) /* Get the level 1 entry */
318 rlwinm. r10, r11,0,0,19 /* Extract page descriptor page address */
319 beq 2f /* If zero, don't try to find a pte */
321 /* We have a pte table, so load the MI_TWC with the attributes
322 * for this "segment."
323 */
324 ori r11,r11,1 /* Set valid bit */
325 DO_8xx_CPU6(0x2b80, r3)
326 mtspr SPRN_MI_TWC, r11 /* Set segment attributes */
327 DO_8xx_CPU6(0x3b80, r3)
328 mtspr SPRN_MD_TWC, r11 /* Load pte table base address */
329 mfspr r11, SPRN_MD_TWC /* ....and get the pte address */
330 lwz r10, 0(r11) /* Get the pte */
332 #ifdef CONFIG_SWAP
333 /* do not set the _PAGE_ACCESSED bit of a non-present page */
334 andi. r11, r10, _PAGE_PRESENT
335 beq 4f
336 ori r10, r10, _PAGE_ACCESSED
337 mfspr r11, SPRN_MD_TWC /* get the pte address again */
338 stw r10, 0(r11)
339 4:
340 #else
341 ori r10, r10, _PAGE_ACCESSED
342 stw r10, 0(r11)
343 #endif
345 /* The Linux PTE won't go exactly into the MMU TLB.
346 * Software indicator bits 21, 22 and 28 must be clear.
347 * Software indicator bits 24, 25, 26, and 27 must be
348 * set. All other Linux PTE bits control the behavior
349 * of the MMU.
350 */
351 2: li r11, 0x00f0
352 rlwimi r10, r11, 0, 24, 28 /* Set 24-27, clear 28 */
353 DO_8xx_CPU6(0x2d80, r3)
354 mtspr SPRN_MI_RPN, r10 /* Update TLB entry */
356 mfspr r10, SPRN_M_TW /* Restore registers */
357 lwz r11, 0(r0)
358 mtcr r11
359 lwz r11, 4(r0)
360 #ifdef CONFIG_8xx_CPU6
361 lwz r3, 8(r0)
362 #endif
363 rfi
365 . = 0x1200
366 DataStoreTLBMiss:
367 stw r3, 8(r0)
368 DO_8xx_CPU6(0x3f80, r3)
369 mtspr SPRN_M_TW, r10 /* Save a couple of working registers */
370 mfcr r10
371 stw r10, 0(r0)
372 stw r11, 4(r0)
373 mfspr r10, SPRN_M_TWB /* Get level 1 table entry address */
375 /* If we are faulting a kernel address, we have to use the
376 * kernel page tables.
377 */
378 andi. r11, r10, 0x0800
379 beq 3f
380 lis r11, swapper_pg_dir@h
381 ori r11, r11, swapper_pg_dir@l
382 rlwimi r10, r11, 0, 2, 19
383 stw r12, 16(r0)
384 b LoadLargeDTLB
385 3:
386 lwz r11, 0(r10) /* Get the level 1 entry */
387 rlwinm. r10, r11,0,0,19 /* Extract page descriptor page address */
388 beq 2f /* If zero, don't try to find a pte */
390 /* We have a pte table, so load fetch the pte from the table.
391 */
392 ori r11, r11, 1 /* Set valid bit in physical L2 page */
393 DO_8xx_CPU6(0x3b80, r3)
394 mtspr SPRN_MD_TWC, r11 /* Load pte table base address */
395 mfspr r10, SPRN_MD_TWC /* ....and get the pte address */
396 lwz r10, 0(r10) /* Get the pte */
398 /* Insert the Guarded flag into the TWC from the Linux PTE.
399 * It is bit 27 of both the Linux PTE and the TWC (at least
400 * I got that right :-). It will be better when we can put
401 * this into the Linux pgd/pmd and load it in the operation
402 * above.
403 */
404 rlwimi r11, r10, 0, 27, 27
405 DO_8xx_CPU6(0x3b80, r3)
406 mtspr SPRN_MD_TWC, r11
408 #ifdef CONFIG_SWAP
409 /* do not set the _PAGE_ACCESSED bit of a non-present page */
410 andi. r11, r10, _PAGE_PRESENT
411 beq 4f
412 ori r10, r10, _PAGE_ACCESSED
413 4:
414 /* and update pte in table */
415 #else
416 ori r10, r10, _PAGE_ACCESSED
417 #endif
418 mfspr r11, SPRN_MD_TWC /* get the pte address again */
419 stw r10, 0(r11)
421 /* The Linux PTE won't go exactly into the MMU TLB.
422 * Software indicator bits 21, 22 and 28 must be clear.
423 * Software indicator bits 24, 25, 26, and 27 must be
424 * set. All other Linux PTE bits control the behavior
425 * of the MMU.
426 */
427 2: li r11, 0x00f0
428 rlwimi r10, r11, 0, 24, 28 /* Set 24-27, clear 28 */
429 DO_8xx_CPU6(0x3d80, r3)
430 mtspr SPRN_MD_RPN, r10 /* Update TLB entry */
432 mfspr r10, SPRN_M_TW /* Restore registers */
433 lwz r11, 0(r0)
434 mtcr r11
435 lwz r11, 4(r0)
436 lwz r3, 8(r0)
437 rfi
439 /* This is an instruction TLB error on the MPC8xx. This could be due
440 * to many reasons, such as executing guarded memory or illegal instruction
441 * addresses. There is nothing to do but handle a big time error fault.
442 */
443 . = 0x1300
444 InstructionTLBError:
445 b InstructionAccess
447 LoadLargeDTLB:
448 li r12, 0
449 lwz r11, 0(r10) /* Get the level 1 entry */
450 rlwinm. r10, r11,0,0,19 /* Extract page descriptor page address */
451 beq 3f /* If zero, don't try to find a pte */
453 /* We have a pte table, so load fetch the pte from the table.
454 */
455 ori r11, r11, 1 /* Set valid bit in physical L2 page */
456 DO_8xx_CPU6(0x3b80, r3)
457 mtspr SPRN_MD_TWC, r11 /* Load pte table base address */
458 mfspr r10, SPRN_MD_TWC /* ....and get the pte address */
459 lwz r10, 0(r10) /* Get the pte */
461 /* Insert the Guarded flag into the TWC from the Linux PTE.
462 * It is bit 27 of both the Linux PTE and the TWC (at least
463 * I got that right :-). It will be better when we can put
464 * this into the Linux pgd/pmd and load it in the operation
465 * above.
466 */
467 rlwimi r11, r10, 0, 27, 27
469 rlwimi r12, r10, 0, 0, 9 /* extract phys. addr */
470 mfspr r3, SPRN_MD_EPN
471 rlwinm r3, r3, 0, 0, 9 /* extract virtual address */
472 tophys(r3, r3)
473 cmpw r3, r12 /* only use 8M page if it is a direct
474 kernel mapping */
475 bne 1f
476 ori r11, r11, MD_PS8MEG
477 li r12, 1
478 b 2f
479 1:
480 li r12, 0 /* can't use 8MB TLB, so zero r12. */
481 2:
482 DO_8xx_CPU6(0x3b80, r3)
483 mtspr SPRN_MD_TWC, r11
485 /* The Linux PTE won't go exactly into the MMU TLB.
486 * Software indicator bits 21, 22 and 28 must be clear.
487 * Software indicator bits 24, 25, 26, and 27 must be
488 * set. All other Linux PTE bits control the behavior
489 * of the MMU.
490 */
491 3: li r11, 0x00f0
492 rlwimi r10, r11, 0, 24, 28 /* Set 24-27, clear 28 */
493 cmpwi r12, 1
494 bne 4f
495 ori r10, r10, 0x8
497 mfspr r12, SPRN_MD_EPN
498 lis r3, 0xff80 /* 10-19 must be clear for 8MB TLB */
499 ori r3, r3, 0x0fff
500 and r12, r3, r12
501 DO_8xx_CPU6(0x3780, r3)
502 mtspr SPRN_MD_EPN, r12
504 lis r3, 0xff80 /* 10-19 must be clear for 8MB TLB */
505 ori r3, r3, 0x0fff
506 and r10, r3, r10
507 4:
508 DO_8xx_CPU6(0x3d80, r3)
509 mtspr SPRN_MD_RPN, r10 /* Update TLB entry */
511 mfspr r10, SPRN_M_TW /* Restore registers */
512 lwz r11, 0(r0)
513 mtcr r11
514 lwz r11, 4(r0)
516 lwz r12, 16(r0)
517 lwz r3, 8(r0)
518 rfi
520 /* This is the data TLB error on the MPC8xx. This could be due to
521 * many reasons, including a dirty update to a pte. We can catch that
522 * one here, but anything else is an error. First, we track down the
523 * Linux pte. If it is valid, write access is allowed, but the
524 * page dirty bit is not set, we will set it and reload the TLB. For
525 * any other case, we bail out to a higher level function that can
526 * handle it.
527 */
528 . = 0x1400
529 DataTLBError:
530 #ifdef CONFIG_8xx_CPU6
531 stw r3, 8(r0)
532 #endif
533 DO_8xx_CPU6(0x3f80, r3)
534 mtspr SPRN_M_TW, r10 /* Save a couple of working registers */
535 mfcr r10
536 stw r10, 0(r0)
537 stw r11, 4(r0)
539 /* First, make sure this was a store operation.
540 */
541 mfspr r10, SPRN_DSISR
542 andis. r11, r10, 0x0200 /* If set, indicates store op */
543 beq 2f
545 /* The EA of a data TLB miss is automatically stored in the MD_EPN
546 * register. The EA of a data TLB error is automatically stored in
547 * the DAR, but not the MD_EPN register. We must copy the 20 most
548 * significant bits of the EA from the DAR to MD_EPN before we
549 * start walking the page tables. We also need to copy the CASID
550 * value from the M_CASID register.
551 * Addendum: The EA of a data TLB error is _supposed_ to be stored
552 * in DAR, but it seems that this doesn't happen in some cases, such
553 * as when the error is due to a dcbi instruction to a page with a
554 * TLB that doesn't have the changed bit set. In such cases, there
555 * does not appear to be any way to recover the EA of the error
556 * since it is neither in DAR nor MD_EPN. As a workaround, the
557 * _PAGE_HWWRITE bit is set for all kernel data pages when the PTEs
558 * are initialized in mapin_ram(). This will avoid the problem,
559 * assuming we only use the dcbi instruction on kernel addresses.
560 */
561 mfspr r10, SPRN_DAR
562 rlwinm r11, r10, 0, 0, 19
563 ori r11, r11, MD_EVALID
564 mfspr r10, SPRN_M_CASID
565 rlwimi r11, r10, 0, 28, 31
566 DO_8xx_CPU6(0x3780, r3)
567 mtspr SPRN_MD_EPN, r11
569 mfspr r10, SPRN_M_TWB /* Get level 1 table entry address */
571 /* If we are faulting a kernel address, we have to use the
572 * kernel page tables.
573 */
574 andi. r11, r10, 0x0800
575 beq 3f
576 lis r11, swapper_pg_dir@h
577 ori r11, r11, swapper_pg_dir@l
578 rlwimi r10, r11, 0, 2, 19
579 3:
580 lwz r11, 0(r10) /* Get the level 1 entry */
581 rlwinm. r10, r11,0,0,19 /* Extract page descriptor page address */
582 beq 2f /* If zero, bail */
584 /* We have a pte table, so fetch the pte from the table.
585 */
586 ori r11, r11, 1 /* Set valid bit in physical L2 page */
587 DO_8xx_CPU6(0x3b80, r3)
588 mtspr SPRN_MD_TWC, r11 /* Load pte table base address */
589 mfspr r11, SPRN_MD_TWC /* ....and get the pte address */
590 lwz r10, 0(r11) /* Get the pte */
592 andi. r11, r10, _PAGE_RW /* Is it writeable? */
593 beq 2f /* Bail out if not */
595 /* Update 'changed', among others.
596 */
597 #ifdef CONFIG_SWAP
598 ori r10, r10, _PAGE_DIRTY|_PAGE_HWWRITE
599 /* do not set the _PAGE_ACCESSED bit of a non-present page */
600 andi. r11, r10, _PAGE_PRESENT
601 beq 4f
602 ori r10, r10, _PAGE_ACCESSED
603 4:
604 #else
605 ori r10, r10, _PAGE_DIRTY|_PAGE_ACCESSED|_PAGE_HWWRITE
606 #endif
607 mfspr r11, SPRN_MD_TWC /* Get pte address again */
608 stw r10, 0(r11) /* and update pte in table */
610 /* The Linux PTE won't go exactly into the MMU TLB.
611 * Software indicator bits 21, 22 and 28 must be clear.
612 * Software indicator bits 24, 25, 26, and 27 must be
613 * set. All other Linux PTE bits control the behavior
614 * of the MMU.
615 */
616 li r11, 0x00f0
617 rlwimi r10, r11, 0, 24, 28 /* Set 24-27, clear 28 */
618 DO_8xx_CPU6(0x3d80, r3)
619 mtspr SPRN_MD_RPN, r10 /* Update TLB entry */
621 mfspr r10, SPRN_M_TW /* Restore registers */
622 lwz r11, 0(r0)
623 mtcr r11
624 lwz r11, 4(r0)
625 #ifdef CONFIG_8xx_CPU6
626 lwz r3, 8(r0)
627 #endif
628 rfi
629 2:
630 mfspr r10, SPRN_M_TW /* Restore registers */
631 lwz r11, 0(r0)
632 mtcr r11
633 lwz r11, 4(r0)
634 #ifdef CONFIG_8xx_CPU6
635 lwz r3, 8(r0)
636 #endif
637 b DataAccess
639 EXCEPTION(0x1500, Trap_15, unknown_exception, EXC_XFER_EE)
640 EXCEPTION(0x1600, Trap_16, unknown_exception, EXC_XFER_EE)
641 EXCEPTION(0x1700, Trap_17, unknown_exception, EXC_XFER_EE)
642 EXCEPTION(0x1800, Trap_18, unknown_exception, EXC_XFER_EE)
643 EXCEPTION(0x1900, Trap_19, unknown_exception, EXC_XFER_EE)
644 EXCEPTION(0x1a00, Trap_1a, unknown_exception, EXC_XFER_EE)
645 EXCEPTION(0x1b00, Trap_1b, unknown_exception, EXC_XFER_EE)
647 /* On the MPC8xx, these next four traps are used for development
648 * support of breakpoints and such. Someday I will get around to
649 * using them.
650 */
651 EXCEPTION(0x1c00, Trap_1c, unknown_exception, EXC_XFER_EE)
652 EXCEPTION(0x1d00, Trap_1d, unknown_exception, EXC_XFER_EE)
653 EXCEPTION(0x1e00, Trap_1e, unknown_exception, EXC_XFER_EE)
654 EXCEPTION(0x1f00, Trap_1f, unknown_exception, EXC_XFER_EE)
656 . = 0x2000
658 .globl giveup_fpu
659 giveup_fpu:
660 blr
662 /*
663 * This is where the main kernel code starts.
664 */
665 start_here:
666 /* ptr to current */
667 lis r2,init_task@h
668 ori r2,r2,init_task@l
670 /* ptr to phys current thread */
671 tophys(r4,r2)
672 addi r4,r4,THREAD /* init task's THREAD */
673 mtspr SPRN_SPRG3,r4
674 li r3,0
675 mtspr SPRN_SPRG2,r3 /* 0 => r1 has kernel sp */
677 /* stack */
678 lis r1,init_thread_union@ha
679 addi r1,r1,init_thread_union@l
680 li r0,0
681 stwu r0,THREAD_SIZE-STACK_FRAME_OVERHEAD(r1)
683 bl early_init /* We have to do this with MMU on */
685 /*
686 * Decide what sort of machine this is and initialize the MMU.
687 */
688 mr r3,r31
689 mr r4,r30
690 mr r5,r29
691 mr r6,r28
692 mr r7,r27
693 bl machine_init
694 bl MMU_init
696 /*
697 * Go back to running unmapped so we can load up new values
698 * and change to using our exception vectors.
699 * On the 8xx, all we have to do is invalidate the TLB to clear
700 * the old 8M byte TLB mappings and load the page table base register.
701 */
702 /* The right way to do this would be to track it down through
703 * init's THREAD like the context switch code does, but this is
704 * easier......until someone changes init's static structures.
705 */
706 lis r6, swapper_pg_dir@h
707 ori r6, r6, swapper_pg_dir@l
708 tophys(r6,r6)
709 #ifdef CONFIG_8xx_CPU6
710 lis r4, cpu6_errata_word@h
711 ori r4, r4, cpu6_errata_word@l
712 li r3, 0x3980
713 stw r3, 12(r4)
714 lwz r3, 12(r4)
715 #endif
716 mtspr SPRN_M_TWB, r6
717 lis r4,2f@h
718 ori r4,r4,2f@l
719 tophys(r4,r4)
720 li r3,MSR_KERNEL & ~(MSR_IR|MSR_DR)
721 mtspr SPRN_SRR0,r4
722 mtspr SPRN_SRR1,r3
723 rfi
724 /* Load up the kernel context */
725 2:
726 SYNC /* Force all PTE updates to finish */
727 tlbia /* Clear all TLB entries */
728 sync /* wait for tlbia/tlbie to finish */
729 TLBSYNC /* ... on all CPUs */
731 /* set up the PTE pointers for the Abatron bdiGDB.
732 */
733 tovirt(r6,r6)
734 lis r5, abatron_pteptrs@h
735 ori r5, r5, abatron_pteptrs@l
736 stw r5, 0xf0(r0) /* Must match your Abatron config file */
737 tophys(r5,r5)
738 stw r6, 0(r5)
740 /* Now turn on the MMU for real! */
741 li r4,MSR_KERNEL
742 lis r3,start_kernel@h
743 ori r3,r3,start_kernel@l
744 mtspr SPRN_SRR0,r3
745 mtspr SPRN_SRR1,r4
746 rfi /* enable MMU and jump to start_kernel */
748 /* Set up the initial MMU state so we can do the first level of
749 * kernel initialization. This maps the first 8 MBytes of memory 1:1
750 * virtual to physical. Also, set the cache mode since that is defined
751 * by TLB entries and perform any additional mapping (like of the IMMR).
752 * If configured to pin some TLBs, we pin the first 8 Mbytes of kernel,
753 * 24 Mbytes of data, and the 8M IMMR space. Anything not covered by
754 * these mappings is mapped by page tables.
755 */
756 initial_mmu:
757 tlbia /* Invalidate all TLB entries */
758 #ifdef CONFIG_PIN_TLB
759 lis r8, MI_RSV4I@h
760 ori r8, r8, 0x1c00
761 #else
762 li r8, 0
763 #endif
764 mtspr SPRN_MI_CTR, r8 /* Set instruction MMU control */
766 #ifdef CONFIG_PIN_TLB
767 lis r10, (MD_RSV4I | MD_RESETVAL)@h
768 ori r10, r10, 0x1c00
769 mr r8, r10
770 #else
771 lis r10, MD_RESETVAL@h
772 #endif
773 #ifndef CONFIG_8xx_COPYBACK
774 oris r10, r10, MD_WTDEF@h
775 #endif
776 mtspr SPRN_MD_CTR, r10 /* Set data TLB control */
778 /* Now map the lower 8 Meg into the TLBs. For this quick hack,
779 * we can load the instruction and data TLB registers with the
780 * same values.
781 */
782 lis r8, KERNELBASE@h /* Create vaddr for TLB */
783 ori r8, r8, MI_EVALID /* Mark it valid */
784 mtspr SPRN_MI_EPN, r8
785 mtspr SPRN_MD_EPN, r8
786 li r8, MI_PS8MEG /* Set 8M byte page */
787 ori r8, r8, MI_SVALID /* Make it valid */
788 mtspr SPRN_MI_TWC, r8
789 mtspr SPRN_MD_TWC, r8
790 li r8, MI_BOOTINIT /* Create RPN for address 0 */
791 mtspr SPRN_MI_RPN, r8 /* Store TLB entry */
792 mtspr SPRN_MD_RPN, r8
793 lis r8, MI_Kp@h /* Set the protection mode */
794 mtspr SPRN_MI_AP, r8
795 mtspr SPRN_MD_AP, r8
797 /* Map another 8 MByte at the IMMR to get the processor
798 * internal registers (among other things).
799 */
800 #ifdef CONFIG_PIN_TLB
801 addi r10, r10, 0x0100
802 mtspr SPRN_MD_CTR, r10
803 #endif
804 mfspr r9, 638 /* Get current IMMR */
805 andis. r9, r9, 0xff80 /* Get 8Mbyte boundary */
807 mr r8, r9 /* Create vaddr for TLB */
808 ori r8, r8, MD_EVALID /* Mark it valid */
809 mtspr SPRN_MD_EPN, r8
810 li r8, MD_PS8MEG /* Set 8M byte page */
811 ori r8, r8, MD_SVALID /* Make it valid */
812 mtspr SPRN_MD_TWC, r8
813 mr r8, r9 /* Create paddr for TLB */
814 ori r8, r8, MI_BOOTINIT|0x2 /* Inhibit cache -- Cort */
815 mtspr SPRN_MD_RPN, r8
817 #ifdef CONFIG_PIN_TLB
818 /* Map two more 8M kernel data pages.
819 */
820 addi r10, r10, 0x0100
821 mtspr SPRN_MD_CTR, r10
823 lis r8, KERNELBASE@h /* Create vaddr for TLB */
824 addis r8, r8, 0x0080 /* Add 8M */
825 ori r8, r8, MI_EVALID /* Mark it valid */
826 mtspr SPRN_MD_EPN, r8
827 li r9, MI_PS8MEG /* Set 8M byte page */
828 ori r9, r9, MI_SVALID /* Make it valid */
829 mtspr SPRN_MD_TWC, r9
830 li r11, MI_BOOTINIT /* Create RPN for address 0 */
831 addis r11, r11, 0x0080 /* Add 8M */
832 mtspr SPRN_MD_RPN, r11
834 addi r10, r10, 0x0100
835 mtspr SPRN_MD_CTR, r10
837 addis r8, r8, 0x0080 /* Add 8M */
838 mtspr SPRN_MD_EPN, r8
839 mtspr SPRN_MD_TWC, r9
840 addis r11, r11, 0x0080 /* Add 8M */
841 mtspr SPRN_MD_RPN, r11
842 #endif
844 /* Since the cache is enabled according to the information we
845 * just loaded into the TLB, invalidate and enable the caches here.
846 * We should probably check/set other modes....later.
847 */
848 lis r8, IDC_INVALL@h
849 mtspr SPRN_IC_CST, r8
850 mtspr SPRN_DC_CST, r8
851 lis r8, IDC_ENABLE@h
852 mtspr SPRN_IC_CST, r8
853 #ifdef CONFIG_8xx_COPYBACK
854 mtspr SPRN_DC_CST, r8
855 #else
856 /* For a debug option, I left this here to easily enable
857 * the write through cache mode
858 */
859 lis r8, DC_SFWT@h
860 mtspr SPRN_DC_CST, r8
861 lis r8, IDC_ENABLE@h
862 mtspr SPRN_DC_CST, r8
863 #endif
864 blr
867 /*
868 * Set up to use a given MMU context.
869 * r3 is context number, r4 is PGD pointer.
870 *
871 * We place the physical address of the new task page directory loaded
872 * into the MMU base register, and set the ASID compare register with
873 * the new "context."
874 */
875 _GLOBAL(set_context)
877 #ifdef CONFIG_BDI_SWITCH
878 /* Context switch the PTE pointer for the Abatron BDI2000.
879 * The PGDIR is passed as second argument.
880 */
881 lis r5, KERNELBASE@h
882 lwz r5, 0xf0(r5)
883 stw r4, 0x4(r5)
884 #endif
886 #ifdef CONFIG_8xx_CPU6
887 lis r6, cpu6_errata_word@h
888 ori r6, r6, cpu6_errata_word@l
889 tophys (r4, r4)
890 li r7, 0x3980
891 stw r7, 12(r6)
892 lwz r7, 12(r6)
893 mtspr SPRN_M_TWB, r4 /* Update MMU base address */
894 li r7, 0x3380
895 stw r7, 12(r6)
896 lwz r7, 12(r6)
897 mtspr SPRN_M_CASID, r3 /* Update context */
898 #else
899 mtspr SPRN_M_CASID,r3 /* Update context */
900 tophys (r4, r4)
901 mtspr SPRN_M_TWB, r4 /* and pgd */
902 #endif
903 SYNC
904 blr
906 #ifdef CONFIG_8xx_CPU6
907 /* It's here because it is unique to the 8xx.
908 * It is important we get called with interrupts disabled. I used to
909 * do that, but it appears that all code that calls this already had
910 * interrupt disabled.
911 */
912 .globl set_dec_cpu6
913 set_dec_cpu6:
914 lis r7, cpu6_errata_word@h
915 ori r7, r7, cpu6_errata_word@l
916 li r4, 0x2c00
917 stw r4, 8(r7)
918 lwz r4, 8(r7)
919 mtspr 22, r3 /* Update Decrementer */
920 SYNC
921 blr
922 #endif
924 /*
925 * We put a few things here that have to be page-aligned.
926 * This stuff goes at the beginning of the data segment,
927 * which is page-aligned.
928 */
929 .data
930 .globl sdata
931 sdata:
932 .globl empty_zero_page
933 empty_zero_page:
934 .space 4096
936 .globl swapper_pg_dir
937 swapper_pg_dir:
938 .space 4096
940 /*
941 * This space gets a copy of optional info passed to us by the bootstrap
942 * Used to pass parameters into the kernel like root=/dev/sda1, etc.
943 */
944 .globl cmd_line
945 cmd_line:
946 .space 512
948 /* Room for two PTE table poiners, usually the kernel and current user
949 * pointer to their respective root page table (pgdir).
950 */
951 abatron_pteptrs:
952 .space 8
954 #ifdef CONFIG_8xx_CPU6
955 .globl cpu6_errata_word
956 cpu6_errata_word:
957 .space 16
958 #endif