arch/ppc/platforms/4xx/ocotea.h

   1 /*
   2  * Ocotea board definitions
   3  *
   4  * Matt Porter <mporter@kernel.crashing.org>
   5  *
   6  * Copyright 2003-2005 MontaVista Software Inc.
   7  *
   8  * This program is free software; you can redistribute  it and/or modify it
   9  * under  the terms of  the GNU General  Public License as published by the
  10  * Free Software Foundation;  either version 2 of the  License, or (at your
  11  * option) any later version.
  12  *
  13  */
  14
  15 #ifdef __KERNEL__
  16 #ifndef __ASM_OCOTEA_H__
  17 #define __ASM_OCOTEA_H__
  18
  19 #include <platforms/4xx/ibm440gx.h>
  20
  21 /* F/W TLB mapping used in bootloader glue to reset EMAC */
  22 #define PPC44x_EMAC0_MR0        0xe0000800
  23
  24 /* Location of MAC addresses in PIBS image */
  25 #define PIBS_FLASH_BASE         0xfff00000
  26 #define PIBS_MAC_BASE           (PIBS_FLASH_BASE+0xb0500)
  27 #define PIBS_MAC_SIZE           0x200
  28 #define PIBS_MAC_OFFSET         0x100
  29
  30 /* External timer clock frequency */
  31 #define OCOTEA_TMR_CLK  25000000
  32
  33 /* RTC/NVRAM location */
  34 #define OCOTEA_RTC_ADDR         0x0000000148000000ULL
  35 #define OCOTEA_RTC_SIZE         0x2000
  36
  37 /* Flash */
  38 #define OCOTEA_FPGA_REG_0               0x0000000148300000ULL
  39 #define OCOTEA_BOOT_LARGE_FLASH(x)      (x & 0x40)
  40 #define OCOTEA_SMALL_FLASH_LOW          0x00000001ff900000ULL
  41 #define OCOTEA_SMALL_FLASH_HIGH         0x00000001fff00000ULL
  42 #define OCOTEA_SMALL_FLASH_SIZE         0x100000
  43 #define OCOTEA_LARGE_FLASH_LOW          0x00000001ff800000ULL
  44 #define OCOTEA_LARGE_FLASH_HIGH         0x00000001ffc00000ULL
  45 #define OCOTEA_LARGE_FLASH_SIZE         0x400000
  46
  47 /* FPGA_REG_3 (Ethernet Groups) */
  48 #define OCOTEA_FPGA_REG_3               0x0000000148300003ULL
  49
  50 /*
  51  * Serial port defines
  52  */
  53 #define RS_TABLE_SIZE   2
  54
  55 #if defined(__BOOTER__)
  56 /* OpenBIOS defined UART mappings, used by bootloader shim */
  57 #define UART0_IO_BASE   0xE0000200
  58 #define UART1_IO_BASE   0xE0000300
  59 #else
  60 /* head_44x.S created UART mapping, used before early_serial_setup.
  61  * We cannot use default OpenBIOS UART mappings because they
  62  * don't work for configurations with more than 512M RAM.    --ebs
  63  */
  64 #define UART0_IO_BASE   0xF0000200
  65 #define UART1_IO_BASE   0xF0000300
  66 #endif
  67
  68 #define BASE_BAUD       11059200/16
  69 #define STD_UART_OP(num)                                        \
  70         { 0, BASE_BAUD, 0, UART##num##_INT,                     \
  71                 (ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST),        \
  72                 iomem_base: (void*)UART##num##_IO_BASE,         \
  73                 io_type: SERIAL_IO_MEM},
  74
  75 #define SERIAL_PORT_DFNS        \
  76         STD_UART_OP(0)          \
  77         STD_UART_OP(1)
  78
  79 /* PCI support */
  80 #define OCOTEA_PCI_LOWER_IO     0x00000000
  81 #define OCOTEA_PCI_UPPER_IO     0x0000ffff
  82 #define OCOTEA_PCI_LOWER_MEM    0x80000000
  83 #define OCOTEA_PCI_UPPER_MEM    0xffffefff
  84
  85 #define OCOTEA_PCI_CFGREGS_BASE 0x000000020ec00000ULL
  86 #define OCOTEA_PCI_CFGA_PLB32   0x0ec00000
  87 #define OCOTEA_PCI_CFGD_PLB32   0x0ec00004
  88
  89 #define OCOTEA_PCI_IO_BASE      0x0000000208000000ULL
  90 #define OCOTEA_PCI_IO_SIZE      0x00010000
  91 #define OCOTEA_PCI_MEM_OFFSET   0x00000000
  92
  93 #endif                          /* __ASM_OCOTEA_H__ */
  94 #endif                          /* __KERNEL__ */