arch/ppc/platforms/fads.h

   1 /*
   2  * A collection of structures, addresses, and values associated with
   3  * the Motorola 860T FADS board.  Copied from the MBX stuff.
   4  *
   5  * Copyright (c) 1998 Dan Malek (dmalek@jlc.net)
   6  *
   7  * Added MPC86XADS support.
   8  * The MPC86xADS manual says the board "is compatible with the MPC8xxFADS
   9  * for SW point of view". This is 99% correct.
  10  *
  11  * Author: MontaVista Software, Inc.
  12  *         source@mvista.com
  13  * 2005 (c) MontaVista Software, Inc.  This file is licensed under the
  14  * terms of the GNU General Public License version 2.  This program is licensed
  15  * "as is" without any warranty of any kind, whether express or implied.
  16  */
  17
  18 #ifdef __KERNEL__
  19 #ifndef __ASM_FADS_H__
  20 #define __ASM_FADS_H__
  21
  22
  23 #include <asm/ppcboot.h>
  24
  25 /* Memory map is configured by the PROM startup.
  26  * I tried to follow the FADS manual, although the startup PROM
  27  * dictates this and we simply have to move some of the physical
  28  * addresses for Linux.
  29  */
  30 #define BCSR_ADDR               ((uint)0xff010000)
  31
  32 /* PHY link change interrupt */
  33 #define PHY_INTERRUPT   SIU_IRQ2
  34
  35 #define BCSR_SIZE               ((uint)(64 * 1024))
  36 #define BCSR0                   ((uint)(BCSR_ADDR + 0x00))
  37 #define BCSR1                   ((uint)(BCSR_ADDR + 0x04))
  38 #define BCSR2                   ((uint)(BCSR_ADDR + 0x08))
  39 #define BCSR3                   ((uint)(BCSR_ADDR + 0x0c))
  40 #define BCSR4                   ((uint)(BCSR_ADDR + 0x10))
  41
  42 #define IMAP_ADDR               ((uint)0xff000000)
  43 #define IMAP_SIZE               ((uint)(64 * 1024))
  44
  45 #define PCMCIA_MEM_ADDR         ((uint)0xff020000)
  46 #define PCMCIA_MEM_SIZE         ((uint)(64 * 1024))
  47
  48 /* Bits of interest in the BCSRs.
  49  */
  50 #define BCSR1_ETHEN             ((uint)0x20000000)
  51 #define BCSR1_IRDAEN            ((uint)0x10000000)
  52 #define BCSR1_RS232EN_1         ((uint)0x01000000)
  53 #define BCSR1_PCCEN             ((uint)0x00800000)
  54 #define BCSR1_PCCVCC0           ((uint)0x00400000)
  55 #define BCSR1_PCCVPP0           ((uint)0x00200000)
  56 #define BCSR1_PCCVPP1           ((uint)0x00100000)
  57 #define BCSR1_PCCVPP_MASK       (BCSR1_PCCVPP0 | BCSR1_PCCVPP1)
  58 #define BCSR1_RS232EN_2         ((uint)0x00040000)
  59 #define BCSR1_PCCVCC1           ((uint)0x00010000)
  60 #define BCSR1_PCCVCC_MASK       (BCSR1_PCCVCC0 | BCSR1_PCCVCC1)
  61
  62 #define BCSR4_ETHLOOP           ((uint)0x80000000)      /* EEST Loopback */
  63 #define BCSR4_EEFDX             ((uint)0x40000000)      /* EEST FDX enable */
  64 #define BCSR4_FETH_EN           ((uint)0x08000000)      /* PHY enable */
  65 #define BCSR4_FETHCFG0          ((uint)0x04000000)      /* PHY autoneg mode */
  66 #define BCSR4_FETHCFG1          ((uint)0x00400000)      /* PHY autoneg mode */
  67 #define BCSR4_FETHFDE           ((uint)0x02000000)      /* PHY FDX advertise */
  68 #define BCSR4_FETHRST           ((uint)0x00200000)      /* PHY Reset */
  69
  70 /* IO_BASE definition for pcmcia.
  71  */
  72 #define _IO_BASE        0x80000000
  73 #define _IO_BASE_SIZE   0x1000
  74
  75 #ifdef CONFIG_IDE
  76 #define MAX_HWIFS 1
  77 #endif
  78
  79 /* Interrupt level assignments.
  80  */
  81 #define FEC_INTERRUPT   SIU_LEVEL1      /* FEC interrupt */
  82
  83 /* We don't use the 8259.
  84  */
  85 #define NR_8259_INTS    0
  86
  87 /* CPM Ethernet through SCC1 or SCC2 */
  88
  89 #if defined(CONFIG_SCC1_ENET) || defined(CONFIG_MPC8xx_SECOND_ETH_SCC1)         /* Probably 860 variant */
  90 /* Bits in parallel I/O port registers that have to be set/cleared
  91  * to configure the pins for SCC1 use.
  92  * TCLK - CLK1, RCLK - CLK2.
  93  */
  94 #define PA_ENET_RXD     ((ushort)0x0001)
  95 #define PA_ENET_TXD     ((ushort)0x0002)
  96 #define PA_ENET_TCLK    ((ushort)0x0100)
  97 #define PA_ENET_RCLK    ((ushort)0x0200)
  98 #define PB_ENET_TENA    ((uint)0x00001000)
  99 #define PC_ENET_CLSN    ((ushort)0x0010)
 100 #define PC_ENET_RENA    ((ushort)0x0020)
 101
 102 /* Control bits in the SICR to route TCLK (CLK1) and RCLK (CLK2) to
 103  * SCC1.  Also, make sure GR1 (bit 24) and SC1 (bit 25) are zero.
 104  */
 105 #define SICR_ENET_MASK  ((uint)0x000000ff)
 106 #define SICR_ENET_CLKRT ((uint)0x0000002c)
 107 #endif /* CONFIG_SCC1_ENET */
 108
 109 #ifdef CONFIG_SCC2_ENET         /* Probably 823/850 variant */
 110 /* Bits in parallel I/O port registers that have to be set/cleared
 111  * to configure the pins for SCC1 use.
 112  * TCLK - CLK1, RCLK - CLK2.
 113  */
 114 #define PA_ENET_RXD     ((ushort)0x0004)
 115 #define PA_ENET_TXD     ((ushort)0x0008)
 116 #define PA_ENET_TCLK    ((ushort)0x0400)
 117 #define PA_ENET_RCLK    ((ushort)0x0200)
 118 #define PB_ENET_TENA    ((uint)0x00002000)
 119 #define PC_ENET_CLSN    ((ushort)0x0040)
 120 #define PC_ENET_RENA    ((ushort)0x0080)
 121
 122 /* Control bits in the SICR to route TCLK and RCLK to
 123  * SCC2.  Also, make sure GR1 (bit 24) and SC1 (bit 25) are zero.
 124  */
 125 #define SICR_ENET_MASK  ((uint)0x0000ff00)
 126 #define SICR_ENET_CLKRT ((uint)0x00002e00)
 127 #endif /* CONFIG_SCC2_ENET */
 128
 129 #endif /* __ASM_FADS_H__ */
 130 #endif /* __KERNEL__ */