arch/ppc/platforms/mbx.h

   1 /*
   2  * A collection of structures, addresses, and values associated with
   3  * the Motorola MBX boards.  This was originally created for the
   4  * MBX860, and probably needs revisions for other boards (like the 821).
   5  * When this file gets out of control, we can split it up into more
   6  * meaningful pieces.
   7  *
   8  * Copyright (c) 1997 Dan Malek (dmalek@jlc.net)
   9  */
  10 #ifdef __KERNEL__
  11 #ifndef __MACH_MBX_DEFS
  12 #define __MACH_MBX_DEFS
  13
  14 #ifndef __ASSEMBLY__
  15 /* A Board Information structure that is given to a program when
  16  * EPPC-Bug starts it up.
  17  */
  18 typedef struct bd_info {
  19         unsigned int    bi_tag;         /* Should be 0x42444944 "BDID" */
  20         unsigned int    bi_size;        /* Size of this structure */
  21         unsigned int    bi_revision;    /* revision of this structure */
  22         unsigned int    bi_bdate;       /* EPPCbug date, i.e. 0x11061997 */
  23         unsigned int    bi_memstart;    /* Memory start address */
  24         unsigned int    bi_memsize;     /* Memory (end) size in bytes */
  25         unsigned int    bi_intfreq;     /* Internal Freq, in Hz */
  26         unsigned int    bi_busfreq;     /* Bus Freq, in Hz */
  27         unsigned int    bi_clun;        /* Boot device controller */
  28         unsigned int    bi_dlun;        /* Boot device logical dev */
  29
  30         /* These fields are not part of the board information structure
  31          * provided by the boot rom.  They are filled in by embed_config.c
  32          * so we have the information consistent with other platforms.
  33          */
  34         unsigned char   bi_enetaddr[6];
  35         unsigned int    bi_baudrate;
  36 } bd_t;
  37
  38 /* Memory map for the MBX as configured by EPPC-Bug.  We could reprogram
  39  * The SIU and PCI bridge, and try to use larger MMU pages, but the
  40  * performance gain is not measurable and it certainly complicates the
  41  * generic MMU model.
  42  *
  43  * In a effort to minimize memory usage for embedded applications, any
  44  * PCI driver or ISA driver must request or map the region required by
  45  * the device.  For convenience (and since we can map up to 4 Mbytes with
  46  * a single page table page), the MMU initialization will map the
  47  * NVRAM, Status/Control registers, CPM Dual Port RAM, and the PCI
  48  * Bridge CSRs 1:1 into the kernel address space.
  49  */
  50 #define PCI_ISA_IO_ADDR         ((unsigned)0x80000000)
  51 #define PCI_ISA_IO_SIZE         ((uint)(512 * 1024 * 1024))
  52 #define PCI_IDE_ADDR            ((unsigned)0x81000000)
  53 #define PCI_ISA_MEM_ADDR        ((unsigned)0xc0000000)
  54 #define PCI_ISA_MEM_SIZE        ((uint)(512 * 1024 * 1024))
  55 #define PCMCIA_MEM_ADDR         ((uint)0xe0000000)
  56 #define PCMCIA_MEM_SIZE         ((uint)(64 * 1024 * 1024))
  57 #define PCMCIA_DMA_ADDR         ((uint)0xe4000000)
  58 #define PCMCIA_DMA_SIZE         ((uint)(64 * 1024 * 1024))
  59 #define PCMCIA_ATTRB_ADDR       ((uint)0xe8000000)
  60 #define PCMCIA_ATTRB_SIZE       ((uint)(64 * 1024 * 1024))
  61 #define PCMCIA_IO_ADDR          ((uint)0xec000000)
  62 #define PCMCIA_IO_SIZE          ((uint)(64 * 1024 * 1024))
  63 #define NVRAM_ADDR              ((uint)0xfa000000)
  64 #define NVRAM_SIZE              ((uint)(1 * 1024 * 1024))
  65 #define MBX_CSR_ADDR            ((uint)0xfa100000)
  66 #define MBX_CSR_SIZE            ((uint)(1 * 1024 * 1024))
  67 #define IMAP_ADDR               ((uint)0xfa200000)
  68 #define IMAP_SIZE               ((uint)(64 * 1024))
  69 #define PCI_CSR_ADDR            ((uint)0xfa210000)
  70 #define PCI_CSR_SIZE            ((uint)(64 * 1024))
  71
  72 /* Map additional physical space into well known virtual addresses.  Due
  73  * to virtual address mapping, these physical addresses are not accessible
  74  * in a 1:1 virtual to physical mapping.
  75  */
  76 #define ISA_IO_VIRT_ADDR        ((uint)0xfa220000)
  77 #define ISA_IO_VIRT_SIZE        ((uint)64 * 1024)
  78
  79 /* Interrupt assignments.
  80  * These are defined (and fixed) by the MBX hardware implementation.
  81  */
  82 #define POWER_FAIL_INT  SIU_IRQ0        /* Power fail */
  83 #define TEMP_HILO_INT   SIU_IRQ1        /* Temperature sensor */
  84 #define QSPAN_INT       SIU_IRQ2        /* PCI Bridge (DMA CTLR?) */
  85 #define ISA_BRIDGE_INT  SIU_IRQ3        /* All those PC things */
  86 #define COMM_L_INT      SIU_IRQ6        /* MBX Comm expansion connector pin */
  87 #define STOP_ABRT_INT   SIU_IRQ7        /* Stop/Abort header pin */
  88
  89 /* CPM Ethernet through SCCx.
  90  *
  91  * Bits in parallel I/O port registers that have to be set/cleared
  92  * to configure the pins for SCC1 use.  The TCLK and RCLK seem unique
  93  * to the MBX860 board.  Any two of the four available clocks could be
  94  * used, and the MPC860 cookbook manual has an example using different
  95  * clock pins.
  96  */
  97 #define PA_ENET_RXD     ((ushort)0x0001)
  98 #define PA_ENET_TXD     ((ushort)0x0002)
  99 #define PA_ENET_TCLK    ((ushort)0x0200)
 100 #define PA_ENET_RCLK    ((ushort)0x0800)
 101 #define PC_ENET_TENA    ((ushort)0x0001)
 102 #define PC_ENET_CLSN    ((ushort)0x0010)
 103 #define PC_ENET_RENA    ((ushort)0x0020)
 104
 105 /* Control bits in the SICR to route TCLK (CLK2) and RCLK (CLK4) to
 106  * SCC1.  Also, make sure GR1 (bit 24) and SC1 (bit 25) are zero.
 107  */
 108 #define SICR_ENET_MASK  ((uint)0x000000ff)
 109 #define SICR_ENET_CLKRT ((uint)0x0000003d)
 110
 111 /* The MBX uses the 8259.
 112 */
 113 #define NR_8259_INTS    16
 114
 115 #endif /* !__ASSEMBLY__ */
 116 #endif /* __MACH_MBX_DEFS */
 117 #endif /* __KERNEL__ */