?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
ia64/kvm: compilation fix. export account_system_vtime.
[pv_ops_mirror.git] / arch / ppc / platforms / pplus.c
blobcbcac85c7a78bb13b8632675852a0d52521051a4
1 /*
2 * Board and PCI setup routines for MCG PowerPlus
3 *
4 * Author: Randy Vinson <rvinson@mvista.com>
5 *
6 * Derived from original PowerPlus PReP work by
7 * Cort Dougan, Johnnie Peters, Matt Porter, and
8 * Troy Benjegerdes.
9 *
10 * 2001-2004 (c) MontaVista, Software, Inc. This file is licensed under
11 * the terms of the GNU General Public License version 2. This program
12 * is licensed "as is" without any warranty of any kind, whether express
13 * or implied.
14 */
15
16 #include <linux/kernel.h>
17 #include <linux/interrupt.h>
18 #include <linux/init.h>
19 #include <linux/ioport.h>
20 #include <linux/console.h>
21 #include <linux/pci.h>
22 #include <linux/seq_file.h>
23 #include <linux/root_dev.h>
24
25 #include <asm/system.h>
26 #include <asm/io.h>
27 #include <asm/pgtable.h>
28 #include <asm/dma.h>
29 #include <asm/machdep.h>
30 #include <asm/prep_nvram.h>
31 #include <asm/vga.h>
32 #include <asm/i8259.h>
33 #include <asm/open_pic.h>
34 #include <asm/hawk.h>
35 #include <asm/todc.h>
36 #include <asm/bootinfo.h>
37 #include <asm/kgdb.h>
38 #include <asm/reg.h>
39
40 #include "pplus.h"
41
42 #undef DUMP_DBATS
43
44 TODC_ALLOC();
45
46 extern void pplus_setup_hose(void);
47 extern void pplus_set_VIA_IDE_native(void);
48
49 extern unsigned long loops_per_jiffy;
50 unsigned char *Motherboard_map_name;
51
52 /* Tables for known hardware */
53
54 /* Motorola Mesquite */
55 static inline int
56 mesquite_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin)
57 {
58 static char pci_irq_table[][4] =
59 /*
60 * MPIC interrupts for various IDSEL values (MPIC IRQ0 =
61 * Linux IRQ16 (to leave room for ISA IRQs at 0-15).
62 * PCI IDSEL/INTPIN->INTLINE
63 * A B C D
64 */
65 {
66 {18, 0, 0, 0}, /* IDSEL 14 - Enet 0 */
67 { 0, 0, 0, 0}, /* IDSEL 15 - unused */
68 {19, 19, 19, 19}, /* IDSEL 16 - PMC Slot 1 */
69 { 0, 0, 0, 0}, /* IDSEL 17 - unused */
70 { 0, 0, 0, 0}, /* IDSEL 18 - unused */
71 { 0, 0, 0, 0}, /* IDSEL 19 - unused */
72 {24, 25, 26, 27}, /* IDSEL 20 - P2P bridge (to cPCI 1) */
73 { 0, 0, 0, 0}, /* IDSEL 21 - unused */
74 {28, 29, 30, 31} /* IDSEL 22 - P2P bridge (to cPCI 2) */
75 };
76
77 const long min_idsel = 14, max_idsel = 22, irqs_per_slot = 4;
78 return PCI_IRQ_TABLE_LOOKUP;
79 }
80
81 /* Motorola Sitka */
82 static inline int
83 sitka_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin)
84 {
85 static char pci_irq_table[][4] =
86 /*
87 * MPIC interrupts for various IDSEL values (MPIC IRQ0 =
88 * Linux IRQ16 (to leave room for ISA IRQs at 0-15).
89 * PCI IDSEL/INTPIN->INTLINE
90 * A B C D
91 */
92 {
93 {18, 0, 0, 0}, /* IDSEL 14 - Enet 0 */
94 { 0, 0, 0, 0}, /* IDSEL 15 - unused */
95 {25, 26, 27, 28}, /* IDSEL 16 - PMC Slot 1 */
96 {28, 25, 26, 27}, /* IDSEL 17 - PMC Slot 2 */
97 { 0, 0, 0, 0}, /* IDSEL 18 - unused */
98 { 0, 0, 0, 0}, /* IDSEL 19 - unused */
99 {20, 0, 0, 0} /* IDSEL 20 - P2P bridge (to cPCI) */
100 };
101
102 const long min_idsel = 14, max_idsel = 20, irqs_per_slot = 4;
103 return PCI_IRQ_TABLE_LOOKUP;
104 }
105
106 /* Motorola MTX */
107 static inline int
108 MTX_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin)
109 {
110 static char pci_irq_table[][4] =
111 /*
112 * MPIC interrupts for various IDSEL values (MPIC IRQ0 =
113 * Linux IRQ16 (to leave room for ISA IRQs at 0-15).
114 * PCI IDSEL/INTPIN->INTLINE
115 * A B C D
116 */
117 {
118 {19, 0, 0, 0}, /* IDSEL 12 - SCSI */
119 { 0, 0, 0, 0}, /* IDSEL 13 - unused */
120 {18, 0, 0, 0}, /* IDSEL 14 - Enet */
121 { 0, 0, 0, 0}, /* IDSEL 15 - unused */
122 {25, 26, 27, 28}, /* IDSEL 16 - PMC Slot 1 */
123 {26, 27, 28, 25}, /* IDSEL 17 - PMC Slot 2 */
124 {27, 28, 25, 26} /* IDSEL 18 - PCI Slot 3 */
125 };
126
127 const long min_idsel = 12, max_idsel = 18, irqs_per_slot = 4;
128 return PCI_IRQ_TABLE_LOOKUP;
129 }
130
131 /* Motorola MTX Plus */
132 /* Secondary bus interrupt routing is not supported yet */
133 static inline int
134 MTXplus_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin)
135 {
136 static char pci_irq_table[][4] =
137 /*
138 * MPIC interrupts for various IDSEL values (MPIC IRQ0 =
139 * Linux IRQ16 (to leave room for ISA IRQs at 0-15).
140 * PCI IDSEL/INTPIN->INTLINE
141 * A B C D
142 */
143 {
144 {19, 0, 0, 0}, /* IDSEL 12 - SCSI */
145 { 0, 0, 0, 0}, /* IDSEL 13 - unused */
146 {18, 0, 0, 0}, /* IDSEL 14 - Enet 1 */
147 { 0, 0, 0, 0}, /* IDSEL 15 - unused */
148 {25, 26, 27, 28}, /* IDSEL 16 - PCI Slot 1P */
149 {26, 27, 28, 25}, /* IDSEL 17 - PCI Slot 2P */
150 {27, 28, 25, 26}, /* IDSEL 18 - PCI Slot 3P */
151 {26, 0, 0, 0}, /* IDSEL 19 - Enet 2 */
152 { 0, 0, 0, 0} /* IDSEL 20 - P2P Bridge */
153 };
154
155 const long min_idsel = 12, max_idsel = 20, irqs_per_slot = 4;
156 return PCI_IRQ_TABLE_LOOKUP;
157 }
158
159 static inline int
160 Genesis2_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin)
161 {
162 /* 2600
163 * Raven 31
164 * ISA 11
165 * SCSI 12 - IRQ3
166 * Univ 13
167 * eth 14 - IRQ2
168 * VGA 15 - IRQ4
169 * PMC1 16 - IRQ9,10,11,12 = PMC1 A-D
170 * PMC2 17 - IRQ12,9,10,11 = A-D
171 * SCSI2 18 - IRQ11
172 * eth2 19 - IRQ10
173 * PCIX 20 - IRQ9,10,11,12 = PCI A-D
174 */
175
176 /* 2400
177 * Hawk 31
178 * ISA 11
179 * Univ 13
180 * eth 14 - IRQ2
181 * PMC1 16 - IRQ9,10,11,12 = PMC A-D
182 * PMC2 17 - IRQ12,9,10,11 = PMC A-D
183 * PCIX 20 - IRQ9,10,11,12 = PMC A-D
184 */
185
186 /* 2300
187 * Raven 31
188 * ISA 11
189 * Univ 13
190 * eth 14 - IRQ2
191 * PMC1 16 - 9,10,11,12 = A-D
192 * PMC2 17 - 9,10,11,12 = B,C,D,A
193 */
194
195 static char pci_irq_table[][4] =
196 /*
197 * MPIC interrupts for various IDSEL values (MPIC IRQ0 =
198 * Linux IRQ16 (to leave room for ISA IRQs at 0-15).
199 * PCI IDSEL/INTPIN->INTLINE
200 * A B C D
201 */
202 {
203 {19, 0, 0, 0}, /* IDSEL 12 - SCSI */
204 { 0, 0, 0, 0}, /* IDSEL 13 - Universe PCI - VME */
205 {18, 0, 0, 0}, /* IDSEL 14 - Enet 1 */
206 { 0, 0, 0, 0}, /* IDSEL 15 - unused */
207 {25, 26, 27, 28}, /* IDSEL 16 - PCI/PMC Slot 1P */
208 {28, 25, 26, 27}, /* IDSEL 17 - PCI/PMC Slot 2P */
209 {27, 28, 25, 26}, /* IDSEL 18 - PCI Slot 3P */
210 {26, 0, 0, 0}, /* IDSEL 19 - Enet 2 */
211 {25, 26, 27, 28} /* IDSEL 20 - P2P Bridge */
212 };
213
214 const long min_idsel = 12, max_idsel = 20, irqs_per_slot = 4;
215 return PCI_IRQ_TABLE_LOOKUP;
216 }
217
218 #define MOTOROLA_CPUTYPE_REG 0x800
219 #define MOTOROLA_BASETYPE_REG 0x803
220 #define MPIC_RAVEN_ID 0x48010000
221 #define MPIC_HAWK_ID 0x48030000
222 #define MOT_PROC2_BIT 0x800
223
224 static u_char pplus_openpic_initsenses[] __initdata = {
225 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* MVME2600_INT_SIO */
226 (IRQ_SENSE_EDGE | IRQ_POLARITY_NEGATIVE),/*MVME2600_INT_FALCN_ECC_ERR */
227 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),/*MVME2600_INT_PCI_ETHERNET */
228 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* MVME2600_INT_PCI_SCSI */
229 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),/*MVME2600_INT_PCI_GRAPHICS */
230 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* MVME2600_INT_PCI_VME0 */
231 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* MVME2600_INT_PCI_VME1 */
232 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* MVME2600_INT_PCI_VME2 */
233 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* MVME2600_INT_PCI_VME3 */
234 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* MVME2600_INT_PCI_INTA */
235 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* MVME2600_INT_PCI_INTB */
236 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* MVME2600_INT_PCI_INTC */
237 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* MVME2600_INT_PCI_INTD */
238 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* MVME2600_INT_LM_SIG0 */
239 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* MVME2600_INT_LM_SIG1 */
240 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),
241 };
242
243 int mot_entry = -1;
244 int prep_keybd_present = 1;
245 int mot_multi = 0;
246
247 struct brd_info {
248 /* 0x100 mask assumes for Raven and Hawk boards that the level/edge
249 * are set */
250 int cpu_type;
251 /* 0x200 if this board has a Hawk chip. */
252 int base_type;
253 /* or'ed with 0x80 if this board should be checked for multi CPU */
254 int max_cpu;
255 const char *name;
256 int (*map_irq) (struct pci_dev *, unsigned char, unsigned char);
257 };
258 struct brd_info mot_info[] = {
259 {0x300, 0x00, 0x00, "MVME 2400", Genesis2_map_irq},
260 {0x1E0, 0xE0, 0x00, "Mesquite cPCI (MCP750)", mesquite_map_irq},
261 {0x1E0, 0xE1, 0x00, "Sitka cPCI (MCPN750)", sitka_map_irq},
262 {0x1E0, 0xE2, 0x00, "Mesquite cPCI (MCP750) w/ HAC", mesquite_map_irq},
263 {0x1E0, 0xF6, 0x80, "MTX Plus", MTXplus_map_irq},
264 {0x1E0, 0xF6, 0x81, "Dual MTX Plus", MTXplus_map_irq},
265 {0x1E0, 0xF7, 0x80, "MTX wo/ Parallel Port", MTX_map_irq},
266 {0x1E0, 0xF7, 0x81, "Dual MTX wo/ Parallel Port", MTX_map_irq},
267 {0x1E0, 0xF8, 0x80, "MTX w/ Parallel Port", MTX_map_irq},
268 {0x1E0, 0xF8, 0x81, "Dual MTX w/ Parallel Port", MTX_map_irq},
269 {0x1E0, 0xF9, 0x00, "MVME 2300", Genesis2_map_irq},
270 {0x1E0, 0xFA, 0x00, "MVME 2300SC/2600", Genesis2_map_irq},
271 {0x1E0, 0xFB, 0x00, "MVME 2600 with MVME712M", Genesis2_map_irq},
272 {0x1E0, 0xFC, 0x00, "MVME 2600/2700 with MVME761", Genesis2_map_irq},
273 {0x1E0, 0xFD, 0x80, "MVME 3600 with MVME712M", Genesis2_map_irq},
274 {0x1E0, 0xFD, 0x81, "MVME 4600 with MVME712M", Genesis2_map_irq},
275 {0x1E0, 0xFE, 0x80, "MVME 3600 with MVME761", Genesis2_map_irq},
276 {0x1E0, 0xFE, 0x81, "MVME 4600 with MVME761", Genesis2_map_irq},
277 {0x000, 0x00, 0x00, "", NULL}
278 };
279
280 void __init pplus_set_board_type(void)
281 {
282 unsigned char cpu_type;
283 unsigned char base_mod;
284 int entry;
285 unsigned short devid;
286 unsigned long *ProcInfo = NULL;
287
288 cpu_type = inb(MOTOROLA_CPUTYPE_REG) & 0xF0;
289 base_mod = inb(MOTOROLA_BASETYPE_REG);
290 early_read_config_word(0, 0, 0, PCI_VENDOR_ID, &devid);
291
292 for (entry = 0; mot_info[entry].cpu_type != 0; entry++) {
293 /* Check for Hawk chip */
294 if (mot_info[entry].cpu_type & 0x200) {
295 if (devid != PCI_DEVICE_ID_MOTOROLA_HAWK)
296 continue;
297 } else {
298 /* store the system config register for later use. */
299 ProcInfo =
300 (unsigned long *)ioremap(PPLUS_SYS_CONFIG_REG, 4);
301
302 /* Check non hawk boards */
303 if ((mot_info[entry].cpu_type & 0xff) != cpu_type)
304 continue;
305
306 if (mot_info[entry].base_type == 0) {
307 mot_entry = entry;
308 break;
309 }
310
311 if (mot_info[entry].base_type != base_mod)
312 continue;
313 }
314
315 if (!(mot_info[entry].max_cpu & 0x80)) {
316 mot_entry = entry;
317 break;
318 }
319
320 /* processor 1 not present and max processor zero indicated */
321 if ((*ProcInfo & MOT_PROC2_BIT)
322 && !(mot_info[entry].max_cpu & 0x7f)) {
323 mot_entry = entry;
324 break;
325 }
326
327 /* processor 1 present and max processor zero indicated */
328 if (!(*ProcInfo & MOT_PROC2_BIT)
329 && (mot_info[entry].max_cpu & 0x7f)) {
330 mot_entry = entry;
331 break;
332 }
333
334 /* Indicate to system if this is a multiprocessor board */
335 if (!(*ProcInfo & MOT_PROC2_BIT))
336 mot_multi = 1;
337 }
338
339 if (mot_entry == -1)
340 /* No particular cpu type found - assume Mesquite (MCP750) */
341 mot_entry = 1;
342
343 Motherboard_map_name = (unsigned char *)mot_info[mot_entry].name;
344 ppc_md.pci_map_irq = mot_info[mot_entry].map_irq;
345 }
346 void __init pplus_pib_init(void)
347 {
348 unsigned char reg;
349 unsigned short short_reg;
350
351 struct pci_dev *dev = NULL;
352
353 /*
354 * Perform specific configuration for the Via Tech or
355 * or Winbond PCI-ISA-Bridge part.
356 */
357 if ((dev = pci_get_device(PCI_VENDOR_ID_VIA,
358 PCI_DEVICE_ID_VIA_82C586_1, dev))) {
359 /*
360 * PPCBUG does not set the enable bits
361 * for the IDE device. Force them on here.
362 */
363 pci_read_config_byte(dev, 0x40, &reg);
364
365 reg |= 0x03; /* IDE: Chip Enable Bits */
366 pci_write_config_byte(dev, 0x40, reg);
367 }
368
369 if ((dev = pci_get_device(PCI_VENDOR_ID_VIA,
370 PCI_DEVICE_ID_VIA_82C586_2,
371 dev)) && (dev->devfn = 0x5a)) {
372 /* Force correct USB interrupt */
373 dev->irq = 11;
374 pci_write_config_byte(dev, PCI_INTERRUPT_LINE, dev->irq);
375 }
376
377 if ((dev = pci_get_device(PCI_VENDOR_ID_WINBOND,
378 PCI_DEVICE_ID_WINBOND_83C553, dev))) {
379 /* Clear PCI Interrupt Routing Control Register. */
380 short_reg = 0x0000;
381 pci_write_config_word(dev, 0x44, short_reg);
382 /* Route IDE interrupts to IRQ 14 */
383 reg = 0xEE;
384 pci_write_config_byte(dev, 0x43, reg);
385 }
386
387 if ((dev = pci_get_device(PCI_VENDOR_ID_WINBOND,
388 PCI_DEVICE_ID_WINBOND_82C105, dev))) {
389 /*
390 * Disable LEGIRQ mode so PCI INTS are routed
391 * directly to the 8259 and enable both channels
392 */
393 pci_write_config_dword(dev, 0x40, 0x10ff0033);
394
395 /* Force correct IDE interrupt */
396 dev->irq = 14;
397 pci_write_config_byte(dev, PCI_INTERRUPT_LINE, dev->irq);
398 }
399 pci_dev_put(dev);
400 }
401
402 void __init pplus_set_VIA_IDE_legacy(void)
403 {
404 unsigned short vend, dev;
405
406 early_read_config_word(0, 0, PCI_DEVFN(0xb, 1), PCI_VENDOR_ID, &vend);
407 early_read_config_word(0, 0, PCI_DEVFN(0xb, 1), PCI_DEVICE_ID, &dev);
408
409 if ((vend == PCI_VENDOR_ID_VIA) &&
410 (dev == PCI_DEVICE_ID_VIA_82C586_1)) {
411 unsigned char temp;
412
413 /* put back original "standard" port base addresses */
414 early_write_config_dword(0, 0, PCI_DEVFN(0xb, 1),
415 PCI_BASE_ADDRESS_0, 0x1f1);
416 early_write_config_dword(0, 0, PCI_DEVFN(0xb, 1),
417 PCI_BASE_ADDRESS_1, 0x3f5);
418 early_write_config_dword(0, 0, PCI_DEVFN(0xb, 1),
419 PCI_BASE_ADDRESS_2, 0x171);
420 early_write_config_dword(0, 0, PCI_DEVFN(0xb, 1),
421 PCI_BASE_ADDRESS_3, 0x375);
422 early_write_config_dword(0, 0, PCI_DEVFN(0xb, 1),
423 PCI_BASE_ADDRESS_4, 0xcc01);
424
425 /* put into legacy mode */
426 early_read_config_byte(0, 0, PCI_DEVFN(0xb, 1), PCI_CLASS_PROG,
427 &temp);
428 temp &= ~0x05;
429 early_write_config_byte(0, 0, PCI_DEVFN(0xb, 1), PCI_CLASS_PROG,
430 temp);
431 }
432 }
433
434 void pplus_set_VIA_IDE_native(void)
435 {
436 unsigned short vend, dev;
437
438 early_read_config_word(0, 0, PCI_DEVFN(0xb, 1), PCI_VENDOR_ID, &vend);
439 early_read_config_word(0, 0, PCI_DEVFN(0xb, 1), PCI_DEVICE_ID, &dev);
440
441 if ((vend == PCI_VENDOR_ID_VIA) &&
442 (dev == PCI_DEVICE_ID_VIA_82C586_1)) {
443 unsigned char temp;
444
445 /* put into native mode */
446 early_read_config_byte(0, 0, PCI_DEVFN(0xb, 1), PCI_CLASS_PROG,
447 &temp);
448 temp |= 0x05;
449 early_write_config_byte(0, 0, PCI_DEVFN(0xb, 1), PCI_CLASS_PROG,
450 temp);
451 }
452 }
453
454 void __init pplus_pcibios_fixup(void)
455 {
456
457 unsigned char reg;
458 unsigned short devid;
459 unsigned char base_mod;
460
461 printk(KERN_INFO "Setting PCI interrupts for a \"%s\"\n",
462 Motherboard_map_name);
463
464 /* Setup the Winbond or Via PIB */
465 pplus_pib_init();
466
467 /* Set up floppy in PS/2 mode */
468 outb(0x09, SIO_CONFIG_RA);
469 reg = inb(SIO_CONFIG_RD);
470 reg = (reg & 0x3F) | 0x40;
471 outb(reg, SIO_CONFIG_RD);
472 outb(reg, SIO_CONFIG_RD); /* Have to write twice to change! */
473
474 /* This is a hack. If this is a 2300 or 2400 mot board then there is
475 * no keyboard controller and we have to indicate that.
476 */
477
478 early_read_config_word(0, 0, 0, PCI_VENDOR_ID, &devid);
479 base_mod = inb(MOTOROLA_BASETYPE_REG);
480 if ((devid == PCI_DEVICE_ID_MOTOROLA_HAWK) ||
481 (base_mod == 0xF9) || (base_mod == 0xFA) || (base_mod == 0xE1))
482 prep_keybd_present = 0;
483 }
484
485 void __init pplus_find_bridges(void)
486 {
487 struct pci_controller *hose;
488
489 hose = pcibios_alloc_controller();
490 if (!hose)
491 return;
492
493 hose->first_busno = 0;
494 hose->last_busno = 0xff;
495
496 hose->pci_mem_offset = PREP_ISA_MEM_BASE;
497 hose->io_base_virt = (void *)PREP_ISA_IO_BASE;
498
499 pci_init_resource(&hose->io_resource, PPLUS_PCI_IO_START,
500 PPLUS_PCI_IO_END, IORESOURCE_IO, "PCI host bridge");
501 pci_init_resource(&hose->mem_resources[0], PPLUS_PROC_PCI_MEM_START,
502 PPLUS_PROC_PCI_MEM_END, IORESOURCE_MEM,
503 "PCI host bridge");
504
505 hose->io_space.start = PPLUS_PCI_IO_START;
506 hose->io_space.end = PPLUS_PCI_IO_END;
507 hose->mem_space.start = PPLUS_PCI_MEM_START;
508 hose->mem_space.end = PPLUS_PCI_MEM_END - HAWK_MPIC_SIZE;
509
510 if (hawk_init(hose, PPLUS_HAWK_PPC_REG_BASE, PPLUS_PROC_PCI_MEM_START,
511 PPLUS_PROC_PCI_MEM_END - HAWK_MPIC_SIZE,
512 PPLUS_PROC_PCI_IO_START, PPLUS_PROC_PCI_IO_END,
513 PPLUS_PROC_PCI_MEM_END - HAWK_MPIC_SIZE + 1)
514 != 0) {
515 printk(KERN_CRIT "Could not initialize host bridge\n");
516
517 }
518
519 pplus_set_VIA_IDE_legacy();
520
521 hose->last_busno = pciauto_bus_scan(hose, hose->first_busno);
522
523 ppc_md.pcibios_fixup = pplus_pcibios_fixup;
524 ppc_md.pci_swizzle = common_swizzle;
525 }
526
527 static int pplus_show_cpuinfo(struct seq_file *m)
528 {
529 seq_printf(m, "vendor\t\t: Motorola MCG\n");
530 seq_printf(m, "machine\t\t: %s\n", Motherboard_map_name);
531
532 return 0;
533 }
534
535 static void __init pplus_setup_arch(void)
536 {
537 struct pci_controller *hose;
538
539 if (ppc_md.progress)
540 ppc_md.progress("pplus_setup_arch: enter", 0);
541
542 /* init to some ~sane value until calibrate_delay() runs */
543 loops_per_jiffy = 50000000;
544
545 if (ppc_md.progress)
546 ppc_md.progress("pplus_setup_arch: find_bridges", 0);
547
548 /* Setup PCI host bridge */
549 pplus_find_bridges();
550
551 hose = pci_bus_to_hose(0);
552 isa_io_base = (ulong) hose->io_base_virt;
553
554 if (ppc_md.progress)
555 ppc_md.progress("pplus_setup_arch: set_board_type", 0);
556
557 pplus_set_board_type();
558
559 /* Enable L2. Assume we don't need to flush -- Cort */
560 *(unsigned char *)(PPLUS_L2_CONTROL_REG) |= 3;
561
562 #ifdef CONFIG_BLK_DEV_INITRD
563 if (initrd_start)
564 ROOT_DEV = Root_RAM0;
565 else
566 #endif
567 #ifdef CONFIG_ROOT_NFS
568 ROOT_DEV = Root_NFS;
569 #else
570 ROOT_DEV = Root_SDA2;
571 #endif
572
573 printk(KERN_INFO "Motorola PowerPlus Platform\n");
574 printk(KERN_INFO
575 "Port by MontaVista Software, Inc. (source@mvista.com)\n");
576
577 #ifdef CONFIG_VGA_CONSOLE
578 /* remap the VGA memory */
579 vgacon_remap_base = (unsigned long)ioremap(PPLUS_ISA_MEM_BASE,
580 0x08000000);
581 conswitchp = &vga_con;
582 #endif
583 #ifdef CONFIG_PPCBUG_NVRAM
584 /* Read in NVRAM data */
585 init_prep_nvram();
586
587 /* if no bootargs, look in NVRAM */
588 if (cmd_line[0] == '\0') {
589 char *bootargs;
590 bootargs = prep_nvram_get_var("bootargs");
591 if (bootargs != NULL) {
592 strcpy(cmd_line, bootargs);
593 /* again.. */
594 strcpy(boot_command_line, cmd_line);
595 }
596 }
597 #endif
598 if (ppc_md.progress)
599 ppc_md.progress("pplus_setup_arch: exit", 0);
600 }
601
602 static void pplus_restart(char *cmd)
603 {
604 unsigned long i = 10000;
605
606 local_irq_disable();
607
608 /* set VIA IDE controller into native mode */
609 pplus_set_VIA_IDE_native();
610
611 /* set exception prefix high - to the prom */
612 _nmask_and_or_msr(0, MSR_IP);
613
614 /* make sure bit 0 (reset) is a 0 */
615 outb(inb(0x92) & ~1L, 0x92);
616 /* signal a reset to system control port A - soft reset */
617 outb(inb(0x92) | 1, 0x92);
618
619 while (i != 0)
620 i++;
621 panic("restart failed\n");
622 }
623
624 static void pplus_halt(void)
625 {
626 /* set exception prefix high - to the prom */
627 _nmask_and_or_msr(MSR_EE, MSR_IP);
628
629 /* make sure bit 0 (reset) is a 0 */
630 outb(inb(0x92) & ~1L, 0x92);
631 /* signal a reset to system control port A - soft reset */
632 outb(inb(0x92) | 1, 0x92);
633
634 while (1) ;
635 /*
636 * Not reached
637 */
638 }
639
640 static void pplus_power_off(void)
641 {
642 pplus_halt();
643 }
644
645 static void __init pplus_init_IRQ(void)
646 {
647 int i;
648
649 if (ppc_md.progress)
650 ppc_md.progress("init_irq: enter", 0);
651
652 OpenPIC_InitSenses = pplus_openpic_initsenses;
653 OpenPIC_NumInitSenses = sizeof(pplus_openpic_initsenses);
654
655 if (OpenPIC_Addr != NULL) {
656
657 openpic_set_sources(0, 16, OpenPIC_Addr + 0x10000);
658 openpic_init(NUM_8259_INTERRUPTS);
659 openpic_hookup_cascade(NUM_8259_INTERRUPTS, "82c59 cascade",
660 i8259_irq);
661 ppc_md.get_irq = openpic_get_irq;
662 }
663
664 i8259_init(0, 0);
665
666 if (ppc_md.progress)
667 ppc_md.progress("init_irq: exit", 0);
668 }
669
670 #ifdef CONFIG_SMP
671 /* PowerPlus (MTX) support */
672 static int __init smp_pplus_probe(void)
673 {
674 extern int mot_multi;
675
676 if (mot_multi) {
677 openpic_request_IPIs();
678 smp_hw_index[1] = 1;
679 return 2;
680 }
681
682 return 1;
683 }
684
685 static void __init smp_pplus_kick_cpu(int nr)
686 {
687 *(unsigned long *)KERNELBASE = nr;
688 asm volatile ("dcbf 0,%0"::"r" (KERNELBASE):"memory");
689 printk(KERN_INFO "CPU1 reset, waiting\n");
690 }
691
692 static void __init smp_pplus_setup_cpu(int cpu_nr)
693 {
694 if (OpenPIC_Addr)
695 do_openpic_setup_cpu();
696 }
697
698 static struct smp_ops_t pplus_smp_ops = {
699 smp_openpic_message_pass,
700 smp_pplus_probe,
701 smp_pplus_kick_cpu,
702 smp_pplus_setup_cpu,
703 .give_timebase = smp_generic_give_timebase,
704 .take_timebase = smp_generic_take_timebase,
705 };
706 #endif /* CONFIG_SMP */
707
708 #ifdef DUMP_DBATS
709 static void print_dbat(int idx, u32 bat)
710 {
711
712 char str[64];
713
714 sprintf(str, "DBAT%c%c = 0x%08x\n",
715 (char)((idx - DBAT0U) / 2) + '0', (idx & 1) ? 'L' : 'U', bat);
716 ppc_md.progress(str, 0);
717 }
718
719 #define DUMP_DBAT(x) \
720 do { \
721 u32 __temp = mfspr(x);\
722 print_dbat(x, __temp); \
723 } while (0)
724
725 static void dump_dbats(void)
726 {
727 if (ppc_md.progress) {
728 DUMP_DBAT(DBAT0U);
729 DUMP_DBAT(DBAT0L);
730 DUMP_DBAT(DBAT1U);
731 DUMP_DBAT(DBAT1L);
732 DUMP_DBAT(DBAT2U);
733 DUMP_DBAT(DBAT2L);
734 DUMP_DBAT(DBAT3U);
735 DUMP_DBAT(DBAT3L);
736 }
737 }
738 #endif
739
740 static unsigned long __init pplus_find_end_of_memory(void)
741 {
742 unsigned long total;
743
744 if (ppc_md.progress)
745 ppc_md.progress("pplus_find_end_of_memory", 0);
746
747 #ifdef DUMP_DBATS
748 dump_dbats();
749 #endif
750
751 total = hawk_get_mem_size(PPLUS_HAWK_SMC_BASE);
752 return (total);
753 }
754
755 static void __init pplus_map_io(void)
756 {
757 io_block_mapping(PPLUS_ISA_IO_BASE, PPLUS_ISA_IO_BASE, 0x10000000,
758 _PAGE_IO);
759 io_block_mapping(0xfef80000, 0xfef80000, 0x00080000, _PAGE_IO);
760 }
761
762 static void __init pplus_init2(void)
763 {
764 #ifdef CONFIG_NVRAM
765 request_region(PREP_NVRAM_AS0, 0x8, "nvram");
766 #endif
767 request_region(0x20, 0x20, "pic1");
768 request_region(0xa0, 0x20, "pic2");
769 request_region(0x00, 0x20, "dma1");
770 request_region(0x40, 0x20, "timer");
771 request_region(0x80, 0x10, "dma page reg");
772 request_region(0xc0, 0x20, "dma2");
773 }
774
775 /*
776 * Set BAT 2 to access 0x8000000 so progress messages will work and set BAT 3
777 * to 0xf0000000 to access Falcon/Raven or Hawk registers
778 */
779 static __inline__ void pplus_set_bat(void)
780 {
781 /* wait for all outstanding memory accesses to complete */
782 mb();
783
784 /* setup DBATs */
785 mtspr(SPRN_DBAT2U, 0x80001ffe);
786 mtspr(SPRN_DBAT2L, 0x8000002a);
787 mtspr(SPRN_DBAT3U, 0xf0001ffe);
788 mtspr(SPRN_DBAT3L, 0xf000002a);
789
790 /* wait for updates */
791 mb();
792 }
793
794 void __init
795 platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
796 unsigned long r6, unsigned long r7)
797 {
798 parse_bootinfo(find_bootinfo());
799
800 /* Map in board regs, etc. */
801 pplus_set_bat();
802
803 isa_io_base = PREP_ISA_IO_BASE;
804 isa_mem_base = PREP_ISA_MEM_BASE;
805 pci_dram_offset = PREP_PCI_DRAM_OFFSET;
806 ISA_DMA_THRESHOLD = 0x00ffffff;
807 DMA_MODE_READ = 0x44;
808 DMA_MODE_WRITE = 0x48;
809 ppc_do_canonicalize_irqs = 1;
810
811 ppc_md.setup_arch = pplus_setup_arch;
812 ppc_md.show_cpuinfo = pplus_show_cpuinfo;
813 ppc_md.init_IRQ = pplus_init_IRQ;
814 /* this gets changed later on if we have an OpenPIC -- Cort */
815 ppc_md.get_irq = i8259_irq;
816 ppc_md.init = pplus_init2;
817
818 ppc_md.restart = pplus_restart;
819 ppc_md.power_off = pplus_power_off;
820 ppc_md.halt = pplus_halt;
821
822 TODC_INIT(TODC_TYPE_MK48T59, PREP_NVRAM_AS0, PREP_NVRAM_AS1,
823 PREP_NVRAM_DATA, 8);
824
825 ppc_md.time_init = todc_time_init;
826 ppc_md.set_rtc_time = todc_set_rtc_time;
827 ppc_md.get_rtc_time = todc_get_rtc_time;
828 ppc_md.calibrate_decr = todc_calibrate_decr;
829 ppc_md.nvram_read_val = todc_m48txx_read_val;
830 ppc_md.nvram_write_val = todc_m48txx_write_val;
831
832 ppc_md.find_end_of_memory = pplus_find_end_of_memory;
833 ppc_md.setup_io_mappings = pplus_map_io;
834
835 #ifdef CONFIG_SERIAL_TEXT_DEBUG
836 ppc_md.progress = gen550_progress;
837 #endif /* CONFIG_SERIAL_TEXT_DEBUG */
838 #ifdef CONFIG_KGDB
839 ppc_md.kgdb_map_scc = gen550_kgdb_map_scc;
840 #endif
841 #ifdef CONFIG_SMP
842 smp_ops = &pplus_smp_ops;
843 #endif /* CONFIG_SMP */
844 }
Mirror for ia64_pv_ops.git