arch/ppc/platforms/rpx8260.h

   1 /*
   2  * A collection of structures, addresses, and values associated with
   3  * the Embedded Planet RPX6 (or RPX Super) MPC8260 board.
   4  * Copied from the RPX-Classic and SBS8260 stuff.
   5  *
   6  * Copyright (c) 2001 Dan Malek <dan@embeddededge.com>
   7  */
   8 #ifdef __KERNEL__
   9 #ifndef __ASM_PLATFORMS_RPX8260_H__
  10 #define __ASM_PLATFORMS_RPX8260_H__
  11
  12 /* A Board Information structure that is given to a program when
  13  * prom starts it up.
  14  */
  15 typedef struct bd_info {
  16         unsigned int    bi_memstart;    /* Memory start address */
  17         unsigned int    bi_memsize;     /* Memory (end) size in bytes */
  18         unsigned int    bi_nvsize;      /* NVRAM size in bytes (can be 0) */
  19         unsigned int    bi_intfreq;     /* Internal Freq, in Hz */
  20         unsigned int    bi_busfreq;     /* Bus Freq, in MHz */
  21         unsigned int    bi_cpmfreq;     /* CPM Freq, in MHz */
  22         unsigned int    bi_brgfreq;     /* BRG Freq, in MHz */
  23         unsigned int    bi_vco;         /* VCO Out from PLL */
  24         unsigned int    bi_baudrate;    /* Default console baud rate */
  25         unsigned int    bi_immr;        /* IMMR when called from boot rom */
  26         unsigned char   bi_enetaddr[6];
  27 } bd_t;
  28
  29 extern bd_t m8xx_board_info;
  30
  31 /* Memory map is configured by the PROM startup.
  32  * We just map a few things we need.  The CSR is actually 4 byte-wide
  33  * registers that can be accessed as 8-, 16-, or 32-bit values.
  34  */
  35 #define CPM_MAP_ADDR            ((uint)0xf0000000)
  36 #define RPX_CSR_ADDR            ((uint)0xfa000000)
  37 #define RPX_CSR_SIZE            ((uint)(512 * 1024))
  38 #define RPX_NVRTC_ADDR          ((uint)0xfa080000)
  39 #define RPX_NVRTC_SIZE          ((uint)(512 * 1024))
  40
  41 /* The RPX6 has 16, byte wide control/status registers.
  42  * Not all are used (yet).
  43  */
  44 extern volatile u_char *rpx6_csr_addr;
  45
  46 /* Things of interest in the CSR.
  47 */
  48 #define BCSR0_ID_MASK           ((u_char)0xf0)          /* Read only */
  49 #define BCSR0_SWITCH_MASK       ((u_char)0x0f)          /* Read only */
  50 #define BCSR1_XCVR_SMC1         ((u_char)0x80)
  51 #define BCSR1_XCVR_SMC2         ((u_char)0x40)
  52 #define BCSR2_FLASH_WENABLE     ((u_char)0x20)
  53 #define BCSR2_NVRAM_ENABLE      ((u_char)0x10)
  54 #define BCSR2_ALT_IRQ2          ((u_char)0x08)
  55 #define BCSR2_ALT_IRQ3          ((u_char)0x04)
  56 #define BCSR2_PRST              ((u_char)0x02)          /* Force reset */
  57 #define BCSR2_ENPRST            ((u_char)0x01)          /* Enable POR */
  58 #define BCSR3_MODCLK_MASK       ((u_char)0xe0)
  59 #define BCSR3_ENCLKHDR          ((u_char)0x10)
  60 #define BCSR3_LED5              ((u_char)0x04)          /* 0 == on */
  61 #define BCSR3_LED6              ((u_char)0x02)          /* 0 == on */
  62 #define BCSR3_LED7              ((u_char)0x01)          /* 0 == on */
  63 #define BCSR4_EN_PHY            ((u_char)0x80)          /* Enable PHY */
  64 #define BCSR4_EN_MII            ((u_char)0x40)          /* Enable PHY */
  65 #define BCSR4_MII_READ          ((u_char)0x04)
  66 #define BCSR4_MII_MDC           ((u_char)0x02)
  67 #define BCSR4_MII_MDIO          ((u_char)0x01)
  68 #define BCSR13_FETH_IRQMASK     ((u_char)0xf0)
  69 #define BCSR15_FETH_IRQ         ((u_char)0x20)
  70
  71 #define PHY_INTERRUPT   SIU_INT_IRQ7
  72
  73 /* For our show_cpuinfo hooks. */
  74 #define CPUINFO_VENDOR          "Embedded Planet"
  75 #define CPUINFO_MACHINE         "EP8260 PowerPC"
  76
  77 /* Warm reset vector. */
  78 #define BOOTROM_RESTART_ADDR    ((uint)0xfff00104)
  79
  80 #endif /* __ASM_PLATFORMS_RPX8260_H__ */
  81 #endif /* __KERNEL__ */