arch/ppc/platforms/sandpoint.c

   1 /*
   2  * Board setup routines for the Motorola SPS Sandpoint Test Platform.
   3  *
   4  * Author: Mark A. Greer
   5  *       mgreer@mvista.com
   6  *
   7  * 2000-2003 (c) MontaVista Software, Inc.  This file is licensed under
   8  * the terms of the GNU General Public License version 2.  This program
   9  * is licensed "as is" without any warranty of any kind, whether express
  10  * or implied.
  11  */
  12
  13 /*
  14  * This file adds support for the Motorola SPS Sandpoint Test Platform.
  15  * These boards have a PPMC slot for the processor so any combination
  16  * of cpu and host bridge can be attached.  This port is for an 8240 PPMC
  17  * module from Motorola SPS and other closely related cpu/host bridge
  18  * combinations (e.g., 750/755/7400 with MPC107 host bridge).
  19  * The sandpoint itself has a Windbond 83c553 (PCI-ISA bridge, 2 DMA ctlrs, 2
  20  * cascaded 8259 interrupt ctlrs, 8254 Timer/Counter, and an IDE ctlr), a
  21  * National 87308 (RTC, 2 UARTs, Keyboard & mouse ctlrs, and a floppy ctlr),
  22  * and 4 PCI slots (only 2 of which are usable; the other 2 are keyed for 3.3V
  23  * but are really 5V).
  24  *
  25  * The firmware on the sandpoint is called DINK (not my acronym :).  This port
  26  * depends on DINK to do some basic initialization (e.g., initialize the memory
  27  * ctlr) and to ensure that the processor is using MAP B (CHRP map).
  28  *
  29  * The switch settings for the Sandpoint board MUST be as follows:
  30  *      S3: down
  31  *      S4: up
  32  *      S5: up
  33  *      S6: down
  34  *
  35  * 'down' is in the direction from the PCI slots towards the PPMC slot;
  36  * 'up' is in the direction from the PPMC slot towards the PCI slots.
  37  * Be careful, the way the sandpoint board is installed in XT chasses will
  38  * make the directions reversed.
  39  *
  40  * Since Motorola listened to our suggestions for improvement, we now have
  41  * the Sandpoint X3 board.  All of the PCI slots are available, it uses
  42  * the serial interrupt interface (just a hardware thing we need to
  43  * configure properly).
  44  *
  45  * Use the default X3 switch settings.  The interrupts are then:
  46  *              EPIC    Source
  47  *                0     SIOINT          (8259, active low)
  48  *                1     PCI #1
  49  *                2     PCI #2
  50  *                3     PCI #3
  51  *                4     PCI #4
  52  *                7     Winbond INTC    (IDE interrupt)
  53  *                8     Winbond INTD    (IDE interrupt)
  54  *
  55  *
  56  * Motorola has finally released a version of DINK32 that correctly
  57  * (seemingly) initializes the memory controller correctly, regardless
  58  * of the amount of memory in the system.  Once a method of determining
  59  * what version of DINK initializes the system for us, if applicable, is
  60  * found, we can hopefully stop hardcoding 32MB of RAM.
  61  */
  62
  63 #include <linux/stddef.h>
  64 #include <linux/kernel.h>
  65 #include <linux/init.h>
  66 #include <linux/errno.h>
  67 #include <linux/reboot.h>
  68 #include <linux/pci.h>
  69 #include <linux/kdev_t.h>
  70 #include <linux/major.h>
  71 #include <linux/initrd.h>
  72 #include <linux/console.h>
  73 #include <linux/delay.h>
  74 #include <linux/seq_file.h>
  75 #include <linux/root_dev.h>
  76 #include <linux/serial.h>
  77 #include <linux/tty.h>  /* for linux/serial_core.h */
  78 #include <linux/serial_core.h>
  79 #include <linux/serial_8250.h>
  80
  81 #include <asm/system.h>
  82 #include <asm/pgtable.h>
  83 #include <asm/page.h>
  84 #include <asm/time.h>
  85 #include <asm/dma.h>
  86 #include <asm/io.h>
  87 #include <asm/machdep.h>
  88 #include <asm/prom.h>
  89 #include <asm/smp.h>
  90 #include <asm/vga.h>
  91 #include <asm/open_pic.h>
  92 #include <asm/i8259.h>
  93 #include <asm/todc.h>
  94 #include <asm/bootinfo.h>
  95 #include <asm/mpc10x.h>
  96 #include <asm/pci-bridge.h>
  97 #include <asm/kgdb.h>
  98 #include <asm/ppc_sys.h>
  99
 100 #include "sandpoint.h"
 101
 102 /* Set non-zero if an X2 Sandpoint detected. */
 103 static int sandpoint_is_x2;
 104
 105 unsigned char __res[sizeof(bd_t)];
 106
 107 static void sandpoint_halt(void);
 108 static void sandpoint_probe_type(void);
 109
 110 /*
 111  * Define all of the IRQ senses and polarities.  Taken from the
 112  * Sandpoint X3 User's manual.
 113  */
 114 static u_char sandpoint_openpic_initsenses[] __initdata = {
 115         (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),      /* 0: SIOINT */
 116         (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),      /* 2: PCI Slot 1 */
 117         (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),      /* 3: PCI Slot 2 */
 118         (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),      /* 4: PCI Slot 3 */
 119         (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),      /* 5: PCI Slot 4 */
 120         (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),      /* 8: IDE (INT C) */
 121         (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE)       /* 9: IDE (INT D) */
 122 };
 123
 124 /*
 125  * Motorola SPS Sandpoint interrupt routing.
 126  */
 127 static inline int
 128 x3_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin)
 129 {
 130         static char pci_irq_table[][4] =
 131         /*
 132          *      PCI IDSEL/INTPIN->INTLINE
 133          *         A   B   C   D
 134          */
 135         {
 136                 { 16,  0,  0,  0 },     /* IDSEL 11 - i8259 on Winbond */
 137                 {  0,  0,  0,  0 },     /* IDSEL 12 - unused */
 138                 { 18, 21, 20, 19 },     /* IDSEL 13 - PCI slot 1 */
 139                 { 19, 18, 21, 20 },     /* IDSEL 14 - PCI slot 2 */
 140                 { 20, 19, 18, 21 },     /* IDSEL 15 - PCI slot 3 */
 141                 { 21, 20, 19, 18 },     /* IDSEL 16 - PCI slot 4 */
 142         };
 143
 144         const long min_idsel = 11, max_idsel = 16, irqs_per_slot = 4;
 145         return PCI_IRQ_TABLE_LOOKUP;
 146 }
 147
 148 static inline int
 149 x2_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin)
 150 {
 151         static char pci_irq_table[][4] =
 152         /*
 153          *      PCI IDSEL/INTPIN->INTLINE
 154          *         A   B   C   D
 155          */
 156         {
 157                 { 18,  0,  0,  0 },     /* IDSEL 11 - i8259 on Windbond */
 158                 {  0,  0,  0,  0 },     /* IDSEL 12 - unused */
 159                 { 16, 17, 18, 19 },     /* IDSEL 13 - PCI slot 1 */
 160                 { 17, 18, 19, 16 },     /* IDSEL 14 - PCI slot 2 */
 161                 { 18, 19, 16, 17 },     /* IDSEL 15 - PCI slot 3 */
 162                 { 19, 16, 17, 18 },     /* IDSEL 16 - PCI slot 4 */
 163         };
 164
 165         const long min_idsel = 11, max_idsel = 16, irqs_per_slot = 4;
 166         return PCI_IRQ_TABLE_LOOKUP;
 167 }
 168
 169 static void __init
 170 sandpoint_setup_winbond_83553(struct pci_controller *hose)
 171 {
 172         int             devfn;
 173
 174         /*
 175          * Route IDE interrupts directly to the 8259's IRQ 14 & 15.
 176          * We can't route the IDE interrupt to PCI INTC# or INTD# because those
 177          * woule interfere with the PMC's INTC# and INTD# lines.
 178          */
 179         /*
 180          * Winbond Fcn 0
 181          */
 182         devfn = PCI_DEVFN(11,0);
 183
 184         early_write_config_byte(hose,
 185                                 0,
 186                                 devfn,
 187                                 0x43, /* IDE Interrupt Routing Control */
 188                                 0xef);
 189         early_write_config_word(hose,
 190                                 0,
 191                                 devfn,
 192                                 0x44, /* PCI Interrupt Routing Control */
 193                                 0x0000);
 194
 195         /* Want ISA memory cycles to be forwarded to PCI bus */
 196         early_write_config_byte(hose,
 197                                 0,
 198                                 devfn,
 199                                 0x48, /* ISA-to-PCI Addr Decoder Control */
 200                                 0xf0);
 201
 202         /* Enable Port 92.  */
 203         early_write_config_byte(hose,
 204                                 0,
 205                                 devfn,
 206                                 0x4e,   /* AT System Control Register */
 207                                 0x06);
 208         /*
 209          * Winbond Fcn 1
 210          */
 211         devfn = PCI_DEVFN(11,1);
 212
 213         /* Put IDE controller into native mode. */
 214         early_write_config_byte(hose,
 215                                 0,
 216                                 devfn,
 217                                 0x09,   /* Programming interface Register */
 218                                 0x8f);
 219
 220         /* Init IRQ routing, enable both ports, disable fast 16 */
 221         early_write_config_dword(hose,
 222                                 0,
 223                                 devfn,
 224                                 0x40,   /* IDE Control/Status Register */
 225                                 0x00ff0011);
 226         return;
 227 }
 228
 229 /* On the sandpoint X2, we must avoid sending configuration cycles to
 230  * device #12 (IDSEL addr = AD12).
 231  */
 232 static int
 233 x2_exclude_device(u_char bus, u_char devfn)
 234 {
 235         if ((bus == 0) && (PCI_SLOT(devfn) == SANDPOINT_HOST_BRIDGE_IDSEL))
 236                 return PCIBIOS_DEVICE_NOT_FOUND;
 237         else
 238                 return PCIBIOS_SUCCESSFUL;
 239 }
 240
 241 static void __init
 242 sandpoint_find_bridges(void)
 243 {
 244         struct pci_controller   *hose;
 245
 246         hose = pcibios_alloc_controller();
 247
 248         if (!hose)
 249                 return;
 250
 251         hose->first_busno = 0;
 252         hose->last_busno = 0xff;
 253
 254         if (mpc10x_bridge_init(hose,
 255                                MPC10X_MEM_MAP_B,
 256                                MPC10X_MEM_MAP_B,
 257                                MPC10X_MAPB_EUMB_BASE) == 0) {
 258
 259                 /* Do early winbond init, then scan PCI bus */
 260                 sandpoint_setup_winbond_83553(hose);
 261                 hose->last_busno = pciauto_bus_scan(hose, hose->first_busno);
 262
 263                 ppc_md.pcibios_fixup = NULL;
 264                 ppc_md.pcibios_fixup_bus = NULL;
 265                 ppc_md.pci_swizzle = common_swizzle;
 266                 if (sandpoint_is_x2) {
 267                         ppc_md.pci_map_irq = x2_map_irq;
 268                         ppc_md.pci_exclude_device = x2_exclude_device;
 269                 } else
 270                         ppc_md.pci_map_irq = x3_map_irq;
 271         }
 272         else {
 273                 if (ppc_md.progress)
 274                         ppc_md.progress("Bridge init failed", 0x100);
 275                 printk("Host bridge init failed\n");
 276         }
 277
 278         return;
 279 }
 280
 281 static void __init
 282 sandpoint_setup_arch(void)
 283 {
 284         /* Probe for Sandpoint model */
 285         sandpoint_probe_type();
 286         if (sandpoint_is_x2)
 287                 epic_serial_mode = 0;
 288
 289         loops_per_jiffy = 100000000 / HZ;
 290
 291 #ifdef CONFIG_BLK_DEV_INITRD
 292         if (initrd_start)
 293                 ROOT_DEV = Root_RAM0;
 294         else
 295 #endif
 296 #ifdef  CONFIG_ROOT_NFS
 297                 ROOT_DEV = Root_NFS;
 298 #else
 299                 ROOT_DEV = Root_HDA1;
 300 #endif
 301
 302         /* Lookup PCI host bridges */
 303         sandpoint_find_bridges();
 304
 305         if (strncmp (cur_ppc_sys_spec->ppc_sys_name, "8245", 4) == 0)
 306         {
 307                 bd_t *bp = (bd_t *)__res;
 308                 struct plat_serial8250_port *pdata;
 309
 310                 pdata = (struct plat_serial8250_port *) ppc_sys_get_pdata(MPC10X_UART0);
 311                 if (pdata)
 312                 {
 313                         pdata[0].uartclk = bp->bi_busfreq;
 314                 }
 315
 316 #ifdef CONFIG_SANDPOINT_ENABLE_UART1
 317                 pdata = (struct plat_serial8250_port *) ppc_sys_get_pdata(MPC10X_UART1);
 318                 if (pdata)
 319                 {
 320                         pdata[0].uartclk = bp->bi_busfreq;
 321                 }
 322 #else
 323                 ppc_sys_device_remove(MPC10X_UART1);
 324 #endif
 325         }
 326
 327         printk(KERN_INFO "Motorola SPS Sandpoint Test Platform\n");
 328         printk(KERN_INFO "Port by MontaVista Software, Inc. (source@mvista.com)\n");
 329
 330         /* DINK32 12.3 and below do not correctly enable any caches.
 331          * We will do this now with good known values.  Future versions
 332          * of DINK32 are supposed to get this correct.
 333          */
 334         if (cpu_has_feature(CPU_FTR_SPEC7450))
 335                 /* 745x is different.  We only want to pass along enable. */
 336                 _set_L2CR(L2CR_L2E);
 337         else if (cpu_has_feature(CPU_FTR_L2CR))
 338                 /* All modules have 1MB of L2.  We also assume that an
 339                  * L2 divisor of 3 will work.
 340                  */
 341                 _set_L2CR(L2CR_L2E | L2CR_L2SIZ_1MB | L2CR_L2CLK_DIV3
 342                                 | L2CR_L2RAM_PIPE | L2CR_L2OH_1_0 | L2CR_L2DF);
 343 #if 0
 344         /* Untested right now. */
 345         if (cpu_has_feature(CPU_FTR_L3CR)) {
 346                 /* Magic value. */
 347                 _set_L3CR(0x8f032000);
 348         }
 349 #endif
 350 }
 351
 352 #define SANDPOINT_87308_CFG_ADDR                0x15c
 353 #define SANDPOINT_87308_CFG_DATA                0x15d
 354
 355 #define SANDPOINT_87308_CFG_INB(addr, byte) {                           \
 356         outb((addr), SANDPOINT_87308_CFG_ADDR);                         \
 357         (byte) = inb(SANDPOINT_87308_CFG_DATA);                         \
 358 }
 359
 360 #define SANDPOINT_87308_CFG_OUTB(addr, byte) {                          \
 361         outb((addr), SANDPOINT_87308_CFG_ADDR);                         \
 362         outb((byte), SANDPOINT_87308_CFG_DATA);                         \
 363 }
 364
 365 #define SANDPOINT_87308_SELECT_DEV(dev_num) {                           \
 366         SANDPOINT_87308_CFG_OUTB(0x07, (dev_num));                      \
 367 }
 368
 369 #define SANDPOINT_87308_DEV_ENABLE(dev_num) {                           \
 370         SANDPOINT_87308_SELECT_DEV(dev_num);                            \
 371         SANDPOINT_87308_CFG_OUTB(0x30, 0x01);                           \
 372 }
 373
 374 /*
 375  * To probe the Sandpoint type, we need to check for a connection between GPIO
 376  * pins 6 and 7 on the NS87308 SuperIO.
 377  */
 378 static void __init sandpoint_probe_type(void)
 379 {
 380         u8 x;
 381         /* First, ensure that the GPIO pins are enabled. */
 382         SANDPOINT_87308_SELECT_DEV(0x07); /* Select GPIO logical device */
 383         SANDPOINT_87308_CFG_OUTB(0x60, 0x07); /* Base address 0x700 */
 384         SANDPOINT_87308_CFG_OUTB(0x61, 0x00);
 385         SANDPOINT_87308_CFG_OUTB(0x30, 0x01); /* Enable */
 386
 387         /* Now, set pin 7 to output and pin 6 to input. */
 388         outb((inb(0x701) | 0x80) & 0xbf, 0x701);
 389         /* Set push-pull output */
 390         outb(inb(0x702) | 0x80, 0x702);
 391         /* Set pull-up on input */
 392         outb(inb(0x703) | 0x40, 0x703);
 393         /* Set output high and check */
 394         x = inb(0x700);
 395         outb(x | 0x80, 0x700);
 396         x = inb(0x700);
 397         sandpoint_is_x2 = ! (x & 0x40);
 398         if (ppc_md.progress && sandpoint_is_x2)
 399                 ppc_md.progress("High output says X2", 0);
 400         /* Set output low and check */
 401         outb(x & 0x7f, 0x700);
 402         sandpoint_is_x2 |= inb(0x700) & 0x40;
 403         if (ppc_md.progress && sandpoint_is_x2)
 404                 ppc_md.progress("Low output says X2", 0);
 405         if (ppc_md.progress && ! sandpoint_is_x2)
 406                 ppc_md.progress("Sandpoint is X3", 0);
 407 }
 408
 409 /*
 410  * Fix IDE interrupts.
 411  */
 412 static int __init
 413 sandpoint_fix_winbond_83553(void)
 414 {
 415         /* Make some 8259 interrupt level sensitive */
 416         outb(0xe0, 0x4d0);
 417         outb(0xde, 0x4d1);
 418
 419         return 0;
 420 }
 421
 422 arch_initcall(sandpoint_fix_winbond_83553);
 423
 424 /*
 425  * Initialize the ISA devices on the Nat'l PC87308VUL SuperIO chip.
 426  */
 427 static int __init
 428 sandpoint_setup_natl_87308(void)
 429 {
 430         u_char  reg;
 431
 432         /*
 433          * Enable all the devices on the Super I/O chip.
 434          */
 435         SANDPOINT_87308_SELECT_DEV(0x00); /* Select kbd logical device */
 436         SANDPOINT_87308_CFG_OUTB(0xf0, 0x00); /* Set KBC clock to 8 Mhz */
 437         SANDPOINT_87308_DEV_ENABLE(0x00); /* Enable keyboard */
 438         SANDPOINT_87308_DEV_ENABLE(0x01); /* Enable mouse */
 439         SANDPOINT_87308_DEV_ENABLE(0x02); /* Enable rtc */
 440         SANDPOINT_87308_DEV_ENABLE(0x03); /* Enable fdc (floppy) */
 441         SANDPOINT_87308_DEV_ENABLE(0x04); /* Enable parallel */
 442         SANDPOINT_87308_DEV_ENABLE(0x05); /* Enable UART 2 */
 443         SANDPOINT_87308_CFG_OUTB(0xf0, 0x82); /* Enable bank select regs */
 444         SANDPOINT_87308_DEV_ENABLE(0x06); /* Enable UART 1 */
 445         SANDPOINT_87308_CFG_OUTB(0xf0, 0x82); /* Enable bank select regs */
 446
 447         /* Set up floppy in PS/2 mode */
 448         outb(0x09, SIO_CONFIG_RA);
 449         reg = inb(SIO_CONFIG_RD);
 450         reg = (reg & 0x3F) | 0x40;
 451         outb(reg, SIO_CONFIG_RD);
 452         outb(reg, SIO_CONFIG_RD);       /* Have to write twice to change! */
 453
 454         return 0;
 455 }
 456
 457 arch_initcall(sandpoint_setup_natl_87308);
 458
 459 static int __init
 460 sandpoint_request_io(void)
 461 {
 462         request_region(0x00,0x20,"dma1");
 463         request_region(0x20,0x20,"pic1");
 464         request_region(0x40,0x20,"timer");
 465         request_region(0x80,0x10,"dma page reg");
 466         request_region(0xa0,0x20,"pic2");
 467         request_region(0xc0,0x20,"dma2");
 468
 469         return 0;
 470 }
 471
 472 arch_initcall(sandpoint_request_io);
 473
 474 /*
 475  * Interrupt setup and service.  Interrupts on the Sandpoint come
 476  * from the four PCI slots plus the 8259 in the Winbond Super I/O (SIO).
 477  * The 8259 is cascaded from EPIC IRQ0, IRQ1-4 map to PCI slots 1-4,
 478  * IDE is on EPIC 7 and 8.
 479  */
 480 static void __init
 481 sandpoint_init_IRQ(void)
 482 {
 483         int i;
 484
 485         OpenPIC_InitSenses = sandpoint_openpic_initsenses;
 486         OpenPIC_NumInitSenses = sizeof(sandpoint_openpic_initsenses);
 487
 488         mpc10x_set_openpic();
 489         openpic_hookup_cascade(sandpoint_is_x2 ? 17 : NUM_8259_INTERRUPTS, "82c59 cascade",
 490                         i8259_irq);
 491
 492         /*
 493          * The EPIC allows for a read in the range of 0xFEF00000 ->
 494          * 0xFEFFFFFF to generate a PCI interrupt-acknowledge transaction.
 495          */
 496         i8259_init(0xfef00000, 0);
 497 }
 498
 499 static unsigned long __init
 500 sandpoint_find_end_of_memory(void)
 501 {
 502         bd_t *bp = (bd_t *)__res;
 503
 504         if (bp->bi_memsize)
 505                 return bp->bi_memsize;
 506
 507         /* DINK32 13.0 correctly initializes things, so iff you use
 508          * this you _should_ be able to change this instead of a
 509          * hardcoded value. */
 510 #if 0
 511         return mpc10x_get_mem_size(MPC10X_MEM_MAP_B);
 512 #else
 513         return 32*1024*1024;
 514 #endif
 515 }
 516
 517 static void __init
 518 sandpoint_map_io(void)
 519 {
 520         io_block_mapping(0xfe000000, 0xfe000000, 0x02000000, _PAGE_IO);
 521 }
 522
 523 static void
 524 sandpoint_restart(char *cmd)
 525 {
 526         local_irq_disable();
 527
 528         /* Set exception prefix high - to the firmware */
 529         _nmask_and_or_msr(0, MSR_IP);
 530
 531         /* Reset system via Port 92 */
 532         outb(0x00, 0x92);
 533         outb(0x01, 0x92);
 534         for(;;);        /* Spin until reset happens */
 535 }
 536
 537 static void
 538 sandpoint_power_off(void)
 539 {
 540         local_irq_disable();
 541         for(;;);        /* No way to shut power off with software */
 542         /* NOTREACHED */
 543 }
 544
 545 static void
 546 sandpoint_halt(void)
 547 {
 548         sandpoint_power_off();
 549         /* NOTREACHED */
 550 }
 551
 552 static int
 553 sandpoint_show_cpuinfo(struct seq_file *m)
 554 {
 555         seq_printf(m, "vendor\t\t: Motorola SPS\n");
 556         seq_printf(m, "machine\t\t: Sandpoint\n");
 557
 558         return 0;
 559 }
 560
 561 /*
 562  * Set BAT 3 to map 0xf8000000 to end of physical memory space 1-to-1.
 563  */
 564 static __inline__ void
 565 sandpoint_set_bat(void)
 566 {
 567         unsigned long bat3u, bat3l;
 568
 569         __asm__ __volatile__(
 570                         " lis %0,0xf800\n       \
 571                         ori %1,%0,0x002a\n      \
 572                         ori %0,%0,0x0ffe\n      \
 573                         mtspr 0x21e,%0\n        \
 574                         mtspr 0x21f,%1\n        \
 575                         isync\n                 \
 576                         sync "
 577                         : "=r" (bat3u), "=r" (bat3l));
 578 }
 579
 580 TODC_ALLOC();
 581
 582 void __init
 583 platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
 584                 unsigned long r6, unsigned long r7)
 585 {
 586         parse_bootinfo(find_bootinfo());
 587
 588         /* ASSUMPTION:  If both r3 (bd_t pointer) and r6 (cmdline pointer)
 589          * are non-zero, then we should use the board info from the bd_t
 590          * structure and the cmdline pointed to by r6 instead of the
 591          * information from birecs, if any.  Otherwise, use the information
 592          * from birecs as discovered by the preceding call to
 593          * parse_bootinfo().  This rule should work with both PPCBoot, which
 594          * uses a bd_t board info structure, and the kernel boot wrapper,
 595          * which uses birecs.
 596          */
 597         if (r3 && r6) {
 598                 /* copy board info structure */
 599                 memcpy( (void *)__res,(void *)(r3+KERNELBASE), sizeof(bd_t) );
 600                 /* copy command line */
 601                 *(char *)(r7+KERNELBASE) = 0;
 602                 strcpy(cmd_line, (char *)(r6+KERNELBASE));
 603         }
 604
 605 #ifdef CONFIG_BLK_DEV_INITRD
 606         /* take care of initrd if we have one */
 607         if (r4) {
 608                 initrd_start = r4 + KERNELBASE;
 609                 initrd_end = r5 + KERNELBASE;
 610         }
 611 #endif /* CONFIG_BLK_DEV_INITRD */
 612
 613         /* Map in board regs, etc. */
 614         sandpoint_set_bat();
 615
 616         isa_io_base = MPC10X_MAPB_ISA_IO_BASE;
 617         isa_mem_base = MPC10X_MAPB_ISA_MEM_BASE;
 618         pci_dram_offset = MPC10X_MAPB_DRAM_OFFSET;
 619         ISA_DMA_THRESHOLD = 0x00ffffff;
 620         DMA_MODE_READ = 0x44;
 621         DMA_MODE_WRITE = 0x48;
 622         ppc_do_canonicalize_irqs = 1;
 623
 624         ppc_md.setup_arch = sandpoint_setup_arch;
 625         ppc_md.show_cpuinfo = sandpoint_show_cpuinfo;
 626         ppc_md.init_IRQ = sandpoint_init_IRQ;
 627         ppc_md.get_irq = openpic_get_irq;
 628
 629         ppc_md.restart = sandpoint_restart;
 630         ppc_md.power_off = sandpoint_power_off;
 631         ppc_md.halt = sandpoint_halt;
 632
 633         ppc_md.find_end_of_memory = sandpoint_find_end_of_memory;
 634         ppc_md.setup_io_mappings = sandpoint_map_io;
 635
 636         TODC_INIT(TODC_TYPE_PC97307, 0x70, 0x00, 0x71, 8);
 637         ppc_md.time_init = todc_time_init;
 638         ppc_md.set_rtc_time = todc_set_rtc_time;
 639         ppc_md.get_rtc_time = todc_get_rtc_time;
 640         ppc_md.calibrate_decr = todc_calibrate_decr;
 641
 642         ppc_md.nvram_read_val = todc_mc146818_read_val;
 643         ppc_md.nvram_write_val = todc_mc146818_write_val;
 644
 645 #ifdef CONFIG_KGDB
 646         ppc_md.kgdb_map_scc = gen550_kgdb_map_scc;
 647 #endif
 648 #ifdef CONFIG_SERIAL_TEXT_DEBUG
 649         ppc_md.progress = gen550_progress;
 650 #endif
 651 }