arch/ppc/platforms/tqm8xx.h

   1 /*
   2  * TQM8xx(L) board specific definitions
   3  *
   4  * Copyright (c) 1999-2002 Wolfgang Denk (wd@denx.de)
   5  */
   6
   7 #ifdef __KERNEL__
   8 #ifndef __MACH_TQM8xx_H
   9 #define __MACH_TQM8xx_H
  10
  11
  12 #include <asm/ppcboot.h>
  13
  14 #ifndef __ASSEMBLY__
  15 #define TQM_IMMR_BASE   0xFFF00000      /* phys. addr of IMMR */
  16 #define TQM_IMAP_SIZE   (64 * 1024)     /* size of mapped area */
  17
  18 #define IMAP_ADDR       TQM_IMMR_BASE   /* physical base address of IMMR area */
  19 #define IMAP_SIZE       TQM_IMAP_SIZE   /* mapped size of IMMR area */
  20
  21 /*-----------------------------------------------------------------------
  22  * PCMCIA stuff
  23  *-----------------------------------------------------------------------
  24  *
  25  */
  26 #define PCMCIA_MEM_SIZE         ( 64 << 20 )
  27
  28 #ifndef CONFIG_KUP4K
  29 # define        MAX_HWIFS       1       /* overwrite default in include/asm-ppc/ide.h   */
  30
  31 #else   /* CONFIG_KUP4K */
  32
  33 # define        MAX_HWIFS       2       /* overwrite default in include/asm-ppc/ide.h   */
  34 # ifndef __ASSEMBLY__
  35 # include <asm/8xx_immap.h>
  36 static __inline__ void ide_led(int on)
  37 {
  38         volatile immap_t        *immap = (immap_t *)IMAP_ADDR;
  39
  40         if (on) {
  41                 immap->im_ioport.iop_padat &= ~0x80;
  42         } else {
  43                 immap->im_ioport.iop_padat |= 0x80;
  44         }
  45 }
  46 # endif /* __ASSEMBLY__ */
  47 # define IDE_LED(x) ide_led((x))
  48 #endif  /* CONFIG_KUP4K */
  49
  50 /*
  51  * Definitions for IDE0 Interface
  52  */
  53 #define IDE0_BASE_OFFSET                0
  54 #define IDE0_DATA_REG_OFFSET            (PCMCIA_MEM_SIZE + 0x320)
  55 #define IDE0_ERROR_REG_OFFSET           (2 * PCMCIA_MEM_SIZE + 0x320 + 1)
  56 #define IDE0_NSECTOR_REG_OFFSET         (2 * PCMCIA_MEM_SIZE + 0x320 + 2)
  57 #define IDE0_SECTOR_REG_OFFSET          (2 * PCMCIA_MEM_SIZE + 0x320 + 3)
  58 #define IDE0_LCYL_REG_OFFSET            (2 * PCMCIA_MEM_SIZE + 0x320 + 4)
  59 #define IDE0_HCYL_REG_OFFSET            (2 * PCMCIA_MEM_SIZE + 0x320 + 5)
  60 #define IDE0_SELECT_REG_OFFSET          (2 * PCMCIA_MEM_SIZE + 0x320 + 6)
  61 #define IDE0_STATUS_REG_OFFSET          (2 * PCMCIA_MEM_SIZE + 0x320 + 7)
  62 #define IDE0_CONTROL_REG_OFFSET         0x0106
  63 #define IDE0_IRQ_REG_OFFSET             0x000A  /* not used */
  64
  65 /* define IO_BASE for PCMCIA */
  66 #define _IO_BASE 0x80000000
  67 #define _IO_BASE_SIZE  (64<<10)
  68
  69 #define FEC_INTERRUPT            9      /* = SIU_LEVEL4                 */
  70 #define PHY_INTERRUPT           12      /* = IRQ6                       */
  71 #define IDE0_INTERRUPT          13
  72
  73 #ifdef CONFIG_IDE
  74 #endif
  75
  76 /*-----------------------------------------------------------------------
  77  * CPM Ethernet through SCCx.
  78  *-----------------------------------------------------------------------
  79  *
  80  */
  81
  82 /***  TQM823L, TQM850L  ***********************************************/
  83
  84 #if defined(CONFIG_TQM823L) || defined(CONFIG_TQM850L)
  85 /* Bits in parallel I/O port registers that have to be set/cleared
  86  * to configure the pins for SCC1 use.
  87  */
  88 #define PA_ENET_RXD     ((ushort)0x0004)        /* PA 13 */
  89 #define PA_ENET_TXD     ((ushort)0x0008)        /* PA 12 */
  90 #define PA_ENET_RCLK    ((ushort)0x0100)        /* PA  7 */
  91 #define PA_ENET_TCLK    ((ushort)0x0400)        /* PA  5 */
  92
  93 #define PB_ENET_TENA    ((uint)0x00002000)      /* PB 18 */
  94
  95 #define PC_ENET_CLSN    ((ushort)0x0040)        /* PC  9 */
  96 #define PC_ENET_RENA    ((ushort)0x0080)        /* PC  8 */
  97
  98 /* Control bits in the SICR to route TCLK (CLK3) and RCLK (CLK1) to
  99  * SCC2.  Also, make sure GR2 (bit 16) and SC2 (bit 17) are zero.
 100  */
 101 #define SICR_ENET_MASK  ((uint)0x0000ff00)
 102 #define SICR_ENET_CLKRT ((uint)0x00002600)
 103 #endif  /* CONFIG_TQM823L, CONFIG_TQM850L */
 104
 105 /***  TQM860L  ********************************************************/
 106
 107 #ifdef CONFIG_TQM860L
 108 /* Bits in parallel I/O port registers that have to be set/cleared
 109  * to configure the pins for SCC1 use.
 110  */
 111 #define PA_ENET_RXD     ((ushort)0x0001)        /* PA 15 */
 112 #define PA_ENET_TXD     ((ushort)0x0002)        /* PA 14 */
 113 #define PA_ENET_RCLK    ((ushort)0x0100)        /* PA  7 */
 114 #define PA_ENET_TCLK    ((ushort)0x0400)        /* PA  5 */
 115
 116 #define PC_ENET_TENA    ((ushort)0x0001)        /* PC 15 */
 117 #define PC_ENET_CLSN    ((ushort)0x0010)        /* PC 11 */
 118 #define PC_ENET_RENA    ((ushort)0x0020)        /* PC 10 */
 119
 120 /* Control bits in the SICR to route TCLK (CLK3) and RCLK (CLK1) to
 121  * SCC1.  Also, make sure GR1 (bit 24) and SC1 (bit 25) are zero.
 122  */
 123 #define SICR_ENET_MASK  ((uint)0x000000ff)
 124 #define SICR_ENET_CLKRT ((uint)0x00000026)
 125 #endif  /* CONFIG_TQM860L */
 126
 127 /***  FPS850L  *********************************************************/
 128
 129 #ifdef CONFIG_FPS850L
 130 /* Bits in parallel I/O port registers that have to be set/cleared
 131  * to configure the pins for SCC1 use.
 132  */
 133 #define PA_ENET_RXD     ((ushort)0x0004)        /* PA 13 */
 134 #define PA_ENET_TXD     ((ushort)0x0008)        /* PA 12 */
 135 #define PA_ENET_RCLK    ((ushort)0x0100)        /* PA  7 */
 136 #define PA_ENET_TCLK    ((ushort)0x0400)        /* PA  5 */
 137
 138 #define PC_ENET_TENA    ((ushort)0x0002)        /* PC 14 */
 139 #define PC_ENET_CLSN    ((ushort)0x0040)        /* PC  9 */
 140 #define PC_ENET_RENA    ((ushort)0x0080)        /* PC  8 */
 141
 142 /* Control bits in the SICR to route TCLK (CLK2) and RCLK (CLK4) to
 143  * SCC2.  Also, make sure GR2 (bit 16) and SC2 (bit 17) are zero.
 144  */
 145 #define SICR_ENET_MASK  ((uint)0x0000ff00)
 146 #define SICR_ENET_CLKRT ((uint)0x00002600)
 147 #endif  /* CONFIG_FPS850L */
 148
 149 /* We don't use the 8259.
 150 */
 151 #define NR_8259_INTS    0
 152
 153 #endif /* !__ASSEMBLY__ */
 154 #endif  /* __MACH_TQM8xx_H */
 155 #endif /* __KERNEL__ */