arch/x86/kernel/mfgpt_32.c

   1 /*
   2  * Driver/API for AMD Geode Multi-Function General Purpose Timers (MFGPT)
   3  *
   4  * Copyright (C) 2006, Advanced Micro Devices, Inc.
   5  * Copyright (C) 2007, Andres Salomon <dilinger@debian.org>
   6  *
   7  * This program is free software; you can redistribute it and/or
   8  * modify it under the terms of version 2 of the GNU General Public License
   9  * as published by the Free Software Foundation.
  10  *
  11  * The MFGPTs are documented in AMD Geode CS5536 Companion Device Data Book.
  12  */
  13
  14 /*
  15  * We are using the 32.768kHz input clock - it's the only one that has the
  16  * ranges we find desirable.  The following table lists the suitable
  17  * divisors and the associated Hz, minimum interval and the maximum interval:
  18  *
  19  *  Divisor   Hz      Min Delta (s)  Max Delta (s)
  20  *   1        32768   .00048828125      2.000
  21  *   2        16384   .0009765625       4.000
  22  *   4         8192   .001953125        8.000
  23  *   8         4096   .00390625        16.000
  24  *   16        2048   .0078125         32.000
  25  *   32        1024   .015625          64.000
  26  *   64         512   .03125          128.000
  27  *  128         256   .0625           256.000
  28  *  256         128   .125            512.000
  29  */
  30
  31 #include <linux/kernel.h>
  32 #include <linux/interrupt.h>
  33 #include <linux/module.h>
  34 #include <asm/geode.h>
  35
  36 static struct mfgpt_timer_t {
  37         unsigned int avail:1;
  38 } mfgpt_timers[MFGPT_MAX_TIMERS];
  39
  40 /* Selected from the table above */
  41
  42 #define MFGPT_DIVISOR 16
  43 #define MFGPT_SCALE  4     /* divisor = 2^(scale) */
  44 #define MFGPT_HZ  (32768 / MFGPT_DIVISOR)
  45 #define MFGPT_PERIODIC (MFGPT_HZ / HZ)
  46
  47 /* Allow for disabling of MFGPTs */
  48 static int disable;
  49 static int __init mfgpt_disable(char *s)
  50 {
  51         disable = 1;
  52         return 1;
  53 }
  54 __setup("nomfgpt", mfgpt_disable);
  55
  56 /* Reset the MFGPT timers. This is required by some broken BIOSes which already
  57  * do the same and leave the system in an unstable state. TinyBIOS 0.98 is
  58  * affected at least (0.99 is OK with MFGPT workaround left to off).
  59  */
  60 static int __init mfgpt_fix(char *s)
  61 {
  62         u32 val, dummy;
  63
  64         /* The following udocumented bit resets the MFGPT timers */
  65         val = 0xFF; dummy = 0;
  66         wrmsr(MSR_MFGPT_SETUP, val, dummy);
  67         return 1;
  68 }
  69 __setup("mfgptfix", mfgpt_fix);
  70
  71 /*
  72  * Check whether any MFGPTs are available for the kernel to use.  In most
  73  * cases, firmware that uses AMD's VSA code will claim all timers during
  74  * bootup; we certainly don't want to take them if they're already in use.
  75  * In other cases (such as with VSAless OpenFirmware), the system firmware
  76  * leaves timers available for us to use.
  77  */
  78
  79
  80 static int timers = -1;
  81
  82 static void geode_mfgpt_detect(void)
  83 {
  84         int i;
  85         u16 val;
  86
  87         timers = 0;
  88
  89         if (disable) {
  90                 printk(KERN_INFO "geode-mfgpt:  MFGPT support is disabled\n");
  91                 goto done;
  92         }
  93
  94         if (!geode_get_dev_base(GEODE_DEV_MFGPT)) {
  95                 printk(KERN_INFO "geode-mfgpt:  MFGPT LBAR is not set up\n");
  96                 goto done;
  97         }
  98
  99         for (i = 0; i < MFGPT_MAX_TIMERS; i++) {
 100                 val = geode_mfgpt_read(i, MFGPT_REG_SETUP);
 101                 if (!(val & MFGPT_SETUP_SETUP)) {
 102                         mfgpt_timers[i].avail = 1;
 103                         timers++;
 104                 }
 105         }
 106
 107 done:
 108         printk(KERN_INFO "geode-mfgpt:  %d MFGPT timers available.\n", timers);
 109 }
 110
 111 int geode_mfgpt_toggle_event(int timer, int cmp, int event, int enable)
 112 {
 113         u32 msr, mask, value, dummy;
 114         int shift = (cmp == MFGPT_CMP1) ? 0 : 8;
 115
 116         if (timer < 0 || timer >= MFGPT_MAX_TIMERS)
 117                 return -EIO;
 118
 119         /*
 120          * The register maps for these are described in sections 6.17.1.x of
 121          * the AMD Geode CS5536 Companion Device Data Book.
 122          */
 123         switch (event) {
 124         case MFGPT_EVENT_RESET:
 125                 /*
 126                  * XXX: According to the docs, we cannot reset timers above
 127                  * 6; that is, resets for 7 and 8 will be ignored.  Is this
 128                  * a problem?   -dilinger
 129                  */
 130                 msr = MSR_MFGPT_NR;
 131                 mask = 1 << (timer + 24);
 132                 break;
 133
 134         case MFGPT_EVENT_NMI:
 135                 msr = MSR_MFGPT_NR;
 136                 mask = 1 << (timer + shift);
 137                 break;
 138
 139         case MFGPT_EVENT_IRQ:
 140                 msr = MSR_MFGPT_IRQ;
 141                 mask = 1 << (timer + shift);
 142                 break;
 143
 144         default:
 145                 return -EIO;
 146         }
 147
 148         rdmsr(msr, value, dummy);
 149
 150         if (enable)
 151                 value |= mask;
 152         else
 153                 value &= ~mask;
 154
 155         wrmsr(msr, value, dummy);
 156         return 0;
 157 }
 158
 159 int geode_mfgpt_set_irq(int timer, int cmp, int irq, int enable)
 160 {
 161         u32 val, dummy;
 162         int offset;
 163
 164         if (timer < 0 || timer >= MFGPT_MAX_TIMERS)
 165                 return -EIO;
 166
 167         if (geode_mfgpt_toggle_event(timer, cmp, MFGPT_EVENT_IRQ, enable))
 168                 return -EIO;
 169
 170         rdmsr(MSR_PIC_ZSEL_LOW, val, dummy);
 171
 172         offset = (timer % 4) * 4;
 173
 174         val &= ~((0xF << offset) | (0xF << (offset + 16)));
 175
 176         if (enable) {
 177                 val |= (irq & 0x0F) << (offset);
 178                 val |= (irq & 0x0F) << (offset + 16);
 179         }
 180
 181         wrmsr(MSR_PIC_ZSEL_LOW, val, dummy);
 182         return 0;
 183 }
 184
 185 static int mfgpt_get(int timer)
 186 {
 187         mfgpt_timers[timer].avail = 0;
 188         printk(KERN_INFO "geode-mfgpt:  Registered timer %d\n", timer);
 189         return timer;
 190 }
 191
 192 int geode_mfgpt_alloc_timer(int timer, int domain)
 193 {
 194         int i;
 195
 196         if (timers == -1) {
 197                 /* timers haven't been detected yet */
 198                 geode_mfgpt_detect();
 199         }
 200
 201         if (!timers)
 202                 return -1;
 203
 204         if (timer >= MFGPT_MAX_TIMERS)
 205                 return -1;
 206
 207         if (timer < 0) {
 208                 /* Try to find an available timer */
 209                 for (i = 0; i < MFGPT_MAX_TIMERS; i++) {
 210                         if (mfgpt_timers[i].avail)
 211                                 return mfgpt_get(i);
 212
 213                         if (i == 5 && domain == MFGPT_DOMAIN_WORKING)
 214                                 break;
 215                 }
 216         } else {
 217                 /* If they requested a specific timer, try to honor that */
 218                 if (mfgpt_timers[timer].avail)
 219                         return mfgpt_get(timer);
 220         }
 221
 222         /* No timers available - too bad */
 223         return -1;
 224 }
 225
 226
 227 #ifdef CONFIG_GEODE_MFGPT_TIMER
 228
 229 /*
 230  * The MFPGT timers on the CS5536 provide us with suitable timers to use
 231  * as clock event sources - not as good as a HPET or APIC, but certainly
 232  * better then the PIT.  This isn't a general purpose MFGPT driver, but
 233  * a simplified one designed specifically to act as a clock event source.
 234  * For full details about the MFGPT, please consult the CS5536 data sheet.
 235  */
 236
 237 #include <linux/clocksource.h>
 238 #include <linux/clockchips.h>
 239
 240 static unsigned int mfgpt_tick_mode = CLOCK_EVT_MODE_SHUTDOWN;
 241 static u16 mfgpt_event_clock;
 242
 243 static int irq = 7;
 244 static int __init mfgpt_setup(char *str)
 245 {
 246         get_option(&str, &irq);
 247         return 1;
 248 }
 249 __setup("mfgpt_irq=", mfgpt_setup);
 250
 251 static void mfgpt_disable_timer(u16 clock)
 252 {
 253         /* avoid races by clearing CMP1 and CMP2 unconditionally */
 254         geode_mfgpt_write(clock, MFGPT_REG_SETUP, (u16) ~MFGPT_SETUP_CNTEN |
 255                         MFGPT_SETUP_CMP1 | MFGPT_SETUP_CMP2);
 256 }
 257
 258 static int mfgpt_next_event(unsigned long, struct clock_event_device *);
 259 static void mfgpt_set_mode(enum clock_event_mode, struct clock_event_device *);
 260
 261 static struct clock_event_device mfgpt_clockevent = {
 262         .name = "mfgpt-timer",
 263         .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
 264         .set_mode = mfgpt_set_mode,
 265         .set_next_event = mfgpt_next_event,
 266         .rating = 250,
 267         .cpumask = CPU_MASK_ALL,
 268         .shift = 32
 269 };
 270
 271 static void mfgpt_start_timer(u16 delta)
 272 {
 273         geode_mfgpt_write(mfgpt_event_clock, MFGPT_REG_CMP2, (u16) delta);
 274         geode_mfgpt_write(mfgpt_event_clock, MFGPT_REG_COUNTER, 0);
 275
 276         geode_mfgpt_write(mfgpt_event_clock, MFGPT_REG_SETUP,
 277                           MFGPT_SETUP_CNTEN | MFGPT_SETUP_CMP2);
 278 }
 279
 280 static void mfgpt_set_mode(enum clock_event_mode mode,
 281                            struct clock_event_device *evt)
 282 {
 283         mfgpt_disable_timer(mfgpt_event_clock);
 284
 285         if (mode == CLOCK_EVT_MODE_PERIODIC)
 286                 mfgpt_start_timer(MFGPT_PERIODIC);
 287
 288         mfgpt_tick_mode = mode;
 289 }
 290
 291 static int mfgpt_next_event(unsigned long delta, struct clock_event_device *evt)
 292 {
 293         mfgpt_start_timer(delta);
 294         return 0;
 295 }
 296
 297 static irqreturn_t mfgpt_tick(int irq, void *dev_id)
 298 {
 299         u16 val = geode_mfgpt_read(mfgpt_event_clock, MFGPT_REG_SETUP);
 300
 301         /* See if the interrupt was for us */
 302         if (!(val & (MFGPT_SETUP_SETUP  | MFGPT_SETUP_CMP2 | MFGPT_SETUP_CMP1)))
 303                 return IRQ_NONE;
 304
 305         /* Turn off the clock (and clear the event) */
 306         mfgpt_disable_timer(mfgpt_event_clock);
 307
 308         if (mfgpt_tick_mode == CLOCK_EVT_MODE_SHUTDOWN)
 309                 return IRQ_HANDLED;
 310
 311         /* Clear the counter */
 312         geode_mfgpt_write(mfgpt_event_clock, MFGPT_REG_COUNTER, 0);
 313
 314         /* Restart the clock in periodic mode */
 315
 316         if (mfgpt_tick_mode == CLOCK_EVT_MODE_PERIODIC) {
 317                 geode_mfgpt_write(mfgpt_event_clock, MFGPT_REG_SETUP,
 318                                   MFGPT_SETUP_CNTEN | MFGPT_SETUP_CMP2);
 319         }
 320
 321         mfgpt_clockevent.event_handler(&mfgpt_clockevent);
 322         return IRQ_HANDLED;
 323 }
 324
 325 static struct irqaction mfgptirq  = {
 326         .handler = mfgpt_tick,
 327         .flags = IRQF_DISABLED | IRQF_NOBALANCING,
 328         .mask = CPU_MASK_NONE,
 329         .name = "mfgpt-timer"
 330 };
 331
 332 int __init mfgpt_timer_setup(void)
 333 {
 334         int timer, ret;
 335         u16 val;
 336
 337         timer = geode_mfgpt_alloc_timer(MFGPT_TIMER_ANY, MFGPT_DOMAIN_WORKING);
 338         if (timer < 0) {
 339                 printk(KERN_ERR
 340                        "mfgpt-timer:  Could not allocate a MFPGT timer\n");
 341                 return -ENODEV;
 342         }
 343
 344         mfgpt_event_clock = timer;
 345
 346         /* Set up the IRQ on the MFGPT side */
 347         if (geode_mfgpt_setup_irq(mfgpt_event_clock, MFGPT_CMP2, irq)) {
 348                 printk(KERN_ERR "mfgpt-timer:  Could not set up IRQ %d\n", irq);
 349                 return -EIO;
 350         }
 351
 352         /* And register it with the kernel */
 353         ret = setup_irq(irq, &mfgptirq);
 354
 355         if (ret) {
 356                 printk(KERN_ERR
 357                        "mfgpt-timer:  Unable to set up the interrupt.\n");
 358                 goto err;
 359         }
 360
 361         /* Set the clock scale and enable the event mode for CMP2 */
 362         val = MFGPT_SCALE | (3 << 8);
 363
 364         geode_mfgpt_write(mfgpt_event_clock, MFGPT_REG_SETUP, val);
 365
 366         /* Set up the clock event */
 367         mfgpt_clockevent.mult = div_sc(MFGPT_HZ, NSEC_PER_SEC,
 368                                        mfgpt_clockevent.shift);
 369         mfgpt_clockevent.min_delta_ns = clockevent_delta2ns(0xF,
 370                         &mfgpt_clockevent);
 371         mfgpt_clockevent.max_delta_ns = clockevent_delta2ns(0xFFFE,
 372                         &mfgpt_clockevent);
 373
 374         printk(KERN_INFO
 375                "mfgpt-timer:  registering the MFGPT timer as a clock event.\n");
 376         clockevents_register_device(&mfgpt_clockevent);
 377
 378         return 0;
 379
 380 err:
 381         geode_mfgpt_release_irq(mfgpt_event_clock, MFGPT_CMP2, irq);
 382         printk(KERN_ERR
 383                "mfgpt-timer:  Unable to set up the MFGPT clock source\n");
 384         return -EIO;
 385 }
 386
 387 #endif