ia64/kvm: compilation fix. export account_system_vtime.
[pv_ops_mirror.git] / drivers / ata / pata_bf54x.c
blob9ab89732cf9474f1fa34458717bb9bd7da755d88
1 /*
2 * File: drivers/ata/pata_bf54x.c
3 * Author: Sonic Zhang <sonic.zhang@analog.com>
5 * Created:
6 * Description: PATA Driver for blackfin 54x
8 * Modified:
9 * Copyright 2007 Analog Devices Inc.
11 * Bugs: Enter bugs at http://blackfin.uclinux.org/
13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of the GNU General Public License as published by
15 * the Free Software Foundation; either version 2 of the License, or
16 * (at your option) any later version.
18 * This program is distributed in the hope that it will be useful,
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 * GNU General Public License for more details.
23 * You should have received a copy of the GNU General Public License
24 * along with this program; if not, see the file COPYING, or write
25 * to the Free Software Foundation, Inc.,
26 * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
29 #include <linux/kernel.h>
30 #include <linux/module.h>
31 #include <linux/pci.h>
32 #include <linux/init.h>
33 #include <linux/blkdev.h>
34 #include <linux/delay.h>
35 #include <linux/device.h>
36 #include <scsi/scsi_host.h>
37 #include <linux/libata.h>
38 #include <linux/platform_device.h>
39 #include <asm/dma.h>
40 #include <asm/gpio.h>
41 #include <asm/portmux.h>
43 #define DRV_NAME "pata-bf54x"
44 #define DRV_VERSION "0.9"
46 #define ATA_REG_CTRL 0x0E
47 #define ATA_REG_ALTSTATUS ATA_REG_CTRL
49 /* These are the offset of the controller's registers */
50 #define ATAPI_OFFSET_CONTROL 0x00
51 #define ATAPI_OFFSET_STATUS 0x04
52 #define ATAPI_OFFSET_DEV_ADDR 0x08
53 #define ATAPI_OFFSET_DEV_TXBUF 0x0c
54 #define ATAPI_OFFSET_DEV_RXBUF 0x10
55 #define ATAPI_OFFSET_INT_MASK 0x14
56 #define ATAPI_OFFSET_INT_STATUS 0x18
57 #define ATAPI_OFFSET_XFER_LEN 0x1c
58 #define ATAPI_OFFSET_LINE_STATUS 0x20
59 #define ATAPI_OFFSET_SM_STATE 0x24
60 #define ATAPI_OFFSET_TERMINATE 0x28
61 #define ATAPI_OFFSET_PIO_TFRCNT 0x2c
62 #define ATAPI_OFFSET_DMA_TFRCNT 0x30
63 #define ATAPI_OFFSET_UMAIN_TFRCNT 0x34
64 #define ATAPI_OFFSET_UDMAOUT_TFRCNT 0x38
65 #define ATAPI_OFFSET_REG_TIM_0 0x40
66 #define ATAPI_OFFSET_PIO_TIM_0 0x44
67 #define ATAPI_OFFSET_PIO_TIM_1 0x48
68 #define ATAPI_OFFSET_MULTI_TIM_0 0x50
69 #define ATAPI_OFFSET_MULTI_TIM_1 0x54
70 #define ATAPI_OFFSET_MULTI_TIM_2 0x58
71 #define ATAPI_OFFSET_ULTRA_TIM_0 0x60
72 #define ATAPI_OFFSET_ULTRA_TIM_1 0x64
73 #define ATAPI_OFFSET_ULTRA_TIM_2 0x68
74 #define ATAPI_OFFSET_ULTRA_TIM_3 0x6c
77 #define ATAPI_GET_CONTROL(base)\
78 bfin_read16(base + ATAPI_OFFSET_CONTROL)
79 #define ATAPI_SET_CONTROL(base, val)\
80 bfin_write16(base + ATAPI_OFFSET_CONTROL, val)
81 #define ATAPI_GET_STATUS(base)\
82 bfin_read16(base + ATAPI_OFFSET_STATUS)
83 #define ATAPI_GET_DEV_ADDR(base)\
84 bfin_read16(base + ATAPI_OFFSET_DEV_ADDR)
85 #define ATAPI_SET_DEV_ADDR(base, val)\
86 bfin_write16(base + ATAPI_OFFSET_DEV_ADDR, val)
87 #define ATAPI_GET_DEV_TXBUF(base)\
88 bfin_read16(base + ATAPI_OFFSET_DEV_TXBUF)
89 #define ATAPI_SET_DEV_TXBUF(base, val)\
90 bfin_write16(base + ATAPI_OFFSET_DEV_TXBUF, val)
91 #define ATAPI_GET_DEV_RXBUF(base)\
92 bfin_read16(base + ATAPI_OFFSET_DEV_RXBUF)
93 #define ATAPI_SET_DEV_RXBUF(base, val)\
94 bfin_write16(base + ATAPI_OFFSET_DEV_RXBUF, val)
95 #define ATAPI_GET_INT_MASK(base)\
96 bfin_read16(base + ATAPI_OFFSET_INT_MASK)
97 #define ATAPI_SET_INT_MASK(base, val)\
98 bfin_write16(base + ATAPI_OFFSET_INT_MASK, val)
99 #define ATAPI_GET_INT_STATUS(base)\
100 bfin_read16(base + ATAPI_OFFSET_INT_STATUS)
101 #define ATAPI_SET_INT_STATUS(base, val)\
102 bfin_write16(base + ATAPI_OFFSET_INT_STATUS, val)
103 #define ATAPI_GET_XFER_LEN(base)\
104 bfin_read16(base + ATAPI_OFFSET_XFER_LEN)
105 #define ATAPI_SET_XFER_LEN(base, val)\
106 bfin_write16(base + ATAPI_OFFSET_XFER_LEN, val)
107 #define ATAPI_GET_LINE_STATUS(base)\
108 bfin_read16(base + ATAPI_OFFSET_LINE_STATUS)
109 #define ATAPI_GET_SM_STATE(base)\
110 bfin_read16(base + ATAPI_OFFSET_SM_STATE)
111 #define ATAPI_GET_TERMINATE(base)\
112 bfin_read16(base + ATAPI_OFFSET_TERMINATE)
113 #define ATAPI_SET_TERMINATE(base, val)\
114 bfin_write16(base + ATAPI_OFFSET_TERMINATE, val)
115 #define ATAPI_GET_PIO_TFRCNT(base)\
116 bfin_read16(base + ATAPI_OFFSET_PIO_TFRCNT)
117 #define ATAPI_GET_DMA_TFRCNT(base)\
118 bfin_read16(base + ATAPI_OFFSET_DMA_TFRCNT)
119 #define ATAPI_GET_UMAIN_TFRCNT(base)\
120 bfin_read16(base + ATAPI_OFFSET_UMAIN_TFRCNT)
121 #define ATAPI_GET_UDMAOUT_TFRCNT(base)\
122 bfin_read16(base + ATAPI_OFFSET_UDMAOUT_TFRCNT)
123 #define ATAPI_GET_REG_TIM_0(base)\
124 bfin_read16(base + ATAPI_OFFSET_REG_TIM_0)
125 #define ATAPI_SET_REG_TIM_0(base, val)\
126 bfin_write16(base + ATAPI_OFFSET_REG_TIM_0, val)
127 #define ATAPI_GET_PIO_TIM_0(base)\
128 bfin_read16(base + ATAPI_OFFSET_PIO_TIM_0)
129 #define ATAPI_SET_PIO_TIM_0(base, val)\
130 bfin_write16(base + ATAPI_OFFSET_PIO_TIM_0, val)
131 #define ATAPI_GET_PIO_TIM_1(base)\
132 bfin_read16(base + ATAPI_OFFSET_PIO_TIM_1)
133 #define ATAPI_SET_PIO_TIM_1(base, val)\
134 bfin_write16(base + ATAPI_OFFSET_PIO_TIM_1, val)
135 #define ATAPI_GET_MULTI_TIM_0(base)\
136 bfin_read16(base + ATAPI_OFFSET_MULTI_TIM_0)
137 #define ATAPI_SET_MULTI_TIM_0(base, val)\
138 bfin_write16(base + ATAPI_OFFSET_MULTI_TIM_0, val)
139 #define ATAPI_GET_MULTI_TIM_1(base)\
140 bfin_read16(base + ATAPI_OFFSET_MULTI_TIM_1)
141 #define ATAPI_SET_MULTI_TIM_1(base, val)\
142 bfin_write16(base + ATAPI_OFFSET_MULTI_TIM_1, val)
143 #define ATAPI_GET_MULTI_TIM_2(base)\
144 bfin_read16(base + ATAPI_OFFSET_MULTI_TIM_2)
145 #define ATAPI_SET_MULTI_TIM_2(base, val)\
146 bfin_write16(base + ATAPI_OFFSET_MULTI_TIM_2, val)
147 #define ATAPI_GET_ULTRA_TIM_0(base)\
148 bfin_read16(base + ATAPI_OFFSET_ULTRA_TIM_0)
149 #define ATAPI_SET_ULTRA_TIM_0(base, val)\
150 bfin_write16(base + ATAPI_OFFSET_ULTRA_TIM_0, val)
151 #define ATAPI_GET_ULTRA_TIM_1(base)\
152 bfin_read16(base + ATAPI_OFFSET_ULTRA_TIM_1)
153 #define ATAPI_SET_ULTRA_TIM_1(base, val)\
154 bfin_write16(base + ATAPI_OFFSET_ULTRA_TIM_1, val)
155 #define ATAPI_GET_ULTRA_TIM_2(base)\
156 bfin_read16(base + ATAPI_OFFSET_ULTRA_TIM_2)
157 #define ATAPI_SET_ULTRA_TIM_2(base, val)\
158 bfin_write16(base + ATAPI_OFFSET_ULTRA_TIM_2, val)
159 #define ATAPI_GET_ULTRA_TIM_3(base)\
160 bfin_read16(base + ATAPI_OFFSET_ULTRA_TIM_3)
161 #define ATAPI_SET_ULTRA_TIM_3(base, val)\
162 bfin_write16(base + ATAPI_OFFSET_ULTRA_TIM_3, val)
165 * PIO Mode - Frequency compatibility
167 /* mode: 0 1 2 3 4 */
168 static const u32 pio_fsclk[] =
169 { 33333333, 33333333, 33333333, 33333333, 33333333 };
172 * MDMA Mode - Frequency compatibility
174 /* mode: 0 1 2 */
175 static const u32 mdma_fsclk[] = { 33333333, 33333333, 33333333 };
178 * UDMA Mode - Frequency compatibility
180 * UDMA5 - 100 MB/s - SCLK = 133 MHz
181 * UDMA4 - 66 MB/s - SCLK >= 80 MHz
182 * UDMA3 - 44.4 MB/s - SCLK >= 50 MHz
183 * UDMA2 - 33 MB/s - SCLK >= 40 MHz
185 /* mode: 0 1 2 3 4 5 */
186 static const u32 udma_fsclk[] =
187 { 33333333, 33333333, 40000000, 50000000, 80000000, 133333333 };
190 * Register transfer timing table
192 /* mode: 0 1 2 3 4 */
193 /* Cycle Time */
194 static const u32 reg_t0min[] = { 600, 383, 330, 180, 120 };
195 /* DIOR/DIOW to end cycle */
196 static const u32 reg_t2min[] = { 290, 290, 290, 70, 25 };
197 /* DIOR/DIOW asserted pulse width */
198 static const u32 reg_teocmin[] = { 290, 290, 290, 80, 70 };
201 * PIO timing table
203 /* mode: 0 1 2 3 4 */
204 /* Cycle Time */
205 static const u32 pio_t0min[] = { 600, 383, 240, 180, 120 };
206 /* Address valid to DIOR/DIORW */
207 static const u32 pio_t1min[] = { 70, 50, 30, 30, 25 };
208 /* DIOR/DIOW to end cycle */
209 static const u32 pio_t2min[] = { 165, 125, 100, 80, 70 };
210 /* DIOR/DIOW asserted pulse width */
211 static const u32 pio_teocmin[] = { 165, 125, 100, 70, 25 };
212 /* DIOW data hold */
213 static const u32 pio_t4min[] = { 30, 20, 15, 10, 10 };
215 /* ******************************************************************
216 * Multiword DMA timing table
217 * ******************************************************************
219 /* mode: 0 1 2 */
220 /* Cycle Time */
221 static const u32 mdma_t0min[] = { 480, 150, 120 };
222 /* DIOR/DIOW asserted pulse width */
223 static const u32 mdma_tdmin[] = { 215, 80, 70 };
224 /* DMACK to read data released */
225 static const u32 mdma_thmin[] = { 20, 15, 10 };
226 /* DIOR/DIOW to DMACK hold */
227 static const u32 mdma_tjmin[] = { 20, 5, 5 };
228 /* DIOR negated pulse width */
229 static const u32 mdma_tkrmin[] = { 50, 50, 25 };
230 /* DIOR negated pulse width */
231 static const u32 mdma_tkwmin[] = { 215, 50, 25 };
232 /* CS[1:0] valid to DIOR/DIOW */
233 static const u32 mdma_tmmin[] = { 50, 30, 25 };
234 /* DMACK to read data released */
235 static const u32 mdma_tzmax[] = { 20, 25, 25 };
238 * Ultra DMA timing table
240 /* mode: 0 1 2 3 4 5 */
241 static const u32 udma_tcycmin[] = { 112, 73, 54, 39, 25, 17 };
242 static const u32 udma_tdvsmin[] = { 70, 48, 31, 20, 7, 5 };
243 static const u32 udma_tenvmax[] = { 70, 70, 70, 55, 55, 50 };
244 static const u32 udma_trpmin[] = { 160, 125, 100, 100, 100, 85 };
245 static const u32 udma_tmin[] = { 5, 5, 5, 5, 3, 3 };
248 static const u32 udma_tmlimin = 20;
249 static const u32 udma_tzahmin = 20;
250 static const u32 udma_tenvmin = 20;
251 static const u32 udma_tackmin = 20;
252 static const u32 udma_tssmin = 50;
256 * Function: num_clocks_min
258 * Description:
259 * calculate number of SCLK cycles to meet minimum timing
261 static unsigned short num_clocks_min(unsigned long tmin,
262 unsigned long fsclk)
264 unsigned long tmp ;
265 unsigned short result;
267 tmp = tmin * (fsclk/1000/1000) / 1000;
268 result = (unsigned short)tmp;
269 if ((tmp*1000*1000) < (tmin*(fsclk/1000))) {
270 result++;
273 return result;
277 * bfin_set_piomode - Initialize host controller PATA PIO timings
278 * @ap: Port whose timings we are configuring
279 * @adev: um
281 * Set PIO mode for device.
283 * LOCKING:
284 * None (inherited from caller).
287 static void bfin_set_piomode(struct ata_port *ap, struct ata_device *adev)
289 int mode = adev->pio_mode - XFER_PIO_0;
290 void __iomem *base = (void __iomem *)ap->ioaddr.ctl_addr;
291 unsigned int fsclk = get_sclk();
292 unsigned short teoc_reg, t2_reg, teoc_pio;
293 unsigned short t4_reg, t2_pio, t1_reg;
294 unsigned short n0, n6, t6min = 5;
296 /* the most restrictive timing value is t6 and tc, the DIOW - data hold
297 * If one SCLK pulse is longer than this minimum value then register
298 * transfers cannot be supported at this frequency.
300 n6 = num_clocks_min(t6min, fsclk);
301 if (mode >= 0 && mode <= 4 && n6 >= 1) {
302 dev_dbg(adev->link->ap->dev, "set piomode: mode=%d, fsclk=%ud\n", mode, fsclk);
303 /* calculate the timing values for register transfers. */
304 while (mode > 0 && pio_fsclk[mode] > fsclk)
305 mode--;
307 /* DIOR/DIOW to end cycle time */
308 t2_reg = num_clocks_min(reg_t2min[mode], fsclk);
309 /* DIOR/DIOW asserted pulse width */
310 teoc_reg = num_clocks_min(reg_teocmin[mode], fsclk);
311 /* Cycle Time */
312 n0 = num_clocks_min(reg_t0min[mode], fsclk);
314 /* increase t2 until we meed the minimum cycle length */
315 if (t2_reg + teoc_reg < n0)
316 t2_reg = n0 - teoc_reg;
318 /* calculate the timing values for pio transfers. */
320 /* DIOR/DIOW to end cycle time */
321 t2_pio = num_clocks_min(pio_t2min[mode], fsclk);
322 /* DIOR/DIOW asserted pulse width */
323 teoc_pio = num_clocks_min(pio_teocmin[mode], fsclk);
324 /* Cycle Time */
325 n0 = num_clocks_min(pio_t0min[mode], fsclk);
327 /* increase t2 until we meed the minimum cycle length */
328 if (t2_pio + teoc_pio < n0)
329 t2_pio = n0 - teoc_pio;
331 /* Address valid to DIOR/DIORW */
332 t1_reg = num_clocks_min(pio_t1min[mode], fsclk);
334 /* DIOW data hold */
335 t4_reg = num_clocks_min(pio_t4min[mode], fsclk);
337 ATAPI_SET_REG_TIM_0(base, (teoc_reg<<8 | t2_reg));
338 ATAPI_SET_PIO_TIM_0(base, (t4_reg<<12 | t2_pio<<4 | t1_reg));
339 ATAPI_SET_PIO_TIM_1(base, teoc_pio);
340 if (mode > 2) {
341 ATAPI_SET_CONTROL(base,
342 ATAPI_GET_CONTROL(base) | IORDY_EN);
343 } else {
344 ATAPI_SET_CONTROL(base,
345 ATAPI_GET_CONTROL(base) & ~IORDY_EN);
348 /* Disable host ATAPI PIO interrupts */
349 ATAPI_SET_INT_MASK(base, ATAPI_GET_INT_MASK(base)
350 & ~(PIO_DONE_MASK | HOST_TERM_XFER_MASK));
351 SSYNC();
356 * bfin_set_dmamode - Initialize host controller PATA DMA timings
357 * @ap: Port whose timings we are configuring
358 * @adev: um
359 * @udma: udma mode, 0 - 6
361 * Set UDMA mode for device.
363 * LOCKING:
364 * None (inherited from caller).
367 static void bfin_set_dmamode(struct ata_port *ap, struct ata_device *adev)
369 int mode;
370 void __iomem *base = (void __iomem *)ap->ioaddr.ctl_addr;
371 unsigned long fsclk = get_sclk();
372 unsigned short tenv, tack, tcyc_tdvs, tdvs, tmli, tss, trp, tzah;
373 unsigned short tm, td, tkr, tkw, teoc, th;
374 unsigned short n0, nf, tfmin = 5;
375 unsigned short nmin, tcyc;
377 mode = adev->dma_mode - XFER_UDMA_0;
378 if (mode >= 0 && mode <= 5) {
379 dev_dbg(adev->link->ap->dev, "set udmamode: mode=%d\n", mode);
380 /* the most restrictive timing value is t6 and tc,
381 * the DIOW - data hold. If one SCLK pulse is longer
382 * than this minimum value then register
383 * transfers cannot be supported at this frequency.
385 while (mode > 0 && udma_fsclk[mode] > fsclk)
386 mode--;
388 nmin = num_clocks_min(udma_tmin[mode], fsclk);
389 if (nmin >= 1) {
390 /* calculate the timing values for Ultra DMA. */
391 tdvs = num_clocks_min(udma_tdvsmin[mode], fsclk);
392 tcyc = num_clocks_min(udma_tcycmin[mode], fsclk);
393 tcyc_tdvs = 2;
395 /* increase tcyc - tdvs (tcyc_tdvs) until we meed
396 * the minimum cycle length
398 if (tdvs + tcyc_tdvs < tcyc)
399 tcyc_tdvs = tcyc - tdvs;
401 /* Mow assign the values required for the timing
402 * registers
404 if (tcyc_tdvs < 2)
405 tcyc_tdvs = 2;
407 if (tdvs < 2)
408 tdvs = 2;
410 tack = num_clocks_min(udma_tackmin, fsclk);
411 tss = num_clocks_min(udma_tssmin, fsclk);
412 tmli = num_clocks_min(udma_tmlimin, fsclk);
413 tzah = num_clocks_min(udma_tzahmin, fsclk);
414 trp = num_clocks_min(udma_trpmin[mode], fsclk);
415 tenv = num_clocks_min(udma_tenvmin, fsclk);
416 if (tenv <= udma_tenvmax[mode]) {
417 ATAPI_SET_ULTRA_TIM_0(base, (tenv<<8 | tack));
418 ATAPI_SET_ULTRA_TIM_1(base,
419 (tcyc_tdvs<<8 | tdvs));
420 ATAPI_SET_ULTRA_TIM_2(base, (tmli<<8 | tss));
421 ATAPI_SET_ULTRA_TIM_3(base, (trp<<8 | tzah));
423 /* Enable host ATAPI Untra DMA interrupts */
424 ATAPI_SET_INT_MASK(base,
425 ATAPI_GET_INT_MASK(base)
426 | UDMAIN_DONE_MASK
427 | UDMAOUT_DONE_MASK
428 | UDMAIN_TERM_MASK
429 | UDMAOUT_TERM_MASK);
434 mode = adev->dma_mode - XFER_MW_DMA_0;
435 if (mode >= 0 && mode <= 2) {
436 dev_dbg(adev->link->ap->dev, "set mdmamode: mode=%d\n", mode);
437 /* the most restrictive timing value is tf, the DMACK to
438 * read data released. If one SCLK pulse is longer than
439 * this maximum value then the MDMA mode
440 * cannot be supported at this frequency.
442 while (mode > 0 && mdma_fsclk[mode] > fsclk)
443 mode--;
445 nf = num_clocks_min(tfmin, fsclk);
446 if (nf >= 1) {
447 /* calculate the timing values for Multi-word DMA. */
449 /* DIOR/DIOW asserted pulse width */
450 td = num_clocks_min(mdma_tdmin[mode], fsclk);
452 /* DIOR negated pulse width */
453 tkw = num_clocks_min(mdma_tkwmin[mode], fsclk);
455 /* Cycle Time */
456 n0 = num_clocks_min(mdma_t0min[mode], fsclk);
458 /* increase tk until we meed the minimum cycle length */
459 if (tkw + td < n0)
460 tkw = n0 - td;
462 /* DIOR negated pulse width - read */
463 tkr = num_clocks_min(mdma_tkrmin[mode], fsclk);
464 /* CS{1:0] valid to DIOR/DIOW */
465 tm = num_clocks_min(mdma_tmmin[mode], fsclk);
466 /* DIOR/DIOW to DMACK hold */
467 teoc = num_clocks_min(mdma_tjmin[mode], fsclk);
468 /* DIOW Data hold */
469 th = num_clocks_min(mdma_thmin[mode], fsclk);
471 ATAPI_SET_MULTI_TIM_0(base, (tm<<8 | td));
472 ATAPI_SET_MULTI_TIM_1(base, (tkr<<8 | tkw));
473 ATAPI_SET_MULTI_TIM_2(base, (teoc<<8 | th));
475 /* Enable host ATAPI Multi DMA interrupts */
476 ATAPI_SET_INT_MASK(base, ATAPI_GET_INT_MASK(base)
477 | MULTI_DONE_MASK | MULTI_TERM_MASK);
478 SSYNC();
481 return;
486 * Function: wait_complete
488 * Description: Waits the interrupt from device
491 static inline void wait_complete(void __iomem *base, unsigned short mask)
493 unsigned short status;
494 unsigned int i = 0;
496 #define PATA_BF54X_WAIT_TIMEOUT 10000
498 for (i = 0; i < PATA_BF54X_WAIT_TIMEOUT; i++) {
499 status = ATAPI_GET_INT_STATUS(base) & mask;
500 if (status)
501 break;
504 ATAPI_SET_INT_STATUS(base, mask);
509 * Function: write_atapi_register
511 * Description: Writes to ATA Device Resgister
515 static void write_atapi_register(void __iomem *base,
516 unsigned long ata_reg, unsigned short value)
518 /* Program the ATA_DEV_TXBUF register with write data (to be
519 * written into the device).
521 ATAPI_SET_DEV_TXBUF(base, value);
523 /* Program the ATA_DEV_ADDR register with address of the
524 * device register (0x01 to 0x0F).
526 ATAPI_SET_DEV_ADDR(base, ata_reg);
528 /* Program the ATA_CTRL register with dir set to write (1)
530 ATAPI_SET_CONTROL(base, (ATAPI_GET_CONTROL(base) | XFER_DIR));
532 /* ensure PIO DMA is not set */
533 ATAPI_SET_CONTROL(base, (ATAPI_GET_CONTROL(base) & ~PIO_USE_DMA));
535 /* and start the transfer */
536 ATAPI_SET_CONTROL(base, (ATAPI_GET_CONTROL(base) | PIO_START));
538 /* Wait for the interrupt to indicate the end of the transfer.
539 * (We need to wait on and clear rhe ATA_DEV_INT interrupt status)
541 wait_complete(base, PIO_DONE_INT);
546 * Function: read_atapi_register
548 *Description: Reads from ATA Device Resgister
552 static unsigned short read_atapi_register(void __iomem *base,
553 unsigned long ata_reg)
555 /* Program the ATA_DEV_ADDR register with address of the
556 * device register (0x01 to 0x0F).
558 ATAPI_SET_DEV_ADDR(base, ata_reg);
560 /* Program the ATA_CTRL register with dir set to read (0) and
562 ATAPI_SET_CONTROL(base, (ATAPI_GET_CONTROL(base) & ~XFER_DIR));
564 /* ensure PIO DMA is not set */
565 ATAPI_SET_CONTROL(base, (ATAPI_GET_CONTROL(base) & ~PIO_USE_DMA));
567 /* and start the transfer */
568 ATAPI_SET_CONTROL(base, (ATAPI_GET_CONTROL(base) | PIO_START));
570 /* Wait for the interrupt to indicate the end of the transfer.
571 * (PIO_DONE interrupt is set and it doesn't seem to matter
572 * that we don't clear it)
574 wait_complete(base, PIO_DONE_INT);
576 /* Read the ATA_DEV_RXBUF register with write data (to be
577 * written into the device).
579 return ATAPI_GET_DEV_RXBUF(base);
584 * Function: write_atapi_register_data
586 * Description: Writes to ATA Device Resgister
590 static void write_atapi_data(void __iomem *base,
591 int len, unsigned short *buf)
593 int i;
595 /* Set transfer length to 1 */
596 ATAPI_SET_XFER_LEN(base, 1);
598 /* Program the ATA_DEV_ADDR register with address of the
599 * ATA_REG_DATA
601 ATAPI_SET_DEV_ADDR(base, ATA_REG_DATA);
603 /* Program the ATA_CTRL register with dir set to write (1)
605 ATAPI_SET_CONTROL(base, (ATAPI_GET_CONTROL(base) | XFER_DIR));
607 /* ensure PIO DMA is not set */
608 ATAPI_SET_CONTROL(base, (ATAPI_GET_CONTROL(base) & ~PIO_USE_DMA));
610 for (i = 0; i < len; i++) {
611 /* Program the ATA_DEV_TXBUF register with write data (to be
612 * written into the device).
614 ATAPI_SET_DEV_TXBUF(base, buf[i]);
616 /* and start the transfer */
617 ATAPI_SET_CONTROL(base, (ATAPI_GET_CONTROL(base) | PIO_START));
619 /* Wait for the interrupt to indicate the end of the transfer.
620 * (We need to wait on and clear rhe ATA_DEV_INT
621 * interrupt status)
623 wait_complete(base, PIO_DONE_INT);
629 * Function: read_atapi_register_data
631 * Description: Reads from ATA Device Resgister
635 static void read_atapi_data(void __iomem *base,
636 int len, unsigned short *buf)
638 int i;
640 /* Set transfer length to 1 */
641 ATAPI_SET_XFER_LEN(base, 1);
643 /* Program the ATA_DEV_ADDR register with address of the
644 * ATA_REG_DATA
646 ATAPI_SET_DEV_ADDR(base, ATA_REG_DATA);
648 /* Program the ATA_CTRL register with dir set to read (0) and
650 ATAPI_SET_CONTROL(base, (ATAPI_GET_CONTROL(base) & ~XFER_DIR));
652 /* ensure PIO DMA is not set */
653 ATAPI_SET_CONTROL(base, (ATAPI_GET_CONTROL(base) & ~PIO_USE_DMA));
655 for (i = 0; i < len; i++) {
656 /* and start the transfer */
657 ATAPI_SET_CONTROL(base, (ATAPI_GET_CONTROL(base) | PIO_START));
659 /* Wait for the interrupt to indicate the end of the transfer.
660 * (PIO_DONE interrupt is set and it doesn't seem to matter
661 * that we don't clear it)
663 wait_complete(base, PIO_DONE_INT);
665 /* Read the ATA_DEV_RXBUF register with write data (to be
666 * written into the device).
668 buf[i] = ATAPI_GET_DEV_RXBUF(base);
673 * bfin_tf_load - send taskfile registers to host controller
674 * @ap: Port to which output is sent
675 * @tf: ATA taskfile register set
677 * Note: Original code is ata_sff_tf_load().
680 static void bfin_tf_load(struct ata_port *ap, const struct ata_taskfile *tf)
682 void __iomem *base = (void __iomem *)ap->ioaddr.ctl_addr;
683 unsigned int is_addr = tf->flags & ATA_TFLAG_ISADDR;
685 if (tf->ctl != ap->last_ctl) {
686 write_atapi_register(base, ATA_REG_CTRL, tf->ctl);
687 ap->last_ctl = tf->ctl;
688 ata_wait_idle(ap);
691 if (is_addr) {
692 if (tf->flags & ATA_TFLAG_LBA48) {
693 write_atapi_register(base, ATA_REG_FEATURE,
694 tf->hob_feature);
695 write_atapi_register(base, ATA_REG_NSECT,
696 tf->hob_nsect);
697 write_atapi_register(base, ATA_REG_LBAL, tf->hob_lbal);
698 write_atapi_register(base, ATA_REG_LBAM, tf->hob_lbam);
699 write_atapi_register(base, ATA_REG_LBAH, tf->hob_lbah);
700 dev_dbg(ap->dev, "hob: feat 0x%X nsect 0x%X, lba 0x%X "
701 "0x%X 0x%X\n",
702 tf->hob_feature,
703 tf->hob_nsect,
704 tf->hob_lbal,
705 tf->hob_lbam,
706 tf->hob_lbah);
709 write_atapi_register(base, ATA_REG_FEATURE, tf->feature);
710 write_atapi_register(base, ATA_REG_NSECT, tf->nsect);
711 write_atapi_register(base, ATA_REG_LBAL, tf->lbal);
712 write_atapi_register(base, ATA_REG_LBAM, tf->lbam);
713 write_atapi_register(base, ATA_REG_LBAH, tf->lbah);
714 dev_dbg(ap->dev, "feat 0x%X nsect 0x%X lba 0x%X 0x%X 0x%X\n",
715 tf->feature,
716 tf->nsect,
717 tf->lbal,
718 tf->lbam,
719 tf->lbah);
722 if (tf->flags & ATA_TFLAG_DEVICE) {
723 write_atapi_register(base, ATA_REG_DEVICE, tf->device);
724 dev_dbg(ap->dev, "device 0x%X\n", tf->device);
727 ata_wait_idle(ap);
731 * bfin_check_status - Read device status reg & clear interrupt
732 * @ap: port where the device is
734 * Note: Original code is ata_check_status().
737 static u8 bfin_check_status(struct ata_port *ap)
739 void __iomem *base = (void __iomem *)ap->ioaddr.ctl_addr;
740 return read_atapi_register(base, ATA_REG_STATUS);
744 * bfin_tf_read - input device's ATA taskfile shadow registers
745 * @ap: Port from which input is read
746 * @tf: ATA taskfile register set for storing input
748 * Note: Original code is ata_sff_tf_read().
751 static void bfin_tf_read(struct ata_port *ap, struct ata_taskfile *tf)
753 void __iomem *base = (void __iomem *)ap->ioaddr.ctl_addr;
755 tf->command = bfin_check_status(ap);
756 tf->feature = read_atapi_register(base, ATA_REG_ERR);
757 tf->nsect = read_atapi_register(base, ATA_REG_NSECT);
758 tf->lbal = read_atapi_register(base, ATA_REG_LBAL);
759 tf->lbam = read_atapi_register(base, ATA_REG_LBAM);
760 tf->lbah = read_atapi_register(base, ATA_REG_LBAH);
761 tf->device = read_atapi_register(base, ATA_REG_DEVICE);
763 if (tf->flags & ATA_TFLAG_LBA48) {
764 write_atapi_register(base, ATA_REG_CTRL, tf->ctl | ATA_HOB);
765 tf->hob_feature = read_atapi_register(base, ATA_REG_ERR);
766 tf->hob_nsect = read_atapi_register(base, ATA_REG_NSECT);
767 tf->hob_lbal = read_atapi_register(base, ATA_REG_LBAL);
768 tf->hob_lbam = read_atapi_register(base, ATA_REG_LBAM);
769 tf->hob_lbah = read_atapi_register(base, ATA_REG_LBAH);
774 * bfin_exec_command - issue ATA command to host controller
775 * @ap: port to which command is being issued
776 * @tf: ATA taskfile register set
778 * Note: Original code is ata_sff_exec_command().
781 static void bfin_exec_command(struct ata_port *ap,
782 const struct ata_taskfile *tf)
784 void __iomem *base = (void __iomem *)ap->ioaddr.ctl_addr;
785 dev_dbg(ap->dev, "ata%u: cmd 0x%X\n", ap->print_id, tf->command);
787 write_atapi_register(base, ATA_REG_CMD, tf->command);
788 ata_sff_pause(ap);
792 * bfin_check_altstatus - Read device alternate status reg
793 * @ap: port where the device is
796 static u8 bfin_check_altstatus(struct ata_port *ap)
798 void __iomem *base = (void __iomem *)ap->ioaddr.ctl_addr;
799 return read_atapi_register(base, ATA_REG_ALTSTATUS);
803 * bfin_dev_select - Select device 0/1 on ATA bus
804 * @ap: ATA channel to manipulate
805 * @device: ATA device (numbered from zero) to select
807 * Note: Original code is ata_sff_dev_select().
810 static void bfin_dev_select(struct ata_port *ap, unsigned int device)
812 void __iomem *base = (void __iomem *)ap->ioaddr.ctl_addr;
813 u8 tmp;
815 if (device == 0)
816 tmp = ATA_DEVICE_OBS;
817 else
818 tmp = ATA_DEVICE_OBS | ATA_DEV1;
820 write_atapi_register(base, ATA_REG_DEVICE, tmp);
821 ata_sff_pause(ap);
825 * bfin_bmdma_setup - Set up IDE DMA transaction
826 * @qc: Info associated with this ATA transaction.
828 * Note: Original code is ata_bmdma_setup().
831 static void bfin_bmdma_setup(struct ata_queued_cmd *qc)
833 unsigned short config = WDSIZE_16;
834 struct scatterlist *sg;
835 unsigned int si;
837 dev_dbg(qc->ap->dev, "in atapi dma setup\n");
838 /* Program the ATA_CTRL register with dir */
839 if (qc->tf.flags & ATA_TFLAG_WRITE) {
840 /* fill the ATAPI DMA controller */
841 set_dma_config(CH_ATAPI_TX, config);
842 set_dma_x_modify(CH_ATAPI_TX, 2);
843 for_each_sg(qc->sg, sg, qc->n_elem, si) {
844 set_dma_start_addr(CH_ATAPI_TX, sg_dma_address(sg));
845 set_dma_x_count(CH_ATAPI_TX, sg_dma_len(sg) >> 1);
847 } else {
848 config |= WNR;
849 /* fill the ATAPI DMA controller */
850 set_dma_config(CH_ATAPI_RX, config);
851 set_dma_x_modify(CH_ATAPI_RX, 2);
852 for_each_sg(qc->sg, sg, qc->n_elem, si) {
853 set_dma_start_addr(CH_ATAPI_RX, sg_dma_address(sg));
854 set_dma_x_count(CH_ATAPI_RX, sg_dma_len(sg) >> 1);
860 * bfin_bmdma_start - Start an IDE DMA transaction
861 * @qc: Info associated with this ATA transaction.
863 * Note: Original code is ata_bmdma_start().
866 static void bfin_bmdma_start(struct ata_queued_cmd *qc)
868 struct ata_port *ap = qc->ap;
869 void __iomem *base = (void __iomem *)ap->ioaddr.ctl_addr;
870 struct scatterlist *sg;
871 unsigned int si;
873 dev_dbg(qc->ap->dev, "in atapi dma start\n");
874 if (!(ap->udma_mask || ap->mwdma_mask))
875 return;
877 /* start ATAPI DMA controller*/
878 if (qc->tf.flags & ATA_TFLAG_WRITE) {
880 * On blackfin arch, uncacheable memory is not
881 * allocated with flag GFP_DMA. DMA buffer from
882 * common kenel code should be flushed if WB
883 * data cache is enabled. Otherwise, this loop
884 * is an empty loop and optimized out.
886 for_each_sg(qc->sg, sg, qc->n_elem, si) {
887 flush_dcache_range(sg_dma_address(sg),
888 sg_dma_address(sg) + sg_dma_len(sg));
890 enable_dma(CH_ATAPI_TX);
891 dev_dbg(qc->ap->dev, "enable udma write\n");
893 /* Send ATA DMA write command */
894 bfin_exec_command(ap, &qc->tf);
896 /* set ATA DMA write direction */
897 ATAPI_SET_CONTROL(base, (ATAPI_GET_CONTROL(base)
898 | XFER_DIR));
899 } else {
900 enable_dma(CH_ATAPI_RX);
901 dev_dbg(qc->ap->dev, "enable udma read\n");
903 /* Send ATA DMA read command */
904 bfin_exec_command(ap, &qc->tf);
906 /* set ATA DMA read direction */
907 ATAPI_SET_CONTROL(base, (ATAPI_GET_CONTROL(base)
908 & ~XFER_DIR));
911 /* Reset all transfer count */
912 ATAPI_SET_CONTROL(base, ATAPI_GET_CONTROL(base) | TFRCNT_RST);
914 /* Set transfer length to buffer len */
915 for_each_sg(qc->sg, sg, qc->n_elem, si) {
916 ATAPI_SET_XFER_LEN(base, (sg_dma_len(sg) >> 1));
919 /* Enable ATA DMA operation*/
920 if (ap->udma_mask)
921 ATAPI_SET_CONTROL(base, ATAPI_GET_CONTROL(base)
922 | ULTRA_START);
923 else
924 ATAPI_SET_CONTROL(base, ATAPI_GET_CONTROL(base)
925 | MULTI_START);
929 * bfin_bmdma_stop - Stop IDE DMA transfer
930 * @qc: Command we are ending DMA for
933 static void bfin_bmdma_stop(struct ata_queued_cmd *qc)
935 struct ata_port *ap = qc->ap;
936 struct scatterlist *sg;
937 unsigned int si;
939 dev_dbg(qc->ap->dev, "in atapi dma stop\n");
940 if (!(ap->udma_mask || ap->mwdma_mask))
941 return;
943 /* stop ATAPI DMA controller*/
944 if (qc->tf.flags & ATA_TFLAG_WRITE)
945 disable_dma(CH_ATAPI_TX);
946 else {
947 disable_dma(CH_ATAPI_RX);
948 if (ap->hsm_task_state & HSM_ST_LAST) {
950 * On blackfin arch, uncacheable memory is not
951 * allocated with flag GFP_DMA. DMA buffer from
952 * common kenel code should be invalidated if
953 * data cache is enabled. Otherwise, this loop
954 * is an empty loop and optimized out.
956 for_each_sg(qc->sg, sg, qc->n_elem, si) {
957 invalidate_dcache_range(
958 sg_dma_address(sg),
959 sg_dma_address(sg)
960 + sg_dma_len(sg));
967 * bfin_devchk - PATA device presence detection
968 * @ap: ATA channel to examine
969 * @device: Device to examine (starting at zero)
971 * Note: Original code is ata_devchk().
974 static unsigned int bfin_devchk(struct ata_port *ap,
975 unsigned int device)
977 void __iomem *base = (void __iomem *)ap->ioaddr.ctl_addr;
978 u8 nsect, lbal;
980 bfin_dev_select(ap, device);
982 write_atapi_register(base, ATA_REG_NSECT, 0x55);
983 write_atapi_register(base, ATA_REG_LBAL, 0xaa);
985 write_atapi_register(base, ATA_REG_NSECT, 0xaa);
986 write_atapi_register(base, ATA_REG_LBAL, 0x55);
988 write_atapi_register(base, ATA_REG_NSECT, 0x55);
989 write_atapi_register(base, ATA_REG_LBAL, 0xaa);
991 nsect = read_atapi_register(base, ATA_REG_NSECT);
992 lbal = read_atapi_register(base, ATA_REG_LBAL);
994 if ((nsect == 0x55) && (lbal == 0xaa))
995 return 1; /* we found a device */
997 return 0; /* nothing found */
1001 * bfin_bus_post_reset - PATA device post reset
1003 * Note: Original code is ata_bus_post_reset().
1006 static void bfin_bus_post_reset(struct ata_port *ap, unsigned int devmask)
1008 void __iomem *base = (void __iomem *)ap->ioaddr.ctl_addr;
1009 unsigned int dev0 = devmask & (1 << 0);
1010 unsigned int dev1 = devmask & (1 << 1);
1011 unsigned long timeout;
1013 /* if device 0 was found in ata_devchk, wait for its
1014 * BSY bit to clear
1016 if (dev0)
1017 ata_sff_busy_sleep(ap, ATA_TMOUT_BOOT_QUICK, ATA_TMOUT_BOOT);
1019 /* if device 1 was found in ata_devchk, wait for
1020 * register access, then wait for BSY to clear
1022 timeout = jiffies + ATA_TMOUT_BOOT;
1023 while (dev1) {
1024 u8 nsect, lbal;
1026 bfin_dev_select(ap, 1);
1027 nsect = read_atapi_register(base, ATA_REG_NSECT);
1028 lbal = read_atapi_register(base, ATA_REG_LBAL);
1029 if ((nsect == 1) && (lbal == 1))
1030 break;
1031 if (time_after(jiffies, timeout)) {
1032 dev1 = 0;
1033 break;
1035 msleep(50); /* give drive a breather */
1037 if (dev1)
1038 ata_sff_busy_sleep(ap, ATA_TMOUT_BOOT_QUICK, ATA_TMOUT_BOOT);
1040 /* is all this really necessary? */
1041 bfin_dev_select(ap, 0);
1042 if (dev1)
1043 bfin_dev_select(ap, 1);
1044 if (dev0)
1045 bfin_dev_select(ap, 0);
1049 * bfin_bus_softreset - PATA device software reset
1051 * Note: Original code is ata_bus_softreset().
1054 static unsigned int bfin_bus_softreset(struct ata_port *ap,
1055 unsigned int devmask)
1057 void __iomem *base = (void __iomem *)ap->ioaddr.ctl_addr;
1059 /* software reset. causes dev0 to be selected */
1060 write_atapi_register(base, ATA_REG_CTRL, ap->ctl);
1061 udelay(20);
1062 write_atapi_register(base, ATA_REG_CTRL, ap->ctl | ATA_SRST);
1063 udelay(20);
1064 write_atapi_register(base, ATA_REG_CTRL, ap->ctl);
1066 /* spec mandates ">= 2ms" before checking status.
1067 * We wait 150ms, because that was the magic delay used for
1068 * ATAPI devices in Hale Landis's ATADRVR, for the period of time
1069 * between when the ATA command register is written, and then
1070 * status is checked. Because waiting for "a while" before
1071 * checking status is fine, post SRST, we perform this magic
1072 * delay here as well.
1074 * Old drivers/ide uses the 2mS rule and then waits for ready
1076 msleep(150);
1078 /* Before we perform post reset processing we want to see if
1079 * the bus shows 0xFF because the odd clown forgets the D7
1080 * pulldown resistor.
1082 if (bfin_check_status(ap) == 0xFF)
1083 return 0;
1085 bfin_bus_post_reset(ap, devmask);
1087 return 0;
1091 * bfin_softreset - reset host port via ATA SRST
1092 * @ap: port to reset
1093 * @classes: resulting classes of attached devices
1095 * Note: Original code is ata_sff_softreset().
1098 static int bfin_softreset(struct ata_link *link, unsigned int *classes,
1099 unsigned long deadline)
1101 struct ata_port *ap = link->ap;
1102 unsigned int slave_possible = ap->flags & ATA_FLAG_SLAVE_POSS;
1103 unsigned int devmask = 0, err_mask;
1104 u8 err;
1106 /* determine if device 0/1 are present */
1107 if (bfin_devchk(ap, 0))
1108 devmask |= (1 << 0);
1109 if (slave_possible && bfin_devchk(ap, 1))
1110 devmask |= (1 << 1);
1112 /* select device 0 again */
1113 bfin_dev_select(ap, 0);
1115 /* issue bus reset */
1116 err_mask = bfin_bus_softreset(ap, devmask);
1117 if (err_mask) {
1118 ata_port_printk(ap, KERN_ERR, "SRST failed (err_mask=0x%x)\n",
1119 err_mask);
1120 return -EIO;
1123 /* determine by signature whether we have ATA or ATAPI devices */
1124 classes[0] = ata_sff_dev_classify(&ap->link.device[0],
1125 devmask & (1 << 0), &err);
1126 if (slave_possible && err != 0x81)
1127 classes[1] = ata_sff_dev_classify(&ap->link.device[1],
1128 devmask & (1 << 1), &err);
1130 return 0;
1134 * bfin_bmdma_status - Read IDE DMA status
1135 * @ap: Port associated with this ATA transaction.
1138 static unsigned char bfin_bmdma_status(struct ata_port *ap)
1140 unsigned char host_stat = 0;
1141 void __iomem *base = (void __iomem *)ap->ioaddr.ctl_addr;
1142 unsigned short int_status = ATAPI_GET_INT_STATUS(base);
1144 if (ATAPI_GET_STATUS(base) & (MULTI_XFER_ON|ULTRA_XFER_ON))
1145 host_stat |= ATA_DMA_ACTIVE;
1146 if (int_status & (MULTI_DONE_INT|UDMAIN_DONE_INT|UDMAOUT_DONE_INT|
1147 ATAPI_DEV_INT))
1148 host_stat |= ATA_DMA_INTR;
1149 if (int_status & (MULTI_TERM_INT|UDMAIN_TERM_INT|UDMAOUT_TERM_INT))
1150 host_stat |= ATA_DMA_ERR|ATA_DMA_INTR;
1152 dev_dbg(ap->dev, "ATAPI: host_stat=0x%x\n", host_stat);
1154 return host_stat;
1158 * bfin_data_xfer - Transfer data by PIO
1159 * @adev: device for this I/O
1160 * @buf: data buffer
1161 * @buflen: buffer length
1162 * @write_data: read/write
1164 * Note: Original code is ata_sff_data_xfer().
1167 static unsigned int bfin_data_xfer(struct ata_device *dev, unsigned char *buf,
1168 unsigned int buflen, int rw)
1170 struct ata_port *ap = dev->link->ap;
1171 void __iomem *base = (void __iomem *)ap->ioaddr.ctl_addr;
1172 unsigned int words = buflen >> 1;
1173 unsigned short *buf16 = (u16 *)buf;
1175 /* Transfer multiple of 2 bytes */
1176 if (rw == READ)
1177 read_atapi_data(base, words, buf16);
1178 else
1179 write_atapi_data(base, words, buf16);
1181 /* Transfer trailing 1 byte, if any. */
1182 if (unlikely(buflen & 0x01)) {
1183 unsigned short align_buf[1] = { 0 };
1184 unsigned char *trailing_buf = buf + buflen - 1;
1186 if (rw == READ) {
1187 read_atapi_data(base, 1, align_buf);
1188 memcpy(trailing_buf, align_buf, 1);
1189 } else {
1190 memcpy(align_buf, trailing_buf, 1);
1191 write_atapi_data(base, 1, align_buf);
1193 words++;
1196 return words << 1;
1200 * bfin_irq_clear - Clear ATAPI interrupt.
1201 * @ap: Port associated with this ATA transaction.
1203 * Note: Original code is ata_sff_irq_clear().
1206 static void bfin_irq_clear(struct ata_port *ap)
1208 void __iomem *base = (void __iomem *)ap->ioaddr.ctl_addr;
1210 dev_dbg(ap->dev, "in atapi irq clear\n");
1211 ATAPI_SET_INT_STATUS(base, ATAPI_GET_INT_STATUS(base)|ATAPI_DEV_INT
1212 | MULTI_DONE_INT | UDMAIN_DONE_INT | UDMAOUT_DONE_INT
1213 | MULTI_TERM_INT | UDMAIN_TERM_INT | UDMAOUT_TERM_INT);
1217 * bfin_irq_on - Enable interrupts on a port.
1218 * @ap: Port on which interrupts are enabled.
1220 * Note: Original code is ata_sff_irq_on().
1223 static unsigned char bfin_irq_on(struct ata_port *ap)
1225 void __iomem *base = (void __iomem *)ap->ioaddr.ctl_addr;
1226 u8 tmp;
1228 dev_dbg(ap->dev, "in atapi irq on\n");
1229 ap->ctl &= ~ATA_NIEN;
1230 ap->last_ctl = ap->ctl;
1232 write_atapi_register(base, ATA_REG_CTRL, ap->ctl);
1233 tmp = ata_wait_idle(ap);
1235 bfin_irq_clear(ap);
1237 return tmp;
1241 * bfin_freeze - Freeze DMA controller port
1242 * @ap: port to freeze
1244 * Note: Original code is ata_sff_freeze().
1247 static void bfin_freeze(struct ata_port *ap)
1249 void __iomem *base = (void __iomem *)ap->ioaddr.ctl_addr;
1251 dev_dbg(ap->dev, "in atapi dma freeze\n");
1252 ap->ctl |= ATA_NIEN;
1253 ap->last_ctl = ap->ctl;
1255 write_atapi_register(base, ATA_REG_CTRL, ap->ctl);
1257 /* Under certain circumstances, some controllers raise IRQ on
1258 * ATA_NIEN manipulation. Also, many controllers fail to mask
1259 * previously pending IRQ on ATA_NIEN assertion. Clear it.
1261 ap->ops->sff_check_status(ap);
1263 bfin_irq_clear(ap);
1267 * bfin_thaw - Thaw DMA controller port
1268 * @ap: port to thaw
1270 * Note: Original code is ata_sff_thaw().
1273 void bfin_thaw(struct ata_port *ap)
1275 dev_dbg(ap->dev, "in atapi dma thaw\n");
1276 bfin_check_status(ap);
1277 bfin_irq_on(ap);
1281 * bfin_postreset - standard postreset callback
1282 * @ap: the target ata_port
1283 * @classes: classes of attached devices
1285 * Note: Original code is ata_sff_postreset().
1288 static void bfin_postreset(struct ata_link *link, unsigned int *classes)
1290 struct ata_port *ap = link->ap;
1291 void __iomem *base = (void __iomem *)ap->ioaddr.ctl_addr;
1293 /* re-enable interrupts */
1294 bfin_irq_on(ap);
1296 /* is double-select really necessary? */
1297 if (classes[0] != ATA_DEV_NONE)
1298 bfin_dev_select(ap, 1);
1299 if (classes[1] != ATA_DEV_NONE)
1300 bfin_dev_select(ap, 0);
1302 /* bail out if no device is present */
1303 if (classes[0] == ATA_DEV_NONE && classes[1] == ATA_DEV_NONE) {
1304 return;
1307 /* set up device control */
1308 write_atapi_register(base, ATA_REG_CTRL, ap->ctl);
1311 static void bfin_port_stop(struct ata_port *ap)
1313 dev_dbg(ap->dev, "in atapi port stop\n");
1314 if (ap->udma_mask != 0 || ap->mwdma_mask != 0) {
1315 free_dma(CH_ATAPI_RX);
1316 free_dma(CH_ATAPI_TX);
1320 static int bfin_port_start(struct ata_port *ap)
1322 dev_dbg(ap->dev, "in atapi port start\n");
1323 if (!(ap->udma_mask || ap->mwdma_mask))
1324 return 0;
1326 if (request_dma(CH_ATAPI_RX, "BFIN ATAPI RX DMA") >= 0) {
1327 if (request_dma(CH_ATAPI_TX,
1328 "BFIN ATAPI TX DMA") >= 0)
1329 return 0;
1331 free_dma(CH_ATAPI_RX);
1334 ap->udma_mask = 0;
1335 ap->mwdma_mask = 0;
1336 dev_err(ap->dev, "Unable to request ATAPI DMA!"
1337 " Continue in PIO mode.\n");
1339 return 0;
1342 static unsigned int bfin_ata_host_intr(struct ata_port *ap,
1343 struct ata_queued_cmd *qc)
1345 struct ata_eh_info *ehi = &ap->link.eh_info;
1346 u8 status, host_stat = 0;
1348 VPRINTK("ata%u: protocol %d task_state %d\n",
1349 ap->print_id, qc->tf.protocol, ap->hsm_task_state);
1351 /* Check whether we are expecting interrupt in this state */
1352 switch (ap->hsm_task_state) {
1353 case HSM_ST_FIRST:
1354 /* Some pre-ATAPI-4 devices assert INTRQ
1355 * at this state when ready to receive CDB.
1358 /* Check the ATA_DFLAG_CDB_INTR flag is enough here.
1359 * The flag was turned on only for atapi devices.
1360 * No need to check is_atapi_taskfile(&qc->tf) again.
1362 if (!(qc->dev->flags & ATA_DFLAG_CDB_INTR))
1363 goto idle_irq;
1364 break;
1365 case HSM_ST_LAST:
1366 if (qc->tf.protocol == ATA_PROT_DMA ||
1367 qc->tf.protocol == ATAPI_PROT_DMA) {
1368 /* check status of DMA engine */
1369 host_stat = ap->ops->bmdma_status(ap);
1370 VPRINTK("ata%u: host_stat 0x%X\n",
1371 ap->print_id, host_stat);
1373 /* if it's not our irq... */
1374 if (!(host_stat & ATA_DMA_INTR))
1375 goto idle_irq;
1377 /* before we do anything else, clear DMA-Start bit */
1378 ap->ops->bmdma_stop(qc);
1380 if (unlikely(host_stat & ATA_DMA_ERR)) {
1381 /* error when transfering data to/from memory */
1382 qc->err_mask |= AC_ERR_HOST_BUS;
1383 ap->hsm_task_state = HSM_ST_ERR;
1386 break;
1387 case HSM_ST:
1388 break;
1389 default:
1390 goto idle_irq;
1393 /* check altstatus */
1394 status = ap->ops->sff_check_altstatus(ap);
1395 if (status & ATA_BUSY)
1396 goto busy_ata;
1398 /* check main status, clearing INTRQ */
1399 status = ap->ops->sff_check_status(ap);
1400 if (unlikely(status & ATA_BUSY))
1401 goto busy_ata;
1403 /* ack bmdma irq events */
1404 ap->ops->sff_irq_clear(ap);
1406 ata_sff_hsm_move(ap, qc, status, 0);
1408 if (unlikely(qc->err_mask) && (qc->tf.protocol == ATA_PROT_DMA ||
1409 qc->tf.protocol == ATAPI_PROT_DMA))
1410 ata_ehi_push_desc(ehi, "BMDMA stat 0x%x", host_stat);
1412 busy_ata:
1413 return 1; /* irq handled */
1415 idle_irq:
1416 ap->stats.idle_irq++;
1418 #ifdef ATA_IRQ_TRAP
1419 if ((ap->stats.idle_irq % 1000) == 0) {
1420 ap->ops->irq_ack(ap, 0); /* debug trap */
1421 ata_port_printk(ap, KERN_WARNING, "irq trap\n");
1422 return 1;
1424 #endif
1425 return 0; /* irq not handled */
1428 static irqreturn_t bfin_ata_interrupt(int irq, void *dev_instance)
1430 struct ata_host *host = dev_instance;
1431 unsigned int i;
1432 unsigned int handled = 0;
1433 unsigned long flags;
1435 /* TODO: make _irqsave conditional on x86 PCI IDE legacy mode */
1436 spin_lock_irqsave(&host->lock, flags);
1438 for (i = 0; i < host->n_ports; i++) {
1439 struct ata_port *ap;
1441 ap = host->ports[i];
1442 if (ap &&
1443 !(ap->flags & ATA_FLAG_DISABLED)) {
1444 struct ata_queued_cmd *qc;
1446 qc = ata_qc_from_tag(ap, ap->link.active_tag);
1447 if (qc && (!(qc->tf.flags & ATA_TFLAG_POLLING)) &&
1448 (qc->flags & ATA_QCFLAG_ACTIVE))
1449 handled |= bfin_ata_host_intr(ap, qc);
1453 spin_unlock_irqrestore(&host->lock, flags);
1455 return IRQ_RETVAL(handled);
1459 static struct scsi_host_template bfin_sht = {
1460 ATA_BASE_SHT(DRV_NAME),
1461 .sg_tablesize = SG_NONE,
1462 .dma_boundary = ATA_DMA_BOUNDARY,
1465 static struct ata_port_operations bfin_pata_ops = {
1466 .inherits = &ata_sff_port_ops,
1468 .set_piomode = bfin_set_piomode,
1469 .set_dmamode = bfin_set_dmamode,
1471 .sff_tf_load = bfin_tf_load,
1472 .sff_tf_read = bfin_tf_read,
1473 .sff_exec_command = bfin_exec_command,
1474 .sff_check_status = bfin_check_status,
1475 .sff_check_altstatus = bfin_check_altstatus,
1476 .sff_dev_select = bfin_dev_select,
1478 .bmdma_setup = bfin_bmdma_setup,
1479 .bmdma_start = bfin_bmdma_start,
1480 .bmdma_stop = bfin_bmdma_stop,
1481 .bmdma_status = bfin_bmdma_status,
1482 .sff_data_xfer = bfin_data_xfer,
1484 .qc_prep = ata_noop_qc_prep,
1486 .freeze = bfin_freeze,
1487 .thaw = bfin_thaw,
1488 .softreset = bfin_softreset,
1489 .postreset = bfin_postreset,
1491 .sff_irq_clear = bfin_irq_clear,
1492 .sff_irq_on = bfin_irq_on,
1494 .port_start = bfin_port_start,
1495 .port_stop = bfin_port_stop,
1498 static struct ata_port_info bfin_port_info[] = {
1500 .flags = ATA_FLAG_SLAVE_POSS
1501 | ATA_FLAG_MMIO
1502 | ATA_FLAG_NO_LEGACY,
1503 .pio_mask = 0x1f, /* pio0-4 */
1504 .mwdma_mask = 0,
1505 .udma_mask = 0,
1506 .port_ops = &bfin_pata_ops,
1511 * bfin_reset_controller - initialize BF54x ATAPI controller.
1514 static int bfin_reset_controller(struct ata_host *host)
1516 void __iomem *base = (void __iomem *)host->ports[0]->ioaddr.ctl_addr;
1517 int count;
1518 unsigned short status;
1520 /* Disable all ATAPI interrupts */
1521 ATAPI_SET_INT_MASK(base, 0);
1522 SSYNC();
1524 /* Assert the RESET signal 25us*/
1525 ATAPI_SET_CONTROL(base, ATAPI_GET_CONTROL(base) | DEV_RST);
1526 udelay(30);
1528 /* Negate the RESET signal for 2ms*/
1529 ATAPI_SET_CONTROL(base, ATAPI_GET_CONTROL(base) & ~DEV_RST);
1530 msleep(2);
1532 /* Wait on Busy flag to clear */
1533 count = 10000000;
1534 do {
1535 status = read_atapi_register(base, ATA_REG_STATUS);
1536 } while (--count && (status & ATA_BUSY));
1538 /* Enable only ATAPI Device interrupt */
1539 ATAPI_SET_INT_MASK(base, 1);
1540 SSYNC();
1542 return (!count);
1546 * atapi_io_port - define atapi peripheral port pins.
1548 static unsigned short atapi_io_port[] = {
1549 P_ATAPI_RESET,
1550 P_ATAPI_DIOR,
1551 P_ATAPI_DIOW,
1552 P_ATAPI_CS0,
1553 P_ATAPI_CS1,
1554 P_ATAPI_DMACK,
1555 P_ATAPI_DMARQ,
1556 P_ATAPI_INTRQ,
1557 P_ATAPI_IORDY,
1562 * bfin_atapi_probe - attach a bfin atapi interface
1563 * @pdev: platform device
1565 * Register a bfin atapi interface.
1568 * Platform devices are expected to contain 2 resources per port:
1570 * - I/O Base (IORESOURCE_IO)
1571 * - IRQ (IORESOURCE_IRQ)
1574 static int __devinit bfin_atapi_probe(struct platform_device *pdev)
1576 int board_idx = 0;
1577 struct resource *res;
1578 struct ata_host *host;
1579 unsigned int fsclk = get_sclk();
1580 int udma_mode = 5;
1581 const struct ata_port_info *ppi[] =
1582 { &bfin_port_info[board_idx], NULL };
1585 * Simple resource validation ..
1587 if (unlikely(pdev->num_resources != 2)) {
1588 dev_err(&pdev->dev, "invalid number of resources\n");
1589 return -EINVAL;
1593 * Get the register base first
1595 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1596 if (res == NULL)
1597 return -EINVAL;
1599 while (bfin_port_info[board_idx].udma_mask > 0 &&
1600 udma_fsclk[udma_mode] > fsclk) {
1601 udma_mode--;
1602 bfin_port_info[board_idx].udma_mask >>= 1;
1606 * Now that that's out of the way, wire up the port..
1608 host = ata_host_alloc_pinfo(&pdev->dev, ppi, 1);
1609 if (!host)
1610 return -ENOMEM;
1612 host->ports[0]->ioaddr.ctl_addr = (void *)res->start;
1614 if (peripheral_request_list(atapi_io_port, "atapi-io-port")) {
1615 dev_err(&pdev->dev, "Requesting Peripherals faild\n");
1616 return -EFAULT;
1619 if (bfin_reset_controller(host)) {
1620 peripheral_free_list(atapi_io_port);
1621 dev_err(&pdev->dev, "Fail to reset ATAPI device\n");
1622 return -EFAULT;
1625 if (ata_host_activate(host, platform_get_irq(pdev, 0),
1626 bfin_ata_interrupt, IRQF_SHARED, &bfin_sht) != 0) {
1627 peripheral_free_list(atapi_io_port);
1628 dev_err(&pdev->dev, "Fail to attach ATAPI device\n");
1629 return -ENODEV;
1632 return 0;
1636 * bfin_atapi_remove - unplug a bfin atapi interface
1637 * @pdev: platform device
1639 * A bfin atapi device has been unplugged. Perform the needed
1640 * cleanup. Also called on module unload for any active devices.
1642 static int __devexit bfin_atapi_remove(struct platform_device *pdev)
1644 struct device *dev = &pdev->dev;
1645 struct ata_host *host = dev_get_drvdata(dev);
1647 ata_host_detach(host);
1649 peripheral_free_list(atapi_io_port);
1651 return 0;
1654 #ifdef CONFIG_PM
1655 int bfin_atapi_suspend(struct platform_device *pdev, pm_message_t state)
1657 return 0;
1660 int bfin_atapi_resume(struct platform_device *pdev)
1662 return 0;
1664 #endif
1666 static struct platform_driver bfin_atapi_driver = {
1667 .probe = bfin_atapi_probe,
1668 .remove = __devexit_p(bfin_atapi_remove),
1669 .driver = {
1670 .name = DRV_NAME,
1671 .owner = THIS_MODULE,
1672 #ifdef CONFIG_PM
1673 .suspend = bfin_atapi_suspend,
1674 .resume = bfin_atapi_resume,
1675 #endif
1679 #define ATAPI_MODE_SIZE 10
1680 static char bfin_atapi_mode[ATAPI_MODE_SIZE];
1682 static int __init bfin_atapi_init(void)
1684 pr_info("register bfin atapi driver\n");
1686 switch(bfin_atapi_mode[0]) {
1687 case 'p':
1688 case 'P':
1689 break;
1690 case 'm':
1691 case 'M':
1692 bfin_port_info[0].mwdma_mask = ATA_MWDMA2;
1693 break;
1694 default:
1695 bfin_port_info[0].udma_mask = ATA_UDMA5;
1698 return platform_driver_register(&bfin_atapi_driver);
1701 static void __exit bfin_atapi_exit(void)
1703 platform_driver_unregister(&bfin_atapi_driver);
1706 module_init(bfin_atapi_init);
1707 module_exit(bfin_atapi_exit);
1709 * ATAPI mode:
1710 * pio/PIO
1711 * udma/UDMA (default)
1712 * mwdma/MWDMA
1714 module_param_string(bfin_atapi_mode, bfin_atapi_mode, ATAPI_MODE_SIZE, 0);
1716 MODULE_AUTHOR("Sonic Zhang <sonic.zhang@analog.com>");
1717 MODULE_DESCRIPTION("PATA driver for blackfin 54x ATAPI controller");
1718 MODULE_LICENSE("GPL");
1719 MODULE_VERSION(DRV_VERSION);
1720 MODULE_ALIAS("platform:" DRV_NAME);