ia64/kvm: compilation fix. export account_system_vtime.
[pv_ops_mirror.git] / drivers / ata / pata_hpt366.c
blobf2b83eabc7c7cd2bb59ba198df4f5c85b7b20355
1 /*
2 * Libata driver for the highpoint 366 and 368 UDMA66 ATA controllers.
4 * This driver is heavily based upon:
6 * linux/drivers/ide/pci/hpt366.c Version 0.36 April 25, 2003
8 * Copyright (C) 1999-2003 Andre Hedrick <andre@linux-ide.org>
9 * Portions Copyright (C) 2001 Sun Microsystems, Inc.
10 * Portions Copyright (C) 2003 Red Hat Inc
13 * TODO
14 * Maybe PLL mode
15 * Look into engine reset on timeout errors. Should not be
16 * required.
20 #include <linux/kernel.h>
21 #include <linux/module.h>
22 #include <linux/pci.h>
23 #include <linux/init.h>
24 #include <linux/blkdev.h>
25 #include <linux/delay.h>
26 #include <scsi/scsi_host.h>
27 #include <linux/libata.h>
29 #define DRV_NAME "pata_hpt366"
30 #define DRV_VERSION "0.6.2"
32 struct hpt_clock {
33 u8 xfer_speed;
34 u32 timing;
37 /* key for bus clock timings
38 * bit
39 * 0:3 data_high_time. inactive time of DIOW_/DIOR_ for PIO and MW
40 * DMA. cycles = value + 1
41 * 4:8 data_low_time. active time of DIOW_/DIOR_ for PIO and MW
42 * DMA. cycles = value + 1
43 * 9:12 cmd_high_time. inactive time of DIOW_/DIOR_ during task file
44 * register access.
45 * 13:17 cmd_low_time. active time of DIOW_/DIOR_ during task file
46 * register access.
47 * 18:21 udma_cycle_time. clock freq and clock cycles for UDMA xfer.
48 * during task file register access.
49 * 22:24 pre_high_time. time to initialize 1st cycle for PIO and MW DMA
50 * xfer.
51 * 25:27 cmd_pre_high_time. time to initialize 1st PIO cycle for task
52 * register access.
53 * 28 UDMA enable
54 * 29 DMA enable
55 * 30 PIO_MST enable. if set, the chip is in bus master mode during
56 * PIO.
57 * 31 FIFO enable.
60 static const struct hpt_clock hpt366_40[] = {
61 { XFER_UDMA_4, 0x900fd943 },
62 { XFER_UDMA_3, 0x900ad943 },
63 { XFER_UDMA_2, 0x900bd943 },
64 { XFER_UDMA_1, 0x9008d943 },
65 { XFER_UDMA_0, 0x9008d943 },
67 { XFER_MW_DMA_2, 0xa008d943 },
68 { XFER_MW_DMA_1, 0xa010d955 },
69 { XFER_MW_DMA_0, 0xa010d9fc },
71 { XFER_PIO_4, 0xc008d963 },
72 { XFER_PIO_3, 0xc010d974 },
73 { XFER_PIO_2, 0xc010d997 },
74 { XFER_PIO_1, 0xc010d9c7 },
75 { XFER_PIO_0, 0xc018d9d9 },
76 { 0, 0x0120d9d9 }
79 static const struct hpt_clock hpt366_33[] = {
80 { XFER_UDMA_4, 0x90c9a731 },
81 { XFER_UDMA_3, 0x90cfa731 },
82 { XFER_UDMA_2, 0x90caa731 },
83 { XFER_UDMA_1, 0x90cba731 },
84 { XFER_UDMA_0, 0x90c8a731 },
86 { XFER_MW_DMA_2, 0xa0c8a731 },
87 { XFER_MW_DMA_1, 0xa0c8a732 }, /* 0xa0c8a733 */
88 { XFER_MW_DMA_0, 0xa0c8a797 },
90 { XFER_PIO_4, 0xc0c8a731 },
91 { XFER_PIO_3, 0xc0c8a742 },
92 { XFER_PIO_2, 0xc0d0a753 },
93 { XFER_PIO_1, 0xc0d0a7a3 }, /* 0xc0d0a793 */
94 { XFER_PIO_0, 0xc0d0a7aa }, /* 0xc0d0a7a7 */
95 { 0, 0x0120a7a7 }
98 static const struct hpt_clock hpt366_25[] = {
99 { XFER_UDMA_4, 0x90c98521 },
100 { XFER_UDMA_3, 0x90cf8521 },
101 { XFER_UDMA_2, 0x90cf8521 },
102 { XFER_UDMA_1, 0x90cb8521 },
103 { XFER_UDMA_0, 0x90cb8521 },
105 { XFER_MW_DMA_2, 0xa0ca8521 },
106 { XFER_MW_DMA_1, 0xa0ca8532 },
107 { XFER_MW_DMA_0, 0xa0ca8575 },
109 { XFER_PIO_4, 0xc0ca8521 },
110 { XFER_PIO_3, 0xc0ca8532 },
111 { XFER_PIO_2, 0xc0ca8542 },
112 { XFER_PIO_1, 0xc0d08572 },
113 { XFER_PIO_0, 0xc0d08585 },
114 { 0, 0x01208585 }
117 static const char *bad_ata33[] = {
118 "Maxtor 92720U8", "Maxtor 92040U6", "Maxtor 91360U4", "Maxtor 91020U3", "Maxtor 90845U3", "Maxtor 90650U2",
119 "Maxtor 91360D8", "Maxtor 91190D7", "Maxtor 91020D6", "Maxtor 90845D5", "Maxtor 90680D4", "Maxtor 90510D3", "Maxtor 90340D2",
120 "Maxtor 91152D8", "Maxtor 91008D7", "Maxtor 90845D6", "Maxtor 90840D6", "Maxtor 90720D5", "Maxtor 90648D5", "Maxtor 90576D4",
121 "Maxtor 90510D4",
122 "Maxtor 90432D3", "Maxtor 90288D2", "Maxtor 90256D2",
123 "Maxtor 91000D8", "Maxtor 90910D8", "Maxtor 90875D7", "Maxtor 90840D7", "Maxtor 90750D6", "Maxtor 90625D5", "Maxtor 90500D4",
124 "Maxtor 91728D8", "Maxtor 91512D7", "Maxtor 91303D6", "Maxtor 91080D5", "Maxtor 90845D4", "Maxtor 90680D4", "Maxtor 90648D3", "Maxtor 90432D2",
125 NULL
128 static const char *bad_ata66_4[] = {
129 "IBM-DTLA-307075",
130 "IBM-DTLA-307060",
131 "IBM-DTLA-307045",
132 "IBM-DTLA-307030",
133 "IBM-DTLA-307020",
134 "IBM-DTLA-307015",
135 "IBM-DTLA-305040",
136 "IBM-DTLA-305030",
137 "IBM-DTLA-305020",
138 "IC35L010AVER07-0",
139 "IC35L020AVER07-0",
140 "IC35L030AVER07-0",
141 "IC35L040AVER07-0",
142 "IC35L060AVER07-0",
143 "WDC AC310200R",
144 NULL
147 static const char *bad_ata66_3[] = {
148 "WDC AC310200R",
149 NULL
152 static int hpt_dma_blacklisted(const struct ata_device *dev, char *modestr, const char *list[])
154 unsigned char model_num[ATA_ID_PROD_LEN + 1];
155 int i = 0;
157 ata_id_c_string(dev->id, model_num, ATA_ID_PROD, sizeof(model_num));
159 while (list[i] != NULL) {
160 if (!strcmp(list[i], model_num)) {
161 printk(KERN_WARNING DRV_NAME ": %s is not supported for %s.\n",
162 modestr, list[i]);
163 return 1;
165 i++;
167 return 0;
171 * hpt366_filter - mode selection filter
172 * @adev: ATA device
174 * Block UDMA on devices that cause trouble with this controller.
177 static unsigned long hpt366_filter(struct ata_device *adev, unsigned long mask)
179 if (adev->class == ATA_DEV_ATA) {
180 if (hpt_dma_blacklisted(adev, "UDMA", bad_ata33))
181 mask &= ~ATA_MASK_UDMA;
182 if (hpt_dma_blacklisted(adev, "UDMA3", bad_ata66_3))
183 mask &= ~(0xF8 << ATA_SHIFT_UDMA);
184 if (hpt_dma_blacklisted(adev, "UDMA4", bad_ata66_4))
185 mask &= ~(0xF0 << ATA_SHIFT_UDMA);
187 return ata_bmdma_mode_filter(adev, mask);
191 * hpt36x_find_mode - reset the hpt36x bus
192 * @ap: ATA port
193 * @speed: transfer mode
195 * Return the 32bit register programming information for this channel
196 * that matches the speed provided.
199 static u32 hpt36x_find_mode(struct ata_port *ap, int speed)
201 struct hpt_clock *clocks = ap->host->private_data;
203 while(clocks->xfer_speed) {
204 if (clocks->xfer_speed == speed)
205 return clocks->timing;
206 clocks++;
208 BUG();
209 return 0xffffffffU; /* silence compiler warning */
212 static int hpt36x_cable_detect(struct ata_port *ap)
214 u8 ata66;
215 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
217 pci_read_config_byte(pdev, 0x5A, &ata66);
218 if (ata66 & (1 << ap->port_no))
219 return ATA_CBL_PATA40;
220 return ATA_CBL_PATA80;
224 * hpt366_set_piomode - PIO setup
225 * @ap: ATA interface
226 * @adev: device on the interface
228 * Perform PIO mode setup.
231 static void hpt366_set_piomode(struct ata_port *ap, struct ata_device *adev)
233 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
234 u32 addr1, addr2;
235 u32 reg;
236 u32 mode;
237 u8 fast;
239 addr1 = 0x40 + 4 * (adev->devno + 2 * ap->port_no);
240 addr2 = 0x51 + 4 * ap->port_no;
242 /* Fast interrupt prediction disable, hold off interrupt disable */
243 pci_read_config_byte(pdev, addr2, &fast);
244 if (fast & 0x80) {
245 fast &= ~0x80;
246 pci_write_config_byte(pdev, addr2, fast);
249 pci_read_config_dword(pdev, addr1, &reg);
250 mode = hpt36x_find_mode(ap, adev->pio_mode);
251 mode &= ~0x8000000; /* No FIFO in PIO */
252 mode &= ~0x30070000; /* Leave config bits alone */
253 reg &= 0x30070000; /* Strip timing bits */
254 pci_write_config_dword(pdev, addr1, reg | mode);
258 * hpt366_set_dmamode - DMA timing setup
259 * @ap: ATA interface
260 * @adev: Device being configured
262 * Set up the channel for MWDMA or UDMA modes. Much the same as with
263 * PIO, load the mode number and then set MWDMA or UDMA flag.
266 static void hpt366_set_dmamode(struct ata_port *ap, struct ata_device *adev)
268 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
269 u32 addr1, addr2;
270 u32 reg;
271 u32 mode;
272 u8 fast;
274 addr1 = 0x40 + 4 * (adev->devno + 2 * ap->port_no);
275 addr2 = 0x51 + 4 * ap->port_no;
277 /* Fast interrupt prediction disable, hold off interrupt disable */
278 pci_read_config_byte(pdev, addr2, &fast);
279 if (fast & 0x80) {
280 fast &= ~0x80;
281 pci_write_config_byte(pdev, addr2, fast);
284 pci_read_config_dword(pdev, addr1, &reg);
285 mode = hpt36x_find_mode(ap, adev->dma_mode);
286 mode |= 0x8000000; /* FIFO in MWDMA or UDMA */
287 mode &= ~0xC0000000; /* Leave config bits alone */
288 reg &= 0xC0000000; /* Strip timing bits */
289 pci_write_config_dword(pdev, addr1, reg | mode);
292 static struct scsi_host_template hpt36x_sht = {
293 ATA_BMDMA_SHT(DRV_NAME),
297 * Configuration for HPT366/68
300 static struct ata_port_operations hpt366_port_ops = {
301 .inherits = &ata_bmdma_port_ops,
302 .cable_detect = hpt36x_cable_detect,
303 .mode_filter = hpt366_filter,
304 .set_piomode = hpt366_set_piomode,
305 .set_dmamode = hpt366_set_dmamode,
309 * hpt36x_init_chipset - common chip setup
310 * @dev: PCI device
312 * Perform the chip setup work that must be done at both init and
313 * resume time
316 static void hpt36x_init_chipset(struct pci_dev *dev)
318 u8 drive_fast;
319 pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, (L1_CACHE_BYTES / 4));
320 pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0x78);
321 pci_write_config_byte(dev, PCI_MIN_GNT, 0x08);
322 pci_write_config_byte(dev, PCI_MAX_LAT, 0x08);
324 pci_read_config_byte(dev, 0x51, &drive_fast);
325 if (drive_fast & 0x80)
326 pci_write_config_byte(dev, 0x51, drive_fast & ~0x80);
330 * hpt36x_init_one - Initialise an HPT366/368
331 * @dev: PCI device
332 * @id: Entry in match table
334 * Initialise an HPT36x device. There are some interesting complications
335 * here. Firstly the chip may report 366 and be one of several variants.
336 * Secondly all the timings depend on the clock for the chip which we must
337 * detect and look up
339 * This is the known chip mappings. It may be missing a couple of later
340 * releases.
342 * Chip version PCI Rev Notes
343 * HPT366 4 (HPT366) 0 UDMA66
344 * HPT366 4 (HPT366) 1 UDMA66
345 * HPT368 4 (HPT366) 2 UDMA66
346 * HPT37x/30x 4 (HPT366) 3+ Other driver
350 static int hpt36x_init_one(struct pci_dev *dev, const struct pci_device_id *id)
352 static const struct ata_port_info info_hpt366 = {
353 .flags = ATA_FLAG_SLAVE_POSS,
354 .pio_mask = 0x1f,
355 .mwdma_mask = 0x07,
356 .udma_mask = ATA_UDMA4,
357 .port_ops = &hpt366_port_ops
359 const struct ata_port_info *ppi[] = { &info_hpt366, NULL };
361 void *hpriv = NULL;
362 u32 class_rev;
363 u32 reg1;
364 int rc;
366 rc = pcim_enable_device(dev);
367 if (rc)
368 return rc;
370 pci_read_config_dword(dev, PCI_CLASS_REVISION, &class_rev);
371 class_rev &= 0xFF;
373 /* May be a later chip in disguise. Check */
374 /* Newer chips are not in the HPT36x driver. Ignore them */
375 if (class_rev > 2)
376 return -ENODEV;
378 hpt36x_init_chipset(dev);
380 pci_read_config_dword(dev, 0x40, &reg1);
382 /* PCI clocking determines the ATA timing values to use */
383 /* info_hpt366 is safe against re-entry so we can scribble on it */
384 switch((reg1 & 0x700) >> 8) {
385 case 5:
386 hpriv = &hpt366_40;
387 break;
388 case 9:
389 hpriv = &hpt366_25;
390 break;
391 default:
392 hpriv = &hpt366_33;
393 break;
395 /* Now kick off ATA set up */
396 return ata_pci_sff_init_one(dev, ppi, &hpt36x_sht, hpriv);
399 #ifdef CONFIG_PM
400 static int hpt36x_reinit_one(struct pci_dev *dev)
402 struct ata_host *host = dev_get_drvdata(&dev->dev);
403 int rc;
405 rc = ata_pci_device_do_resume(dev);
406 if (rc)
407 return rc;
408 hpt36x_init_chipset(dev);
409 ata_host_resume(host);
410 return 0;
412 #endif
414 static const struct pci_device_id hpt36x[] = {
415 { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT366), },
416 { },
419 static struct pci_driver hpt36x_pci_driver = {
420 .name = DRV_NAME,
421 .id_table = hpt36x,
422 .probe = hpt36x_init_one,
423 .remove = ata_pci_remove_one,
424 #ifdef CONFIG_PM
425 .suspend = ata_pci_device_suspend,
426 .resume = hpt36x_reinit_one,
427 #endif
430 static int __init hpt36x_init(void)
432 return pci_register_driver(&hpt36x_pci_driver);
435 static void __exit hpt36x_exit(void)
437 pci_unregister_driver(&hpt36x_pci_driver);
440 MODULE_AUTHOR("Alan Cox");
441 MODULE_DESCRIPTION("low-level driver for the Highpoint HPT366/368");
442 MODULE_LICENSE("GPL");
443 MODULE_DEVICE_TABLE(pci, hpt36x);
444 MODULE_VERSION(DRV_VERSION);
446 module_init(hpt36x_init);
447 module_exit(hpt36x_exit);