2 * pata_ns87415.c - NS87415 (non PARISC) PATA
4 * (C) 2005 Red Hat <alan@redhat.com>
6 * This is a fairly generic MWDMA controller. It has some limitations
7 * as it requires timing reloads on PIO/DMA transitions but it is otherwise
8 * fairly well designed.
10 * This driver assumes the firmware has left the chip in a valid ST506
11 * compliant state, either legacy IRQ 14/15 or native INTA shared. You
12 * may need to add platform code if your system fails to do this.
14 * The same cell appears in the 87560 controller used by some PARISC
15 * systems. This has its own special mountain of errata.
19 * Get someone to test on SPARC
20 * Implement lazy pio/dma switching for better performance
22 * See if we need to kill the FIFO for ATAPI
25 #include <linux/kernel.h>
26 #include <linux/module.h>
27 #include <linux/pci.h>
28 #include <linux/init.h>
29 #include <linux/blkdev.h>
30 #include <linux/delay.h>
31 #include <linux/device.h>
32 #include <scsi/scsi_host.h>
33 #include <linux/libata.h>
34 #include <linux/ata.h>
36 #define DRV_NAME "pata_ns87415"
37 #define DRV_VERSION "0.0.1"
40 * ns87415_set_mode - Initialize host controller mode timings
41 * @ap: Port whose timings we are configuring
42 * @adev: Device whose timings we are configuring
45 * Program the mode registers for this controller, channel and
46 * device. Because the chip is quite an old design we have to do this
47 * for PIO/DMA switches.
50 * None (inherited from caller).
53 static void ns87415_set_mode(struct ata_port
*ap
, struct ata_device
*adev
, u8 mode
)
55 struct pci_dev
*dev
= to_pci_dev(ap
->host
->dev
);
56 int unit
= 2 * ap
->port_no
+ adev
->devno
;
57 int timing
= 0x44 + 2 * unit
;
58 unsigned long T
= 1000000000 / 33333; /* PCI clocks */
64 /* Timing register format is 17 - low nybble read timing with
65 the high nybble being 16 - x for recovery time in PCI clocks */
67 ata_timing_compute(adev
, adev
->pio_mode
, &t
, T
, 0);
69 clocking
= 17 - FIT(t
.active
, 2, 17);
70 clocking
|= (16 - FIT(t
.recover
, 1, 16)) << 4;
71 /* Use the same timing for read and write bytes */
72 clocking
|= (clocking
<< 8);
73 pci_write_config_word(dev
, timing
, clocking
);
75 /* Set the IORDY enable versus DMA enable on or off properly */
76 pci_read_config_byte(dev
, 0x42, &iordy
);
77 iordy
&= ~(1 << (4 + unit
));
78 if (mode
>= XFER_MW_DMA_0
|| !ata_pio_need_iordy(adev
))
79 iordy
|= (1 << (4 + unit
));
81 /* Paranoia: We shouldn't ever get here with busy write buffers
84 pci_read_config_byte(dev
, 0x43, &status
);
85 while (status
& 0x03) {
87 pci_read_config_byte(dev
, 0x43, &status
);
89 /* Flip the IORDY/DMA bits now we are sure the write buffers are
91 pci_write_config_byte(dev
, 0x42, iordy
);
93 /* TODO: Set byte 54 command timing to the best 8bit
94 mode shared by all four devices */
98 * ns87415_set_piomode - Initialize host controller PATA PIO timings
99 * @ap: Port whose timings we are configuring
100 * @adev: Device to program
102 * Set PIO mode for device, in host controller PCI config space.
105 * None (inherited from caller).
108 static void ns87415_set_piomode(struct ata_port
*ap
, struct ata_device
*adev
)
110 ns87415_set_mode(ap
, adev
, adev
->pio_mode
);
114 * ns87415_bmdma_setup - Set up DMA
117 * Set up for bus masterng DMA. We have to do this ourselves
118 * rather than use the helper due to a chip erratum
121 static void ns87415_bmdma_setup(struct ata_queued_cmd
*qc
)
123 struct ata_port
*ap
= qc
->ap
;
124 unsigned int rw
= (qc
->tf
.flags
& ATA_TFLAG_WRITE
);
127 /* load PRD table addr. */
128 mb(); /* make sure PRD table writes are visible to controller */
129 iowrite32(ap
->prd_dma
, ap
->ioaddr
.bmdma_addr
+ ATA_DMA_TABLE_OFS
);
131 /* specify data direction, triple-check start bit is clear */
132 dmactl
= ioread8(ap
->ioaddr
.bmdma_addr
+ ATA_DMA_CMD
);
133 dmactl
&= ~(ATA_DMA_WR
| ATA_DMA_START
);
134 /* Due to an erratum we need to write these bits to the wrong
135 place - which does save us an I/O bizarrely */
136 dmactl
|= ATA_DMA_INTR
| ATA_DMA_ERR
;
138 dmactl
|= ATA_DMA_WR
;
139 iowrite8(dmactl
, ap
->ioaddr
.bmdma_addr
+ ATA_DMA_CMD
);
140 /* issue r/w command */
141 ap
->ops
->sff_exec_command(ap
, &qc
->tf
);
145 * ns87415_bmdma_start - Begin DMA transfer
148 * Switch the timings for the chip and set up for a DMA transfer
149 * before the DMA burst begins.
151 * FIXME: We should do lazy switching on bmdma_start versus
152 * ata_pio_data_xfer for better performance.
155 static void ns87415_bmdma_start(struct ata_queued_cmd
*qc
)
157 ns87415_set_mode(qc
->ap
, qc
->dev
, qc
->dev
->dma_mode
);
162 * ns87415_bmdma_stop - End DMA transfer
165 * End DMA mode and switch the controller back into PIO mode
168 static void ns87415_bmdma_stop(struct ata_queued_cmd
*qc
)
171 ns87415_set_mode(qc
->ap
, qc
->dev
, qc
->dev
->pio_mode
);
175 * ns87415_irq_clear - Clear interrupt
176 * @ap: Channel to clear
178 * Erratum: Due to a chip bug regisers 02 and 0A bit 1 and 2 (the
179 * error bits) are reset by writing to register 00 or 08.
182 static void ns87415_irq_clear(struct ata_port
*ap
)
184 void __iomem
*mmio
= ap
->ioaddr
.bmdma_addr
;
188 iowrite8((ioread8(mmio
+ ATA_DMA_CMD
) | ATA_DMA_INTR
| ATA_DMA_ERR
),
193 * ns87415_check_atapi_dma - ATAPI DMA filter
196 * Disable ATAPI DMA (for now). We may be able to do DMA if we
197 * kill the prefetching. This isn't clear.
200 static int ns87415_check_atapi_dma(struct ata_queued_cmd
*qc
)
205 #if defined(CONFIG_SUPERIO)
207 /* SUPERIO 87560 is a PoS chip that NatSem denies exists.
208 * Unfortunately, it's built-in on all Astro-based PA-RISC workstations
209 * which use the integrated NS87514 cell for CD-ROM support.
210 * i.e we have to support for CD-ROM installs.
211 * See drivers/parisc/superio.c for more gory details.
213 * Workarounds taken from drivers/ide/pci/ns87415.c
216 #include <asm/superio.h>
218 #define SUPERIO_IDE_MAX_RETRIES 25
221 * ns87560_read_buggy - workaround buggy Super I/O chip
222 * @port: Port to read
224 * Work around chipset problems in the 87560 SuperIO chip
227 static u8
ns87560_read_buggy(void __iomem
*port
)
230 int retries
= SUPERIO_IDE_MAX_RETRIES
;
236 } while(retries
-- > 0);
241 * ns87560_check_status
242 * @ap: channel to check
244 * Return the status of the channel working around the
248 static u8
ns87560_check_status(struct ata_port
*ap
)
250 return ns87560_read_buggy(ap
->ioaddr
.status_addr
);
254 * ns87560_tf_read - input device's ATA taskfile shadow registers
255 * @ap: Port from which input is read
256 * @tf: ATA taskfile register set for storing input
258 * Reads ATA taskfile registers for currently-selected device
259 * into @tf. Work around the 87560 bugs.
262 * Inherited from caller.
264 void ns87560_tf_read(struct ata_port
*ap
, struct ata_taskfile
*tf
)
266 struct ata_ioports
*ioaddr
= &ap
->ioaddr
;
268 tf
->command
= ns87560_check_status(ap
);
269 tf
->feature
= ioread8(ioaddr
->error_addr
);
270 tf
->nsect
= ioread8(ioaddr
->nsect_addr
);
271 tf
->lbal
= ioread8(ioaddr
->lbal_addr
);
272 tf
->lbam
= ioread8(ioaddr
->lbam_addr
);
273 tf
->lbah
= ioread8(ioaddr
->lbah_addr
);
274 tf
->device
= ns87560_read_buggy(ioaddr
->device_addr
);
276 if (tf
->flags
& ATA_TFLAG_LBA48
) {
277 iowrite8(tf
->ctl
| ATA_HOB
, ioaddr
->ctl_addr
);
278 tf
->hob_feature
= ioread8(ioaddr
->error_addr
);
279 tf
->hob_nsect
= ioread8(ioaddr
->nsect_addr
);
280 tf
->hob_lbal
= ioread8(ioaddr
->lbal_addr
);
281 tf
->hob_lbam
= ioread8(ioaddr
->lbam_addr
);
282 tf
->hob_lbah
= ioread8(ioaddr
->lbah_addr
);
283 iowrite8(tf
->ctl
, ioaddr
->ctl_addr
);
284 ap
->last_ctl
= tf
->ctl
;
289 * ns87560_bmdma_status
290 * @ap: channel to check
292 * Return the DMA status of the channel working around the
296 static u8
ns87560_bmdma_status(struct ata_port
*ap
)
298 return ns87560_read_buggy(ap
->ioaddr
.bmdma_addr
+ ATA_DMA_STATUS
);
300 #endif /* 87560 SuperIO Support */
302 static struct ata_port_operations ns87415_pata_ops
= {
303 .inherits
= &ata_bmdma_port_ops
,
305 .check_atapi_dma
= ns87415_check_atapi_dma
,
306 .bmdma_setup
= ns87415_bmdma_setup
,
307 .bmdma_start
= ns87415_bmdma_start
,
308 .bmdma_stop
= ns87415_bmdma_stop
,
309 .sff_irq_clear
= ns87415_irq_clear
,
311 .cable_detect
= ata_cable_40wire
,
312 .set_piomode
= ns87415_set_piomode
,
315 #if defined(CONFIG_SUPERIO)
316 static struct ata_port_operations ns87560_pata_ops
= {
317 .inherits
= &ns87415_pata_ops
,
318 .sff_tf_read
= ns87560_tf_read
,
319 .sff_check_status
= ns87560_check_status
,
320 .bmdma_status
= ns87560_bmdma_status
,
324 static struct scsi_host_template ns87415_sht
= {
325 ATA_BMDMA_SHT(DRV_NAME
),
330 * ns87415_init_one - Register 87415 ATA PCI device with kernel services
331 * @pdev: PCI device to register
332 * @ent: Entry in ns87415_pci_tbl matching with @pdev
334 * Called from kernel PCI layer. We probe for combined mode (sigh),
335 * and then hand over control to libata, for it to do the rest.
338 * Inherited from PCI layer (may sleep).
341 * Zero on success, or -ERRNO value.
344 static int ns87415_init_one (struct pci_dev
*pdev
, const struct pci_device_id
*ent
)
346 static int printed_version
;
347 static const struct ata_port_info info
= {
348 .flags
= ATA_FLAG_SLAVE_POSS
,
349 .pio_mask
= 0x1f, /* pio0-4 */
350 .mwdma_mask
= 0x07, /* mwdma0-2 */
351 .port_ops
= &ns87415_pata_ops
,
353 const struct ata_port_info
*ppi
[] = { &info
, NULL
};
355 #if defined(CONFIG_SUPERIO)
356 static const struct ata_port_info info87560
= {
357 .flags
= ATA_FLAG_SLAVE_POSS
,
358 .pio_mask
= 0x1f, /* pio0-4 */
359 .mwdma_mask
= 0x07, /* mwdma0-2 */
360 .port_ops
= &ns87560_pata_ops
,
363 if (PCI_SLOT(pdev
->devfn
) == 0x0E)
366 if (!printed_version
++)
367 dev_printk(KERN_DEBUG
, &pdev
->dev
,
368 "version " DRV_VERSION
"\n");
370 rc
= pcim_enable_device(pdev
);
374 /* Select 512 byte sectors */
375 pci_write_config_byte(pdev
, 0x55, 0xEE);
376 /* Select PIO0 8bit clocking */
377 pci_write_config_byte(pdev
, 0x54, 0xB7);
378 return ata_pci_sff_init_one(pdev
, ppi
, &ns87415_sht
, NULL
);
381 static const struct pci_device_id ns87415_pci_tbl
[] = {
382 { PCI_VDEVICE(NS
, PCI_DEVICE_ID_NS_87415
), },
384 { } /* terminate list */
387 static struct pci_driver ns87415_pci_driver
= {
389 .id_table
= ns87415_pci_tbl
,
390 .probe
= ns87415_init_one
,
391 .remove
= ata_pci_remove_one
,
393 .suspend
= ata_pci_device_suspend
,
394 .resume
= ata_pci_device_resume
,
398 static int __init
ns87415_init(void)
400 return pci_register_driver(&ns87415_pci_driver
);
403 static void __exit
ns87415_exit(void)
405 pci_unregister_driver(&ns87415_pci_driver
);
408 module_init(ns87415_init
);
409 module_exit(ns87415_exit
);
411 MODULE_AUTHOR("Alan Cox");
412 MODULE_DESCRIPTION("ATA low-level driver for NS87415 controllers");
413 MODULE_LICENSE("GPL");
414 MODULE_DEVICE_TABLE(pci
, ns87415_pci_tbl
);
415 MODULE_VERSION(DRV_VERSION
);