ia64/kvm: compilation fix. export account_system_vtime.
[pv_ops_mirror.git] / drivers / ata / sata_sis.c
blob1010b3069bd5164bb9ded003df2d41371c4f91c9
1 /*
2 * sata_sis.c - Silicon Integrated Systems SATA
4 * Maintained by: Uwe Koziolek
5 * Please ALWAYS copy linux-ide@vger.kernel.org
6 * on emails.
8 * Copyright 2004 Uwe Koziolek
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2, or (at your option)
14 * any later version.
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program; see the file COPYING. If not, write to
23 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
26 * libata documentation is available via 'make {ps|pdf}docs',
27 * as Documentation/DocBook/libata.*
29 * Hardware documentation available under NDA.
33 #include <linux/kernel.h>
34 #include <linux/module.h>
35 #include <linux/pci.h>
36 #include <linux/init.h>
37 #include <linux/blkdev.h>
38 #include <linux/delay.h>
39 #include <linux/interrupt.h>
40 #include <linux/device.h>
41 #include <scsi/scsi_host.h>
42 #include <linux/libata.h>
43 #include "sis.h"
45 #define DRV_NAME "sata_sis"
46 #define DRV_VERSION "1.0"
48 enum {
49 sis_180 = 0,
50 SIS_SCR_PCI_BAR = 5,
52 /* PCI configuration registers */
53 SIS_GENCTL = 0x54, /* IDE General Control register */
54 SIS_SCR_BASE = 0xc0, /* sata0 phy SCR registers */
55 SIS180_SATA1_OFS = 0x10, /* offset from sata0->sata1 phy regs */
56 SIS182_SATA1_OFS = 0x20, /* offset from sata0->sata1 phy regs */
57 SIS_PMR = 0x90, /* port mapping register */
58 SIS_PMR_COMBINED = 0x30,
60 /* random bits */
61 SIS_FLAG_CFGSCR = (1 << 30), /* host flag: SCRs via PCI cfg */
63 GENCTL_IOMAPPED_SCR = (1 << 26), /* if set, SCRs are in IO space */
66 static int sis_init_one(struct pci_dev *pdev, const struct pci_device_id *ent);
67 static int sis_scr_read(struct ata_port *ap, unsigned int sc_reg, u32 *val);
68 static int sis_scr_write(struct ata_port *ap, unsigned int sc_reg, u32 val);
70 static const struct pci_device_id sis_pci_tbl[] = {
71 { PCI_VDEVICE(SI, 0x0180), sis_180 }, /* SiS 964/180 */
72 { PCI_VDEVICE(SI, 0x0181), sis_180 }, /* SiS 964/180 */
73 { PCI_VDEVICE(SI, 0x0182), sis_180 }, /* SiS 965/965L */
74 { PCI_VDEVICE(SI, 0x0183), sis_180 }, /* SiS 965/965L */
75 { PCI_VDEVICE(SI, 0x1182), sis_180 }, /* SiS 966/680 */
76 { PCI_VDEVICE(SI, 0x1183), sis_180 }, /* SiS 966/966L/968/680 */
78 { } /* terminate list */
81 static struct pci_driver sis_pci_driver = {
82 .name = DRV_NAME,
83 .id_table = sis_pci_tbl,
84 .probe = sis_init_one,
85 .remove = ata_pci_remove_one,
88 static struct scsi_host_template sis_sht = {
89 ATA_BMDMA_SHT(DRV_NAME),
92 static struct ata_port_operations sis_ops = {
93 .inherits = &ata_bmdma_port_ops,
94 .scr_read = sis_scr_read,
95 .scr_write = sis_scr_write,
98 static const struct ata_port_info sis_port_info = {
99 .flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY,
100 .pio_mask = 0x1f,
101 .mwdma_mask = 0x7,
102 .udma_mask = ATA_UDMA6,
103 .port_ops = &sis_ops,
106 MODULE_AUTHOR("Uwe Koziolek");
107 MODULE_DESCRIPTION("low-level driver for Silicon Integratad Systems SATA controller");
108 MODULE_LICENSE("GPL");
109 MODULE_DEVICE_TABLE(pci, sis_pci_tbl);
110 MODULE_VERSION(DRV_VERSION);
112 static unsigned int get_scr_cfg_addr(struct ata_port *ap, unsigned int sc_reg)
114 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
115 unsigned int addr = SIS_SCR_BASE + (4 * sc_reg);
116 u8 pmr;
118 if (ap->port_no) {
119 switch (pdev->device) {
120 case 0x0180:
121 case 0x0181:
122 pci_read_config_byte(pdev, SIS_PMR, &pmr);
123 if ((pmr & SIS_PMR_COMBINED) == 0)
124 addr += SIS180_SATA1_OFS;
125 break;
127 case 0x0182:
128 case 0x0183:
129 case 0x1182:
130 addr += SIS182_SATA1_OFS;
131 break;
134 return addr;
137 static u32 sis_scr_cfg_read(struct ata_port *ap, unsigned int sc_reg, u32 *val)
139 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
140 unsigned int cfg_addr = get_scr_cfg_addr(ap, sc_reg);
141 u32 val2 = 0;
142 u8 pmr;
144 if (sc_reg == SCR_ERROR) /* doesn't exist in PCI cfg space */
145 return -EINVAL;
147 pci_read_config_byte(pdev, SIS_PMR, &pmr);
149 pci_read_config_dword(pdev, cfg_addr, val);
151 if ((pdev->device == 0x0182) || (pdev->device == 0x0183) ||
152 (pdev->device == 0x1182) || (pmr & SIS_PMR_COMBINED))
153 pci_read_config_dword(pdev, cfg_addr+0x10, &val2);
155 *val |= val2;
156 *val &= 0xfffffffb; /* avoid problems with powerdowned ports */
158 return 0;
161 static int sis_scr_cfg_write(struct ata_port *ap, unsigned int sc_reg, u32 val)
163 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
164 unsigned int cfg_addr = get_scr_cfg_addr(ap, sc_reg);
165 u8 pmr;
167 if (sc_reg == SCR_ERROR) /* doesn't exist in PCI cfg space */
168 return -EINVAL;
170 pci_read_config_byte(pdev, SIS_PMR, &pmr);
172 pci_write_config_dword(pdev, cfg_addr, val);
174 if ((pdev->device == 0x0182) || (pdev->device == 0x0183) ||
175 (pdev->device == 0x1182) || (pmr & SIS_PMR_COMBINED))
176 pci_write_config_dword(pdev, cfg_addr+0x10, val);
178 return 0;
181 static int sis_scr_read(struct ata_port *ap, unsigned int sc_reg, u32 *val)
183 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
184 u8 pmr;
186 if (sc_reg > SCR_CONTROL)
187 return -EINVAL;
189 if (ap->flags & SIS_FLAG_CFGSCR)
190 return sis_scr_cfg_read(ap, sc_reg, val);
192 pci_read_config_byte(pdev, SIS_PMR, &pmr);
194 *val = ioread32(ap->ioaddr.scr_addr + (sc_reg * 4));
196 if ((pdev->device == 0x0182) || (pdev->device == 0x0183) ||
197 (pdev->device == 0x1182) || (pmr & SIS_PMR_COMBINED))
198 *val |= ioread32(ap->ioaddr.scr_addr + (sc_reg * 4) + 0x10);
200 *val &= 0xfffffffb;
202 return 0;
205 static int sis_scr_write(struct ata_port *ap, unsigned int sc_reg, u32 val)
207 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
208 u8 pmr;
210 if (sc_reg > SCR_CONTROL)
211 return -EINVAL;
213 pci_read_config_byte(pdev, SIS_PMR, &pmr);
215 if (ap->flags & SIS_FLAG_CFGSCR)
216 return sis_scr_cfg_write(ap, sc_reg, val);
217 else {
218 iowrite32(val, ap->ioaddr.scr_addr + (sc_reg * 4));
219 if ((pdev->device == 0x0182) || (pdev->device == 0x0183) ||
220 (pdev->device == 0x1182) || (pmr & SIS_PMR_COMBINED))
221 iowrite32(val, ap->ioaddr.scr_addr + (sc_reg * 4)+0x10);
222 return 0;
226 static int sis_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
228 static int printed_version;
229 struct ata_port_info pi = sis_port_info;
230 const struct ata_port_info *ppi[] = { &pi, &pi };
231 struct ata_host *host;
232 u32 genctl, val;
233 u8 pmr;
234 u8 port2_start = 0x20;
235 int rc;
237 if (!printed_version++)
238 dev_printk(KERN_INFO, &pdev->dev, "version " DRV_VERSION "\n");
240 rc = pcim_enable_device(pdev);
241 if (rc)
242 return rc;
244 /* check and see if the SCRs are in IO space or PCI cfg space */
245 pci_read_config_dword(pdev, SIS_GENCTL, &genctl);
246 if ((genctl & GENCTL_IOMAPPED_SCR) == 0)
247 pi.flags |= SIS_FLAG_CFGSCR;
249 /* if hardware thinks SCRs are in IO space, but there are
250 * no IO resources assigned, change to PCI cfg space.
252 if ((!(pi.flags & SIS_FLAG_CFGSCR)) &&
253 ((pci_resource_start(pdev, SIS_SCR_PCI_BAR) == 0) ||
254 (pci_resource_len(pdev, SIS_SCR_PCI_BAR) < 128))) {
255 genctl &= ~GENCTL_IOMAPPED_SCR;
256 pci_write_config_dword(pdev, SIS_GENCTL, genctl);
257 pi.flags |= SIS_FLAG_CFGSCR;
260 pci_read_config_byte(pdev, SIS_PMR, &pmr);
261 switch (ent->device) {
262 case 0x0180:
263 case 0x0181:
265 /* The PATA-handling is provided by pata_sis */
266 switch (pmr & 0x30) {
267 case 0x10:
268 ppi[1] = &sis_info133_for_sata;
269 break;
271 case 0x30:
272 ppi[0] = &sis_info133_for_sata;
273 break;
275 if ((pmr & SIS_PMR_COMBINED) == 0) {
276 dev_printk(KERN_INFO, &pdev->dev,
277 "Detected SiS 180/181/964 chipset in SATA mode\n");
278 port2_start = 64;
279 } else {
280 dev_printk(KERN_INFO, &pdev->dev,
281 "Detected SiS 180/181 chipset in combined mode\n");
282 port2_start = 0;
283 pi.flags |= ATA_FLAG_SLAVE_POSS;
285 break;
287 case 0x0182:
288 case 0x0183:
289 pci_read_config_dword(pdev, 0x6C, &val);
290 if (val & (1L << 31)) {
291 dev_printk(KERN_INFO, &pdev->dev,
292 "Detected SiS 182/965 chipset\n");
293 pi.flags |= ATA_FLAG_SLAVE_POSS;
294 } else {
295 dev_printk(KERN_INFO, &pdev->dev,
296 "Detected SiS 182/965L chipset\n");
298 break;
300 case 0x1182:
301 dev_printk(KERN_INFO, &pdev->dev,
302 "Detected SiS 1182/966/680 SATA controller\n");
303 pi.flags |= ATA_FLAG_SLAVE_POSS;
304 break;
306 case 0x1183:
307 dev_printk(KERN_INFO, &pdev->dev,
308 "Detected SiS 1183/966/966L/968/680 controller in PATA mode\n");
309 ppi[0] = &sis_info133_for_sata;
310 ppi[1] = &sis_info133_for_sata;
311 break;
314 rc = ata_pci_sff_prepare_host(pdev, ppi, &host);
315 if (rc)
316 return rc;
318 if (!(pi.flags & SIS_FLAG_CFGSCR)) {
319 void __iomem *mmio;
321 rc = pcim_iomap_regions(pdev, 1 << SIS_SCR_PCI_BAR, DRV_NAME);
322 if (rc)
323 return rc;
324 mmio = host->iomap[SIS_SCR_PCI_BAR];
326 host->ports[0]->ioaddr.scr_addr = mmio;
327 host->ports[1]->ioaddr.scr_addr = mmio + port2_start;
330 pci_set_master(pdev);
331 pci_intx(pdev, 1);
332 return ata_host_activate(host, pdev->irq, ata_sff_interrupt,
333 IRQF_SHARED, &sis_sht);
336 static int __init sis_init(void)
338 return pci_register_driver(&sis_pci_driver);
341 static void __exit sis_exit(void)
343 pci_unregister_driver(&sis_pci_driver);
346 module_init(sis_init);
347 module_exit(sis_exit);