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ia64/kvm: compilation fix. export account_system_vtime.
[pv_ops_mirror.git] / drivers / dma / iop-adma.c
blob762b729672e02bbe530c580f13cbe6395b53ccc3
1 /*
2 * offload engine driver for the Intel Xscale series of i/o processors
3 * Copyright © 2006, Intel Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
17 *
18 */
19
20 /*
21 * This driver supports the asynchrounous DMA copy and RAID engines available
22 * on the Intel Xscale(R) family of I/O Processors (IOP 32x, 33x, 134x)
23 */
24
25 #include <linux/init.h>
26 #include <linux/module.h>
27 #include <linux/async_tx.h>
28 #include <linux/delay.h>
29 #include <linux/dma-mapping.h>
30 #include <linux/spinlock.h>
31 #include <linux/interrupt.h>
32 #include <linux/platform_device.h>
33 #include <linux/memory.h>
34 #include <linux/ioport.h>
35
36 #include <asm/arch/adma.h>
37
38 #define to_iop_adma_chan(chan) container_of(chan, struct iop_adma_chan, common)
39 #define to_iop_adma_device(dev) \
40 container_of(dev, struct iop_adma_device, common)
41 #define tx_to_iop_adma_slot(tx) \
42 container_of(tx, struct iop_adma_desc_slot, async_tx)
43
44 /**
45 * iop_adma_free_slots - flags descriptor slots for reuse
46 * @slot: Slot to free
47 * Caller must hold &iop_chan->lock while calling this function
48 */
49 static void iop_adma_free_slots(struct iop_adma_desc_slot *slot)
50 {
51 int stride = slot->slots_per_op;
52
53 while (stride--) {
54 slot->slots_per_op = 0;
55 slot = list_entry(slot->slot_node.next,
56 struct iop_adma_desc_slot,
57 slot_node);
58 }
59 }
60
61 static dma_cookie_t
62 iop_adma_run_tx_complete_actions(struct iop_adma_desc_slot *desc,
63 struct iop_adma_chan *iop_chan, dma_cookie_t cookie)
64 {
65 BUG_ON(desc->async_tx.cookie < 0);
66 if (desc->async_tx.cookie > 0) {
67 cookie = desc->async_tx.cookie;
68 desc->async_tx.cookie = 0;
69
70 /* call the callback (must not sleep or submit new
71 * operations to this channel)
72 */
73 if (desc->async_tx.callback)
74 desc->async_tx.callback(
75 desc->async_tx.callback_param);
76
77 /* unmap dma addresses
78 * (unmap_single vs unmap_page?)
79 */
80 if (desc->group_head && desc->unmap_len) {
81 struct iop_adma_desc_slot *unmap = desc->group_head;
82 struct device *dev =
83 &iop_chan->device->pdev->dev;
84 u32 len = unmap->unmap_len;
85 u32 src_cnt = unmap->unmap_src_cnt;
86 dma_addr_t addr = iop_desc_get_dest_addr(unmap,
87 iop_chan);
88
89 dma_unmap_page(dev, addr, len, DMA_FROM_DEVICE);
90 while (src_cnt--) {
91 addr = iop_desc_get_src_addr(unmap,
92 iop_chan,
93 src_cnt);
94 dma_unmap_page(dev, addr, len,
95 DMA_TO_DEVICE);
96 }
97 desc->group_head = NULL;
98 }
99 }
100
101 /* run dependent operations */
102 async_tx_run_dependencies(&desc->async_tx);
103
104 return cookie;
105 }
106
107 static int
108 iop_adma_clean_slot(struct iop_adma_desc_slot *desc,
109 struct iop_adma_chan *iop_chan)
110 {
111 /* the client is allowed to attach dependent operations
112 * until 'ack' is set
113 */
114 if (!async_tx_test_ack(&desc->async_tx))
115 return 0;
116
117 /* leave the last descriptor in the chain
118 * so we can append to it
119 */
120 if (desc->chain_node.next == &iop_chan->chain)
121 return 1;
122
123 dev_dbg(iop_chan->device->common.dev,
124 "\tfree slot: %d slots_per_op: %d\n",
125 desc->idx, desc->slots_per_op);
126
127 list_del(&desc->chain_node);
128 iop_adma_free_slots(desc);
129
130 return 0;
131 }
132
133 static void __iop_adma_slot_cleanup(struct iop_adma_chan *iop_chan)
134 {
135 struct iop_adma_desc_slot *iter, *_iter, *grp_start = NULL;
136 dma_cookie_t cookie = 0;
137 u32 current_desc = iop_chan_get_current_descriptor(iop_chan);
138 int busy = iop_chan_is_busy(iop_chan);
139 int seen_current = 0, slot_cnt = 0, slots_per_op = 0;
140
141 dev_dbg(iop_chan->device->common.dev, "%s\n", __func__);
142 /* free completed slots from the chain starting with
143 * the oldest descriptor
144 */
145 list_for_each_entry_safe(iter, _iter, &iop_chan->chain,
146 chain_node) {
147 pr_debug("\tcookie: %d slot: %d busy: %d "
148 "this_desc: %#x next_desc: %#x ack: %d\n",
149 iter->async_tx.cookie, iter->idx, busy,
150 iter->async_tx.phys, iop_desc_get_next_desc(iter),
151 async_tx_test_ack(&iter->async_tx));
152 prefetch(_iter);
153 prefetch(&_iter->async_tx);
154
155 /* do not advance past the current descriptor loaded into the
156 * hardware channel, subsequent descriptors are either in
157 * process or have not been submitted
158 */
159 if (seen_current)
160 break;
161
162 /* stop the search if we reach the current descriptor and the
163 * channel is busy, or if it appears that the current descriptor
164 * needs to be re-read (i.e. has been appended to)
165 */
166 if (iter->async_tx.phys == current_desc) {
167 BUG_ON(seen_current++);
168 if (busy || iop_desc_get_next_desc(iter))
169 break;
170 }
171
172 /* detect the start of a group transaction */
173 if (!slot_cnt && !slots_per_op) {
174 slot_cnt = iter->slot_cnt;
175 slots_per_op = iter->slots_per_op;
176 if (slot_cnt <= slots_per_op) {
177 slot_cnt = 0;
178 slots_per_op = 0;
179 }
180 }
181
182 if (slot_cnt) {
183 pr_debug("\tgroup++\n");
184 if (!grp_start)
185 grp_start = iter;
186 slot_cnt -= slots_per_op;
187 }
188
189 /* all the members of a group are complete */
190 if (slots_per_op != 0 && slot_cnt == 0) {
191 struct iop_adma_desc_slot *grp_iter, *_grp_iter;
192 int end_of_chain = 0;
193 pr_debug("\tgroup end\n");
194
195 /* collect the total results */
196 if (grp_start->xor_check_result) {
197 u32 zero_sum_result = 0;
198 slot_cnt = grp_start->slot_cnt;
199 grp_iter = grp_start;
200
201 list_for_each_entry_from(grp_iter,
202 &iop_chan->chain, chain_node) {
203 zero_sum_result |=
204 iop_desc_get_zero_result(grp_iter);
205 pr_debug("\titer%d result: %d\n",
206 grp_iter->idx, zero_sum_result);
207 slot_cnt -= slots_per_op;
208 if (slot_cnt == 0)
209 break;
210 }
211 pr_debug("\tgrp_start->xor_check_result: %p\n",
212 grp_start->xor_check_result);
213 *grp_start->xor_check_result = zero_sum_result;
214 }
215
216 /* clean up the group */
217 slot_cnt = grp_start->slot_cnt;
218 grp_iter = grp_start;
219 list_for_each_entry_safe_from(grp_iter, _grp_iter,
220 &iop_chan->chain, chain_node) {
221 cookie = iop_adma_run_tx_complete_actions(
222 grp_iter, iop_chan, cookie);
223
224 slot_cnt -= slots_per_op;
225 end_of_chain = iop_adma_clean_slot(grp_iter,
226 iop_chan);
227
228 if (slot_cnt == 0 || end_of_chain)
229 break;
230 }
231
232 /* the group should be complete at this point */
233 BUG_ON(slot_cnt);
234
235 slots_per_op = 0;
236 grp_start = NULL;
237 if (end_of_chain)
238 break;
239 else
240 continue;
241 } else if (slots_per_op) /* wait for group completion */
242 continue;
243
244 /* write back zero sum results (single descriptor case) */
245 if (iter->xor_check_result && iter->async_tx.cookie)
246 *iter->xor_check_result =
247 iop_desc_get_zero_result(iter);
248
249 cookie = iop_adma_run_tx_complete_actions(
250 iter, iop_chan, cookie);
251
252 if (iop_adma_clean_slot(iter, iop_chan))
253 break;
254 }
255
256 BUG_ON(!seen_current);
257
258 if (cookie > 0) {
259 iop_chan->completed_cookie = cookie;
260 pr_debug("\tcompleted cookie %d\n", cookie);
261 }
262 }
263
264 static void
265 iop_adma_slot_cleanup(struct iop_adma_chan *iop_chan)
266 {
267 spin_lock_bh(&iop_chan->lock);
268 __iop_adma_slot_cleanup(iop_chan);
269 spin_unlock_bh(&iop_chan->lock);
270 }
271
272 static void iop_adma_tasklet(unsigned long data)
273 {
274 struct iop_adma_chan *iop_chan = (struct iop_adma_chan *) data;
275
276 spin_lock(&iop_chan->lock);
277 __iop_adma_slot_cleanup(iop_chan);
278 spin_unlock(&iop_chan->lock);
279 }
280
281 static struct iop_adma_desc_slot *
282 iop_adma_alloc_slots(struct iop_adma_chan *iop_chan, int num_slots,
283 int slots_per_op)
284 {
285 struct iop_adma_desc_slot *iter, *_iter, *alloc_start = NULL;
286 LIST_HEAD(chain);
287 int slots_found, retry = 0;
288
289 /* start search from the last allocated descrtiptor
290 * if a contiguous allocation can not be found start searching
291 * from the beginning of the list
292 */
293 retry:
294 slots_found = 0;
295 if (retry == 0)
296 iter = iop_chan->last_used;
297 else
298 iter = list_entry(&iop_chan->all_slots,
299 struct iop_adma_desc_slot,
300 slot_node);
301
302 list_for_each_entry_safe_continue(
303 iter, _iter, &iop_chan->all_slots, slot_node) {
304 prefetch(_iter);
305 prefetch(&_iter->async_tx);
306 if (iter->slots_per_op) {
307 /* give up after finding the first busy slot
308 * on the second pass through the list
309 */
310 if (retry)
311 break;
312
313 slots_found = 0;
314 continue;
315 }
316
317 /* start the allocation if the slot is correctly aligned */
318 if (!slots_found++) {
319 if (iop_desc_is_aligned(iter, slots_per_op))
320 alloc_start = iter;
321 else {
322 slots_found = 0;
323 continue;
324 }
325 }
326
327 if (slots_found == num_slots) {
328 struct iop_adma_desc_slot *alloc_tail = NULL;
329 struct iop_adma_desc_slot *last_used = NULL;
330 iter = alloc_start;
331 while (num_slots) {
332 int i;
333 dev_dbg(iop_chan->device->common.dev,
334 "allocated slot: %d "
335 "(desc %p phys: %#x) slots_per_op %d\n",
336 iter->idx, iter->hw_desc,
337 iter->async_tx.phys, slots_per_op);
338
339 /* pre-ack all but the last descriptor */
340 if (num_slots != slots_per_op)
341 async_tx_ack(&iter->async_tx);
342
343 list_add_tail(&iter->chain_node, &chain);
344 alloc_tail = iter;
345 iter->async_tx.cookie = 0;
346 iter->slot_cnt = num_slots;
347 iter->xor_check_result = NULL;
348 for (i = 0; i < slots_per_op; i++) {
349 iter->slots_per_op = slots_per_op - i;
350 last_used = iter;
351 iter = list_entry(iter->slot_node.next,
352 struct iop_adma_desc_slot,
353 slot_node);
354 }
355 num_slots -= slots_per_op;
356 }
357 alloc_tail->group_head = alloc_start;
358 alloc_tail->async_tx.cookie = -EBUSY;
359 list_splice(&chain, &alloc_tail->async_tx.tx_list);
360 iop_chan->last_used = last_used;
361 iop_desc_clear_next_desc(alloc_start);
362 iop_desc_clear_next_desc(alloc_tail);
363 return alloc_tail;
364 }
365 }
366 if (!retry++)
367 goto retry;
368
369 /* try to free some slots if the allocation fails */
370 tasklet_schedule(&iop_chan->irq_tasklet);
371
372 return NULL;
373 }
374
375 static dma_cookie_t
376 iop_desc_assign_cookie(struct iop_adma_chan *iop_chan,
377 struct iop_adma_desc_slot *desc)
378 {
379 dma_cookie_t cookie = iop_chan->common.cookie;
380 cookie++;
381 if (cookie < 0)
382 cookie = 1;
383 iop_chan->common.cookie = desc->async_tx.cookie = cookie;
384 return cookie;
385 }
386
387 static void iop_adma_check_threshold(struct iop_adma_chan *iop_chan)
388 {
389 dev_dbg(iop_chan->device->common.dev, "pending: %d\n",
390 iop_chan->pending);
391
392 if (iop_chan->pending >= IOP_ADMA_THRESHOLD) {
393 iop_chan->pending = 0;
394 iop_chan_append(iop_chan);
395 }
396 }
397
398 static dma_cookie_t
399 iop_adma_tx_submit(struct dma_async_tx_descriptor *tx)
400 {
401 struct iop_adma_desc_slot *sw_desc = tx_to_iop_adma_slot(tx);
402 struct iop_adma_chan *iop_chan = to_iop_adma_chan(tx->chan);
403 struct iop_adma_desc_slot *grp_start, *old_chain_tail;
404 int slot_cnt;
405 int slots_per_op;
406 dma_cookie_t cookie;
407
408 grp_start = sw_desc->group_head;
409 slot_cnt = grp_start->slot_cnt;
410 slots_per_op = grp_start->slots_per_op;
411
412 spin_lock_bh(&iop_chan->lock);
413 cookie = iop_desc_assign_cookie(iop_chan, sw_desc);
414
415 old_chain_tail = list_entry(iop_chan->chain.prev,
416 struct iop_adma_desc_slot, chain_node);
417 list_splice_init(&sw_desc->async_tx.tx_list,
418 &old_chain_tail->chain_node);
419
420 /* fix up the hardware chain */
421 iop_desc_set_next_desc(old_chain_tail, grp_start->async_tx.phys);
422
423 /* 1/ don't add pre-chained descriptors
424 * 2/ dummy read to flush next_desc write
425 */
426 BUG_ON(iop_desc_get_next_desc(sw_desc));
427
428 /* increment the pending count by the number of slots
429 * memcpy operations have a 1:1 (slot:operation) relation
430 * other operations are heavier and will pop the threshold
431 * more often.
432 */
433 iop_chan->pending += slot_cnt;
434 iop_adma_check_threshold(iop_chan);
435 spin_unlock_bh(&iop_chan->lock);
436
437 dev_dbg(iop_chan->device->common.dev, "%s cookie: %d slot: %d\n",
438 __func__, sw_desc->async_tx.cookie, sw_desc->idx);
439
440 return cookie;
441 }
442
443 static void iop_chan_start_null_memcpy(struct iop_adma_chan *iop_chan);
444 static void iop_chan_start_null_xor(struct iop_adma_chan *iop_chan);
445
446 /* returns the number of allocated descriptors */
447 static int iop_adma_alloc_chan_resources(struct dma_chan *chan)
448 {
449 char *hw_desc;
450 int idx;
451 struct iop_adma_chan *iop_chan = to_iop_adma_chan(chan);
452 struct iop_adma_desc_slot *slot = NULL;
453 int init = iop_chan->slots_allocated ? 0 : 1;
454 struct iop_adma_platform_data *plat_data =
455 iop_chan->device->pdev->dev.platform_data;
456 int num_descs_in_pool = plat_data->pool_size/IOP_ADMA_SLOT_SIZE;
457
458 /* Allocate descriptor slots */
459 do {
460 idx = iop_chan->slots_allocated;
461 if (idx == num_descs_in_pool)
462 break;
463
464 slot = kzalloc(sizeof(*slot), GFP_KERNEL);
465 if (!slot) {
466 printk(KERN_INFO "IOP ADMA Channel only initialized"
467 " %d descriptor slots", idx);
468 break;
469 }
470 hw_desc = (char *) iop_chan->device->dma_desc_pool_virt;
471 slot->hw_desc = (void *) &hw_desc[idx * IOP_ADMA_SLOT_SIZE];
472
473 dma_async_tx_descriptor_init(&slot->async_tx, chan);
474 slot->async_tx.tx_submit = iop_adma_tx_submit;
475 INIT_LIST_HEAD(&slot->chain_node);
476 INIT_LIST_HEAD(&slot->slot_node);
477 INIT_LIST_HEAD(&slot->async_tx.tx_list);
478 hw_desc = (char *) iop_chan->device->dma_desc_pool;
479 slot->async_tx.phys =
480 (dma_addr_t) &hw_desc[idx * IOP_ADMA_SLOT_SIZE];
481 slot->idx = idx;
482
483 spin_lock_bh(&iop_chan->lock);
484 iop_chan->slots_allocated++;
485 list_add_tail(&slot->slot_node, &iop_chan->all_slots);
486 spin_unlock_bh(&iop_chan->lock);
487 } while (iop_chan->slots_allocated < num_descs_in_pool);
488
489 if (idx && !iop_chan->last_used)
490 iop_chan->last_used = list_entry(iop_chan->all_slots.next,
491 struct iop_adma_desc_slot,
492 slot_node);
493
494 dev_dbg(iop_chan->device->common.dev,
495 "allocated %d descriptor slots last_used: %p\n",
496 iop_chan->slots_allocated, iop_chan->last_used);
497
498 /* initialize the channel and the chain with a null operation */
499 if (init) {
500 if (dma_has_cap(DMA_MEMCPY,
501 iop_chan->device->common.cap_mask))
502 iop_chan_start_null_memcpy(iop_chan);
503 else if (dma_has_cap(DMA_XOR,
504 iop_chan->device->common.cap_mask))
505 iop_chan_start_null_xor(iop_chan);
506 else
507 BUG();
508 }
509
510 return (idx > 0) ? idx : -ENOMEM;
511 }
512
513 static struct dma_async_tx_descriptor *
514 iop_adma_prep_dma_interrupt(struct dma_chan *chan, unsigned long flags)
515 {
516 struct iop_adma_chan *iop_chan = to_iop_adma_chan(chan);
517 struct iop_adma_desc_slot *sw_desc, *grp_start;
518 int slot_cnt, slots_per_op;
519
520 dev_dbg(iop_chan->device->common.dev, "%s\n", __func__);
521
522 spin_lock_bh(&iop_chan->lock);
523 slot_cnt = iop_chan_interrupt_slot_count(&slots_per_op, iop_chan);
524 sw_desc = iop_adma_alloc_slots(iop_chan, slot_cnt, slots_per_op);
525 if (sw_desc) {
526 grp_start = sw_desc->group_head;
527 iop_desc_init_interrupt(grp_start, iop_chan);
528 grp_start->unmap_len = 0;
529 sw_desc->async_tx.flags = flags;
530 }
531 spin_unlock_bh(&iop_chan->lock);
532
533 return sw_desc ? &sw_desc->async_tx : NULL;
534 }
535
536 static struct dma_async_tx_descriptor *
537 iop_adma_prep_dma_memcpy(struct dma_chan *chan, dma_addr_t dma_dest,
538 dma_addr_t dma_src, size_t len, unsigned long flags)
539 {
540 struct iop_adma_chan *iop_chan = to_iop_adma_chan(chan);
541 struct iop_adma_desc_slot *sw_desc, *grp_start;
542 int slot_cnt, slots_per_op;
543
544 if (unlikely(!len))
545 return NULL;
546 BUG_ON(unlikely(len > IOP_ADMA_MAX_BYTE_COUNT));
547
548 dev_dbg(iop_chan->device->common.dev, "%s len: %u\n",
549 __func__, len);
550
551 spin_lock_bh(&iop_chan->lock);
552 slot_cnt = iop_chan_memcpy_slot_count(len, &slots_per_op);
553 sw_desc = iop_adma_alloc_slots(iop_chan, slot_cnt, slots_per_op);
554 if (sw_desc) {
555 grp_start = sw_desc->group_head;
556 iop_desc_init_memcpy(grp_start, flags);
557 iop_desc_set_byte_count(grp_start, iop_chan, len);
558 iop_desc_set_dest_addr(grp_start, iop_chan, dma_dest);
559 iop_desc_set_memcpy_src_addr(grp_start, dma_src);
560 sw_desc->unmap_src_cnt = 1;
561 sw_desc->unmap_len = len;
562 sw_desc->async_tx.flags = flags;
563 }
564 spin_unlock_bh(&iop_chan->lock);
565
566 return sw_desc ? &sw_desc->async_tx : NULL;
567 }
568
569 static struct dma_async_tx_descriptor *
570 iop_adma_prep_dma_memset(struct dma_chan *chan, dma_addr_t dma_dest,
571 int value, size_t len, unsigned long flags)
572 {
573 struct iop_adma_chan *iop_chan = to_iop_adma_chan(chan);
574 struct iop_adma_desc_slot *sw_desc, *grp_start;
575 int slot_cnt, slots_per_op;
576
577 if (unlikely(!len))
578 return NULL;
579 BUG_ON(unlikely(len > IOP_ADMA_MAX_BYTE_COUNT));
580
581 dev_dbg(iop_chan->device->common.dev, "%s len: %u\n",
582 __func__, len);
583
584 spin_lock_bh(&iop_chan->lock);
585 slot_cnt = iop_chan_memset_slot_count(len, &slots_per_op);
586 sw_desc = iop_adma_alloc_slots(iop_chan, slot_cnt, slots_per_op);
587 if (sw_desc) {
588 grp_start = sw_desc->group_head;
589 iop_desc_init_memset(grp_start, flags);
590 iop_desc_set_byte_count(grp_start, iop_chan, len);
591 iop_desc_set_block_fill_val(grp_start, value);
592 iop_desc_set_dest_addr(grp_start, iop_chan, dma_dest);
593 sw_desc->unmap_src_cnt = 1;
594 sw_desc->unmap_len = len;
595 sw_desc->async_tx.flags = flags;
596 }
597 spin_unlock_bh(&iop_chan->lock);
598
599 return sw_desc ? &sw_desc->async_tx : NULL;
600 }
601
602 static struct dma_async_tx_descriptor *
603 iop_adma_prep_dma_xor(struct dma_chan *chan, dma_addr_t dma_dest,
604 dma_addr_t *dma_src, unsigned int src_cnt, size_t len,
605 unsigned long flags)
606 {
607 struct iop_adma_chan *iop_chan = to_iop_adma_chan(chan);
608 struct iop_adma_desc_slot *sw_desc, *grp_start;
609 int slot_cnt, slots_per_op;
610
611 if (unlikely(!len))
612 return NULL;
613 BUG_ON(unlikely(len > IOP_ADMA_XOR_MAX_BYTE_COUNT));
614
615 dev_dbg(iop_chan->device->common.dev,
616 "%s src_cnt: %d len: %u flags: %lx\n",
617 __func__, src_cnt, len, flags);
618
619 spin_lock_bh(&iop_chan->lock);
620 slot_cnt = iop_chan_xor_slot_count(len, src_cnt, &slots_per_op);
621 sw_desc = iop_adma_alloc_slots(iop_chan, slot_cnt, slots_per_op);
622 if (sw_desc) {
623 grp_start = sw_desc->group_head;
624 iop_desc_init_xor(grp_start, src_cnt, flags);
625 iop_desc_set_byte_count(grp_start, iop_chan, len);
626 iop_desc_set_dest_addr(grp_start, iop_chan, dma_dest);
627 sw_desc->unmap_src_cnt = src_cnt;
628 sw_desc->unmap_len = len;
629 sw_desc->async_tx.flags = flags;
630 while (src_cnt--)
631 iop_desc_set_xor_src_addr(grp_start, src_cnt,
632 dma_src[src_cnt]);
633 }
634 spin_unlock_bh(&iop_chan->lock);
635
636 return sw_desc ? &sw_desc->async_tx : NULL;
637 }
638
639 static struct dma_async_tx_descriptor *
640 iop_adma_prep_dma_zero_sum(struct dma_chan *chan, dma_addr_t *dma_src,
641 unsigned int src_cnt, size_t len, u32 *result,
642 unsigned long flags)
643 {
644 struct iop_adma_chan *iop_chan = to_iop_adma_chan(chan);
645 struct iop_adma_desc_slot *sw_desc, *grp_start;
646 int slot_cnt, slots_per_op;
647
648 if (unlikely(!len))
649 return NULL;
650
651 dev_dbg(iop_chan->device->common.dev, "%s src_cnt: %d len: %u\n",
652 __func__, src_cnt, len);
653
654 spin_lock_bh(&iop_chan->lock);
655 slot_cnt = iop_chan_zero_sum_slot_count(len, src_cnt, &slots_per_op);
656 sw_desc = iop_adma_alloc_slots(iop_chan, slot_cnt, slots_per_op);
657 if (sw_desc) {
658 grp_start = sw_desc->group_head;
659 iop_desc_init_zero_sum(grp_start, src_cnt, flags);
660 iop_desc_set_zero_sum_byte_count(grp_start, len);
661 grp_start->xor_check_result = result;
662 pr_debug("\t%s: grp_start->xor_check_result: %p\n",
663 __func__, grp_start->xor_check_result);
664 sw_desc->unmap_src_cnt = src_cnt;
665 sw_desc->unmap_len = len;
666 sw_desc->async_tx.flags = flags;
667 while (src_cnt--)
668 iop_desc_set_zero_sum_src_addr(grp_start, src_cnt,
669 dma_src[src_cnt]);
670 }
671 spin_unlock_bh(&iop_chan->lock);
672
673 return sw_desc ? &sw_desc->async_tx : NULL;
674 }
675
676 static void iop_adma_free_chan_resources(struct dma_chan *chan)
677 {
678 struct iop_adma_chan *iop_chan = to_iop_adma_chan(chan);
679 struct iop_adma_desc_slot *iter, *_iter;
680 int in_use_descs = 0;
681
682 iop_adma_slot_cleanup(iop_chan);
683
684 spin_lock_bh(&iop_chan->lock);
685 list_for_each_entry_safe(iter, _iter, &iop_chan->chain,
686 chain_node) {
687 in_use_descs++;
688 list_del(&iter->chain_node);
689 }
690 list_for_each_entry_safe_reverse(
691 iter, _iter, &iop_chan->all_slots, slot_node) {
692 list_del(&iter->slot_node);
693 kfree(iter);
694 iop_chan->slots_allocated--;
695 }
696 iop_chan->last_used = NULL;
697
698 dev_dbg(iop_chan->device->common.dev, "%s slots_allocated %d\n",
699 __func__, iop_chan->slots_allocated);
700 spin_unlock_bh(&iop_chan->lock);
701
702 /* one is ok since we left it on there on purpose */
703 if (in_use_descs > 1)
704 printk(KERN_ERR "IOP: Freeing %d in use descriptors!\n",
705 in_use_descs - 1);
706 }
707
708 /**
709 * iop_adma_is_complete - poll the status of an ADMA transaction
710 * @chan: ADMA channel handle
711 * @cookie: ADMA transaction identifier
712 */
713 static enum dma_status iop_adma_is_complete(struct dma_chan *chan,
714 dma_cookie_t cookie,
715 dma_cookie_t *done,
716 dma_cookie_t *used)
717 {
718 struct iop_adma_chan *iop_chan = to_iop_adma_chan(chan);
719 dma_cookie_t last_used;
720 dma_cookie_t last_complete;
721 enum dma_status ret;
722
723 last_used = chan->cookie;
724 last_complete = iop_chan->completed_cookie;
725
726 if (done)
727 *done = last_complete;
728 if (used)
729 *used = last_used;
730
731 ret = dma_async_is_complete(cookie, last_complete, last_used);
732 if (ret == DMA_SUCCESS)
733 return ret;
734
735 iop_adma_slot_cleanup(iop_chan);
736
737 last_used = chan->cookie;
738 last_complete = iop_chan->completed_cookie;
739
740 if (done)
741 *done = last_complete;
742 if (used)
743 *used = last_used;
744
745 return dma_async_is_complete(cookie, last_complete, last_used);
746 }
747
748 static irqreturn_t iop_adma_eot_handler(int irq, void *data)
749 {
750 struct iop_adma_chan *chan = data;
751
752 dev_dbg(chan->device->common.dev, "%s\n", __func__);
753
754 tasklet_schedule(&chan->irq_tasklet);
755
756 iop_adma_device_clear_eot_status(chan);
757
758 return IRQ_HANDLED;
759 }
760
761 static irqreturn_t iop_adma_eoc_handler(int irq, void *data)
762 {
763 struct iop_adma_chan *chan = data;
764
765 dev_dbg(chan->device->common.dev, "%s\n", __func__);
766
767 tasklet_schedule(&chan->irq_tasklet);
768
769 iop_adma_device_clear_eoc_status(chan);
770
771 return IRQ_HANDLED;
772 }
773
774 static irqreturn_t iop_adma_err_handler(int irq, void *data)
775 {
776 struct iop_adma_chan *chan = data;
777 unsigned long status = iop_chan_get_status(chan);
778
779 dev_printk(KERN_ERR, chan->device->common.dev,
780 "error ( %s%s%s%s%s%s%s)\n",
781 iop_is_err_int_parity(status, chan) ? "int_parity " : "",
782 iop_is_err_mcu_abort(status, chan) ? "mcu_abort " : "",
783 iop_is_err_int_tabort(status, chan) ? "int_tabort " : "",
784 iop_is_err_int_mabort(status, chan) ? "int_mabort " : "",
785 iop_is_err_pci_tabort(status, chan) ? "pci_tabort " : "",
786 iop_is_err_pci_mabort(status, chan) ? "pci_mabort " : "",
787 iop_is_err_split_tx(status, chan) ? "split_tx " : "");
788
789 iop_adma_device_clear_err_status(chan);
790
791 BUG();
792
793 return IRQ_HANDLED;
794 }
795
796 static void iop_adma_issue_pending(struct dma_chan *chan)
797 {
798 struct iop_adma_chan *iop_chan = to_iop_adma_chan(chan);
799
800 if (iop_chan->pending) {
801 iop_chan->pending = 0;
802 iop_chan_append(iop_chan);
803 }
804 }
805
806 /*
807 * Perform a transaction to verify the HW works.
808 */
809 #define IOP_ADMA_TEST_SIZE 2000
810
811 static int __devinit iop_adma_memcpy_self_test(struct iop_adma_device *device)
812 {
813 int i;
814 void *src, *dest;
815 dma_addr_t src_dma, dest_dma;
816 struct dma_chan *dma_chan;
817 dma_cookie_t cookie;
818 struct dma_async_tx_descriptor *tx;
819 int err = 0;
820 struct iop_adma_chan *iop_chan;
821
822 dev_dbg(device->common.dev, "%s\n", __func__);
823
824 src = kzalloc(sizeof(u8) * IOP_ADMA_TEST_SIZE, GFP_KERNEL);
825 if (!src)
826 return -ENOMEM;
827 dest = kzalloc(sizeof(u8) * IOP_ADMA_TEST_SIZE, GFP_KERNEL);
828 if (!dest) {
829 kfree(src);
830 return -ENOMEM;
831 }
832
833 /* Fill in src buffer */
834 for (i = 0; i < IOP_ADMA_TEST_SIZE; i++)
835 ((u8 *) src)[i] = (u8)i;
836
837 memset(dest, 0, IOP_ADMA_TEST_SIZE);
838
839 /* Start copy, using first DMA channel */
840 dma_chan = container_of(device->common.channels.next,
841 struct dma_chan,
842 device_node);
843 if (iop_adma_alloc_chan_resources(dma_chan) < 1) {
844 err = -ENODEV;
845 goto out;
846 }
847
848 dest_dma = dma_map_single(dma_chan->device->dev, dest,
849 IOP_ADMA_TEST_SIZE, DMA_FROM_DEVICE);
850 src_dma = dma_map_single(dma_chan->device->dev, src,
851 IOP_ADMA_TEST_SIZE, DMA_TO_DEVICE);
852 tx = iop_adma_prep_dma_memcpy(dma_chan, dest_dma, src_dma,
853 IOP_ADMA_TEST_SIZE,
854 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
855
856 cookie = iop_adma_tx_submit(tx);
857 iop_adma_issue_pending(dma_chan);
858 msleep(1);
859
860 if (iop_adma_is_complete(dma_chan, cookie, NULL, NULL) !=
861 DMA_SUCCESS) {
862 dev_printk(KERN_ERR, dma_chan->device->dev,
863 "Self-test copy timed out, disabling\n");
864 err = -ENODEV;
865 goto free_resources;
866 }
867
868 iop_chan = to_iop_adma_chan(dma_chan);
869 dma_sync_single_for_cpu(&iop_chan->device->pdev->dev, dest_dma,
870 IOP_ADMA_TEST_SIZE, DMA_FROM_DEVICE);
871 if (memcmp(src, dest, IOP_ADMA_TEST_SIZE)) {
872 dev_printk(KERN_ERR, dma_chan->device->dev,
873 "Self-test copy failed compare, disabling\n");
874 err = -ENODEV;
875 goto free_resources;
876 }
877
878 free_resources:
879 iop_adma_free_chan_resources(dma_chan);
880 out:
881 kfree(src);
882 kfree(dest);
883 return err;
884 }
885
886 #define IOP_ADMA_NUM_SRC_TEST 4 /* must be <= 15 */
887 static int __devinit
888 iop_adma_xor_zero_sum_self_test(struct iop_adma_device *device)
889 {
890 int i, src_idx;
891 struct page *dest;
892 struct page *xor_srcs[IOP_ADMA_NUM_SRC_TEST];
893 struct page *zero_sum_srcs[IOP_ADMA_NUM_SRC_TEST + 1];
894 dma_addr_t dma_srcs[IOP_ADMA_NUM_SRC_TEST + 1];
895 dma_addr_t dma_addr, dest_dma;
896 struct dma_async_tx_descriptor *tx;
897 struct dma_chan *dma_chan;
898 dma_cookie_t cookie;
899 u8 cmp_byte = 0;
900 u32 cmp_word;
901 u32 zero_sum_result;
902 int err = 0;
903 struct iop_adma_chan *iop_chan;
904
905 dev_dbg(device->common.dev, "%s\n", __func__);
906
907 for (src_idx = 0; src_idx < IOP_ADMA_NUM_SRC_TEST; src_idx++) {
908 xor_srcs[src_idx] = alloc_page(GFP_KERNEL);
909 if (!xor_srcs[src_idx])
910 while (src_idx--) {
911 __free_page(xor_srcs[src_idx]);
912 return -ENOMEM;
913 }
914 }
915
916 dest = alloc_page(GFP_KERNEL);
917 if (!dest)
918 while (src_idx--) {
919 __free_page(xor_srcs[src_idx]);
920 return -ENOMEM;
921 }
922
923 /* Fill in src buffers */
924 for (src_idx = 0; src_idx < IOP_ADMA_NUM_SRC_TEST; src_idx++) {
925 u8 *ptr = page_address(xor_srcs[src_idx]);
926 for (i = 0; i < PAGE_SIZE; i++)
927 ptr[i] = (1 << src_idx);
928 }
929
930 for (src_idx = 0; src_idx < IOP_ADMA_NUM_SRC_TEST; src_idx++)
931 cmp_byte ^= (u8) (1 << src_idx);
932
933 cmp_word = (cmp_byte << 24) | (cmp_byte << 16) |
934 (cmp_byte << 8) | cmp_byte;
935
936 memset(page_address(dest), 0, PAGE_SIZE);
937
938 dma_chan = container_of(device->common.channels.next,
939 struct dma_chan,
940 device_node);
941 if (iop_adma_alloc_chan_resources(dma_chan) < 1) {
942 err = -ENODEV;
943 goto out;
944 }
945
946 /* test xor */
947 dest_dma = dma_map_page(dma_chan->device->dev, dest, 0,
948 PAGE_SIZE, DMA_FROM_DEVICE);
949 for (i = 0; i < IOP_ADMA_NUM_SRC_TEST; i++)
950 dma_srcs[i] = dma_map_page(dma_chan->device->dev, xor_srcs[i],
951 0, PAGE_SIZE, DMA_TO_DEVICE);
952 tx = iop_adma_prep_dma_xor(dma_chan, dest_dma, dma_srcs,
953 IOP_ADMA_NUM_SRC_TEST, PAGE_SIZE,
954 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
955
956 cookie = iop_adma_tx_submit(tx);
957 iop_adma_issue_pending(dma_chan);
958 msleep(8);
959
960 if (iop_adma_is_complete(dma_chan, cookie, NULL, NULL) !=
961 DMA_SUCCESS) {
962 dev_printk(KERN_ERR, dma_chan->device->dev,
963 "Self-test xor timed out, disabling\n");
964 err = -ENODEV;
965 goto free_resources;
966 }
967
968 iop_chan = to_iop_adma_chan(dma_chan);
969 dma_sync_single_for_cpu(&iop_chan->device->pdev->dev, dest_dma,
970 PAGE_SIZE, DMA_FROM_DEVICE);
971 for (i = 0; i < (PAGE_SIZE / sizeof(u32)); i++) {
972 u32 *ptr = page_address(dest);
973 if (ptr[i] != cmp_word) {
974 dev_printk(KERN_ERR, dma_chan->device->dev,
975 "Self-test xor failed compare, disabling\n");
976 err = -ENODEV;
977 goto free_resources;
978 }
979 }
980 dma_sync_single_for_device(&iop_chan->device->pdev->dev, dest_dma,
981 PAGE_SIZE, DMA_TO_DEVICE);
982
983 /* skip zero sum if the capability is not present */
984 if (!dma_has_cap(DMA_ZERO_SUM, dma_chan->device->cap_mask))
985 goto free_resources;
986
987 /* zero sum the sources with the destintation page */
988 for (i = 0; i < IOP_ADMA_NUM_SRC_TEST; i++)
989 zero_sum_srcs[i] = xor_srcs[i];
990 zero_sum_srcs[i] = dest;
991
992 zero_sum_result = 1;
993
994 for (i = 0; i < IOP_ADMA_NUM_SRC_TEST + 1; i++)
995 dma_srcs[i] = dma_map_page(dma_chan->device->dev,
996 zero_sum_srcs[i], 0, PAGE_SIZE,
997 DMA_TO_DEVICE);
998 tx = iop_adma_prep_dma_zero_sum(dma_chan, dma_srcs,
999 IOP_ADMA_NUM_SRC_TEST + 1, PAGE_SIZE,
1000 &zero_sum_result,
1001 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1002
1003 cookie = iop_adma_tx_submit(tx);
1004 iop_adma_issue_pending(dma_chan);
1005 msleep(8);
1006
1007 if (iop_adma_is_complete(dma_chan, cookie, NULL, NULL) != DMA_SUCCESS) {
1008 dev_printk(KERN_ERR, dma_chan->device->dev,
1009 "Self-test zero sum timed out, disabling\n");
1010 err = -ENODEV;
1011 goto free_resources;
1012 }
1013
1014 if (zero_sum_result != 0) {
1015 dev_printk(KERN_ERR, dma_chan->device->dev,
1016 "Self-test zero sum failed compare, disabling\n");
1017 err = -ENODEV;
1018 goto free_resources;
1019 }
1020
1021 /* test memset */
1022 dma_addr = dma_map_page(dma_chan->device->dev, dest, 0,
1023 PAGE_SIZE, DMA_FROM_DEVICE);
1024 tx = iop_adma_prep_dma_memset(dma_chan, dma_addr, 0, PAGE_SIZE,
1025 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1026
1027 cookie = iop_adma_tx_submit(tx);
1028 iop_adma_issue_pending(dma_chan);
1029 msleep(8);
1030
1031 if (iop_adma_is_complete(dma_chan, cookie, NULL, NULL) != DMA_SUCCESS) {
1032 dev_printk(KERN_ERR, dma_chan->device->dev,
1033 "Self-test memset timed out, disabling\n");
1034 err = -ENODEV;
1035 goto free_resources;
1036 }
1037
1038 for (i = 0; i < PAGE_SIZE/sizeof(u32); i++) {
1039 u32 *ptr = page_address(dest);
1040 if (ptr[i]) {
1041 dev_printk(KERN_ERR, dma_chan->device->dev,
1042 "Self-test memset failed compare, disabling\n");
1043 err = -ENODEV;
1044 goto free_resources;
1045 }
1046 }
1047
1048 /* test for non-zero parity sum */
1049 zero_sum_result = 0;
1050 for (i = 0; i < IOP_ADMA_NUM_SRC_TEST + 1; i++)
1051 dma_srcs[i] = dma_map_page(dma_chan->device->dev,
1052 zero_sum_srcs[i], 0, PAGE_SIZE,
1053 DMA_TO_DEVICE);
1054 tx = iop_adma_prep_dma_zero_sum(dma_chan, dma_srcs,
1055 IOP_ADMA_NUM_SRC_TEST + 1, PAGE_SIZE,
1056 &zero_sum_result,
1057 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1058
1059 cookie = iop_adma_tx_submit(tx);
1060 iop_adma_issue_pending(dma_chan);
1061 msleep(8);
1062
1063 if (iop_adma_is_complete(dma_chan, cookie, NULL, NULL) != DMA_SUCCESS) {
1064 dev_printk(KERN_ERR, dma_chan->device->dev,
1065 "Self-test non-zero sum timed out, disabling\n");
1066 err = -ENODEV;
1067 goto free_resources;
1068 }
1069
1070 if (zero_sum_result != 1) {
1071 dev_printk(KERN_ERR, dma_chan->device->dev,
1072 "Self-test non-zero sum failed compare, disabling\n");
1073 err = -ENODEV;
1074 goto free_resources;
1075 }
1076
1077 free_resources:
1078 iop_adma_free_chan_resources(dma_chan);
1079 out:
1080 src_idx = IOP_ADMA_NUM_SRC_TEST;
1081 while (src_idx--)
1082 __free_page(xor_srcs[src_idx]);
1083 __free_page(dest);
1084 return err;
1085 }
1086
1087 static int __devexit iop_adma_remove(struct platform_device *dev)
1088 {
1089 struct iop_adma_device *device = platform_get_drvdata(dev);
1090 struct dma_chan *chan, *_chan;
1091 struct iop_adma_chan *iop_chan;
1092 int i;
1093 struct iop_adma_platform_data *plat_data = dev->dev.platform_data;
1094
1095 dma_async_device_unregister(&device->common);
1096
1097 for (i = 0; i < 3; i++) {
1098 unsigned int irq;
1099 irq = platform_get_irq(dev, i);
1100 free_irq(irq, device);
1101 }
1102
1103 dma_free_coherent(&dev->dev, plat_data->pool_size,
1104 device->dma_desc_pool_virt, device->dma_desc_pool);
1105
1106 do {
1107 struct resource *res;
1108 res = platform_get_resource(dev, IORESOURCE_MEM, 0);
1109 release_mem_region(res->start, res->end - res->start);
1110 } while (0);
1111
1112 list_for_each_entry_safe(chan, _chan, &device->common.channels,
1113 device_node) {
1114 iop_chan = to_iop_adma_chan(chan);
1115 list_del(&chan->device_node);
1116 kfree(iop_chan);
1117 }
1118 kfree(device);
1119
1120 return 0;
1121 }
1122
1123 static int __devinit iop_adma_probe(struct platform_device *pdev)
1124 {
1125 struct resource *res;
1126 int ret = 0, i;
1127 struct iop_adma_device *adev;
1128 struct iop_adma_chan *iop_chan;
1129 struct dma_device *dma_dev;
1130 struct iop_adma_platform_data *plat_data = pdev->dev.platform_data;
1131
1132 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1133 if (!res)
1134 return -ENODEV;
1135
1136 if (!devm_request_mem_region(&pdev->dev, res->start,
1137 res->end - res->start, pdev->name))
1138 return -EBUSY;
1139
1140 adev = kzalloc(sizeof(*adev), GFP_KERNEL);
1141 if (!adev)
1142 return -ENOMEM;
1143 dma_dev = &adev->common;
1144
1145 /* allocate coherent memory for hardware descriptors
1146 * note: writecombine gives slightly better performance, but
1147 * requires that we explicitly flush the writes
1148 */
1149 if ((adev->dma_desc_pool_virt = dma_alloc_writecombine(&pdev->dev,
1150 plat_data->pool_size,
1151 &adev->dma_desc_pool,
1152 GFP_KERNEL)) == NULL) {
1153 ret = -ENOMEM;
1154 goto err_free_adev;
1155 }
1156
1157 dev_dbg(&pdev->dev, "%s: allocted descriptor pool virt %p phys %p\n",
1158 __func__, adev->dma_desc_pool_virt,
1159 (void *) adev->dma_desc_pool);
1160
1161 adev->id = plat_data->hw_id;
1162
1163 /* discover transaction capabilites from the platform data */
1164 dma_dev->cap_mask = plat_data->cap_mask;
1165
1166 adev->pdev = pdev;
1167 platform_set_drvdata(pdev, adev);
1168
1169 INIT_LIST_HEAD(&dma_dev->channels);
1170
1171 /* set base routines */
1172 dma_dev->device_alloc_chan_resources = iop_adma_alloc_chan_resources;
1173 dma_dev->device_free_chan_resources = iop_adma_free_chan_resources;
1174 dma_dev->device_is_tx_complete = iop_adma_is_complete;
1175 dma_dev->device_issue_pending = iop_adma_issue_pending;
1176 dma_dev->dev = &pdev->dev;
1177
1178 /* set prep routines based on capability */
1179 if (dma_has_cap(DMA_MEMCPY, dma_dev->cap_mask))
1180 dma_dev->device_prep_dma_memcpy = iop_adma_prep_dma_memcpy;
1181 if (dma_has_cap(DMA_MEMSET, dma_dev->cap_mask))
1182 dma_dev->device_prep_dma_memset = iop_adma_prep_dma_memset;
1183 if (dma_has_cap(DMA_XOR, dma_dev->cap_mask)) {
1184 dma_dev->max_xor = iop_adma_get_max_xor();
1185 dma_dev->device_prep_dma_xor = iop_adma_prep_dma_xor;
1186 }
1187 if (dma_has_cap(DMA_ZERO_SUM, dma_dev->cap_mask))
1188 dma_dev->device_prep_dma_zero_sum =
1189 iop_adma_prep_dma_zero_sum;
1190 if (dma_has_cap(DMA_INTERRUPT, dma_dev->cap_mask))
1191 dma_dev->device_prep_dma_interrupt =
1192 iop_adma_prep_dma_interrupt;
1193
1194 iop_chan = kzalloc(sizeof(*iop_chan), GFP_KERNEL);
1195 if (!iop_chan) {
1196 ret = -ENOMEM;
1197 goto err_free_dma;
1198 }
1199 iop_chan->device = adev;
1200
1201 iop_chan->mmr_base = devm_ioremap(&pdev->dev, res->start,
1202 res->end - res->start);
1203 if (!iop_chan->mmr_base) {
1204 ret = -ENOMEM;
1205 goto err_free_iop_chan;
1206 }
1207 tasklet_init(&iop_chan->irq_tasklet, iop_adma_tasklet, (unsigned long)
1208 iop_chan);
1209
1210 /* clear errors before enabling interrupts */
1211 iop_adma_device_clear_err_status(iop_chan);
1212
1213 for (i = 0; i < 3; i++) {
1214 irq_handler_t handler[] = { iop_adma_eot_handler,
1215 iop_adma_eoc_handler,
1216 iop_adma_err_handler };
1217 int irq = platform_get_irq(pdev, i);
1218 if (irq < 0) {
1219 ret = -ENXIO;
1220 goto err_free_iop_chan;
1221 } else {
1222 ret = devm_request_irq(&pdev->dev, irq,
1223 handler[i], 0, pdev->name, iop_chan);
1224 if (ret)
1225 goto err_free_iop_chan;
1226 }
1227 }
1228
1229 spin_lock_init(&iop_chan->lock);
1230 INIT_LIST_HEAD(&iop_chan->chain);
1231 INIT_LIST_HEAD(&iop_chan->all_slots);
1232 INIT_RCU_HEAD(&iop_chan->common.rcu);
1233 iop_chan->common.device = dma_dev;
1234 list_add_tail(&iop_chan->common.device_node, &dma_dev->channels);
1235
1236 if (dma_has_cap(DMA_MEMCPY, dma_dev->cap_mask)) {
1237 ret = iop_adma_memcpy_self_test(adev);
1238 dev_dbg(&pdev->dev, "memcpy self test returned %d\n", ret);
1239 if (ret)
1240 goto err_free_iop_chan;
1241 }
1242
1243 if (dma_has_cap(DMA_XOR, dma_dev->cap_mask) ||
1244 dma_has_cap(DMA_MEMSET, dma_dev->cap_mask)) {
1245 ret = iop_adma_xor_zero_sum_self_test(adev);
1246 dev_dbg(&pdev->dev, "xor self test returned %d\n", ret);
1247 if (ret)
1248 goto err_free_iop_chan;
1249 }
1250
1251 dev_printk(KERN_INFO, &pdev->dev, "Intel(R) IOP: "
1252 "( %s%s%s%s%s%s%s%s%s%s)\n",
1253 dma_has_cap(DMA_PQ_XOR, dma_dev->cap_mask) ? "pq_xor " : "",
1254 dma_has_cap(DMA_PQ_UPDATE, dma_dev->cap_mask) ? "pq_update " : "",
1255 dma_has_cap(DMA_PQ_ZERO_SUM, dma_dev->cap_mask) ? "pq_zero_sum " : "",
1256 dma_has_cap(DMA_XOR, dma_dev->cap_mask) ? "xor " : "",
1257 dma_has_cap(DMA_DUAL_XOR, dma_dev->cap_mask) ? "dual_xor " : "",
1258 dma_has_cap(DMA_ZERO_SUM, dma_dev->cap_mask) ? "xor_zero_sum " : "",
1259 dma_has_cap(DMA_MEMSET, dma_dev->cap_mask) ? "fill " : "",
1260 dma_has_cap(DMA_MEMCPY_CRC32C, dma_dev->cap_mask) ? "cpy+crc " : "",
1261 dma_has_cap(DMA_MEMCPY, dma_dev->cap_mask) ? "cpy " : "",
1262 dma_has_cap(DMA_INTERRUPT, dma_dev->cap_mask) ? "intr " : "");
1263
1264 dma_async_device_register(dma_dev);
1265 goto out;
1266
1267 err_free_iop_chan:
1268 kfree(iop_chan);
1269 err_free_dma:
1270 dma_free_coherent(&adev->pdev->dev, plat_data->pool_size,
1271 adev->dma_desc_pool_virt, adev->dma_desc_pool);
1272 err_free_adev:
1273 kfree(adev);
1274 out:
1275 return ret;
1276 }
1277
1278 static void iop_chan_start_null_memcpy(struct iop_adma_chan *iop_chan)
1279 {
1280 struct iop_adma_desc_slot *sw_desc, *grp_start;
1281 dma_cookie_t cookie;
1282 int slot_cnt, slots_per_op;
1283
1284 dev_dbg(iop_chan->device->common.dev, "%s\n", __func__);
1285
1286 spin_lock_bh(&iop_chan->lock);
1287 slot_cnt = iop_chan_memcpy_slot_count(0, &slots_per_op);
1288 sw_desc = iop_adma_alloc_slots(iop_chan, slot_cnt, slots_per_op);
1289 if (sw_desc) {
1290 grp_start = sw_desc->group_head;
1291
1292 list_splice_init(&sw_desc->async_tx.tx_list, &iop_chan->chain);
1293 async_tx_ack(&sw_desc->async_tx);
1294 iop_desc_init_memcpy(grp_start, 0);
1295 iop_desc_set_byte_count(grp_start, iop_chan, 0);
1296 iop_desc_set_dest_addr(grp_start, iop_chan, 0);
1297 iop_desc_set_memcpy_src_addr(grp_start, 0);
1298
1299 cookie = iop_chan->common.cookie;
1300 cookie++;
1301 if (cookie <= 1)
1302 cookie = 2;
1303
1304 /* initialize the completed cookie to be less than
1305 * the most recently used cookie
1306 */
1307 iop_chan->completed_cookie = cookie - 1;
1308 iop_chan->common.cookie = sw_desc->async_tx.cookie = cookie;
1309
1310 /* channel should not be busy */
1311 BUG_ON(iop_chan_is_busy(iop_chan));
1312
1313 /* clear any prior error-status bits */
1314 iop_adma_device_clear_err_status(iop_chan);
1315
1316 /* disable operation */
1317 iop_chan_disable(iop_chan);
1318
1319 /* set the descriptor address */
1320 iop_chan_set_next_descriptor(iop_chan, sw_desc->async_tx.phys);
1321
1322 /* 1/ don't add pre-chained descriptors
1323 * 2/ dummy read to flush next_desc write
1324 */
1325 BUG_ON(iop_desc_get_next_desc(sw_desc));
1326
1327 /* run the descriptor */
1328 iop_chan_enable(iop_chan);
1329 } else
1330 dev_printk(KERN_ERR, iop_chan->device->common.dev,
1331 "failed to allocate null descriptor\n");
1332 spin_unlock_bh(&iop_chan->lock);
1333 }
1334
1335 static void iop_chan_start_null_xor(struct iop_adma_chan *iop_chan)
1336 {
1337 struct iop_adma_desc_slot *sw_desc, *grp_start;
1338 dma_cookie_t cookie;
1339 int slot_cnt, slots_per_op;
1340
1341 dev_dbg(iop_chan->device->common.dev, "%s\n", __func__);
1342
1343 spin_lock_bh(&iop_chan->lock);
1344 slot_cnt = iop_chan_xor_slot_count(0, 2, &slots_per_op);
1345 sw_desc = iop_adma_alloc_slots(iop_chan, slot_cnt, slots_per_op);
1346 if (sw_desc) {
1347 grp_start = sw_desc->group_head;
1348 list_splice_init(&sw_desc->async_tx.tx_list, &iop_chan->chain);
1349 async_tx_ack(&sw_desc->async_tx);
1350 iop_desc_init_null_xor(grp_start, 2, 0);
1351 iop_desc_set_byte_count(grp_start, iop_chan, 0);
1352 iop_desc_set_dest_addr(grp_start, iop_chan, 0);
1353 iop_desc_set_xor_src_addr(grp_start, 0, 0);
1354 iop_desc_set_xor_src_addr(grp_start, 1, 0);
1355
1356 cookie = iop_chan->common.cookie;
1357 cookie++;
1358 if (cookie <= 1)
1359 cookie = 2;
1360
1361 /* initialize the completed cookie to be less than
1362 * the most recently used cookie
1363 */
1364 iop_chan->completed_cookie = cookie - 1;
1365 iop_chan->common.cookie = sw_desc->async_tx.cookie = cookie;
1366
1367 /* channel should not be busy */
1368 BUG_ON(iop_chan_is_busy(iop_chan));
1369
1370 /* clear any prior error-status bits */
1371 iop_adma_device_clear_err_status(iop_chan);
1372
1373 /* disable operation */
1374 iop_chan_disable(iop_chan);
1375
1376 /* set the descriptor address */
1377 iop_chan_set_next_descriptor(iop_chan, sw_desc->async_tx.phys);
1378
1379 /* 1/ don't add pre-chained descriptors
1380 * 2/ dummy read to flush next_desc write
1381 */
1382 BUG_ON(iop_desc_get_next_desc(sw_desc));
1383
1384 /* run the descriptor */
1385 iop_chan_enable(iop_chan);
1386 } else
1387 dev_printk(KERN_ERR, iop_chan->device->common.dev,
1388 "failed to allocate null descriptor\n");
1389 spin_unlock_bh(&iop_chan->lock);
1390 }
1391
1392 static struct platform_driver iop_adma_driver = {
1393 .probe = iop_adma_probe,
1394 .remove = iop_adma_remove,
1395 .driver = {
1396 .owner = THIS_MODULE,
1397 .name = "iop-adma",
1398 },
1399 };
1400
1401 static int __init iop_adma_init (void)
1402 {
1403 return platform_driver_register(&iop_adma_driver);
1404 }
1405
1406 /* it's currently unsafe to unload this module */
1407 #if 0
1408 static void __exit iop_adma_exit (void)
1409 {
1410 platform_driver_unregister(&iop_adma_driver);
1411 return;
1412 }
1413 module_exit(iop_adma_exit);
1414 #endif
1415
1416 module_init(iop_adma_init);
1417
1418 MODULE_AUTHOR("Intel Corporation");
1419 MODULE_DESCRIPTION("IOP ADMA Engine Driver");
1420 MODULE_LICENSE("GPL");
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